- For all Keystone1 devices (except C6657):
Figure: High Level Diagram
- ETB Half-Full and Full interrupts are enabled as 2 different system event inputs to chip-level interrupt controller INTC1 and combined to single output
- 19 INTC1 outputs (2-20) can be used as inputs to the EDMA3 Channel Controller TPCC1 (45-63)
- Each ETB event through INTC1 to TPCC1 will initiate a transfer request for half the size of the ETB
- ETB has a maximum burst size of 1KB
- DMA transfers half of ETB in 1KB frames
- 1 DMA channel used to transfer ETB data
- 1 DMA channel used to clear the interrupt status register in the INTC1
Figure: Components
- API Inputs
- TPCC - EDMA3 Channel Controller (0-2)
- DMA Channel 1 - channel used to clear chip-level interrupt
- DMA Channel 2 - channel used to transfer ETB data
- PaRAM numbers - 3 Parameter RAM (PaRAM) entry numbers
- There are an additional 2 PaRAMs that are mapped by the application for the 2 DMA channels, the API reads the mapping register to determine the entry numbers
- Drain Buffer Address - starting address for the memory buffer
- Drain Buffer Size - size in words for the memory buffer
- DMA Mode - set the memory buffer as circular or stop when full
- Application Configuration Requirements
- DMA channel to PaRAM mapping for 2 DMA channels
- DMA channel to Transfer Controller (TPTCx) assignment
- All DMA channels at reset are assigned to TPTC0
- Map INTC1 inputs (ETB events) to output (host) channel
- Enable INTC1 input/outputs and Global host interrupt enable
Figure: Parameter RAMs
- 5 PaRAMs required
- 2 mapped to DMA channels (CLR1 & ETB1)
- 3 additional for linking/chaining (CLR2, ETB2, & ETB3)
- CLRx PaRAM configuration
- Initiated by ETB event
- Writes register to clear INTC1 interrupt
- CLR1 PaRAM is reloaded with values in CLR2 when transfer completes
- ETBx PaRAM configuration
- Half ETB transferred in 1KByte frames per event
- Total transfer count is the number of ETB halves that fit into the provided drain buffer
- When all transfers into drain buffer are complete, ETB2 linked to start a memory to memory transfer for a buffer wrapped flag
- Chain event from ETB1 starts the transfer
- After the wrap flag transfer completes, if the buffer is configured for circular mode, ETB3 reloads ETB1 with initial configuration
The DMA channels that are specified in the DMA configuration structure must be channels that exist in the specified channel controller (cc) parameter.
- Application Requirements for using EDMA3 Drain Buffer
- The memory section "ETBLib_dmaData" should be non-cacheable and can be placed in local L2, MSMC or DDR3 memory.
- Configure the PaRAM to DMA channel mapping registers.
- Configure the INTC1 Channel Map Registers.
- Configure the INTC1 input and output enable registers.
- Call the ETB_config_dma function after ETB_open and before ETB_enable.
- Call the ETB_flush function after tracing has stopped.
- Call the ETB_flush_dma function after ETB_flush and before ETB_read.
- For all Keystone2 devices and C6657:
In all keystone2 and C6657 devices, the ETB half-full and full events are directly hooked up to the EDMA3 CC. Hence, there is no need to route the ETB events via the chip interrupt controller (CIC).
Figure: Keystone2 and C6657 Parameter RAMs
- 3 PaRAMs required
- 1 mapped to DMA channels (ETB1)
- 2 additional for linking/chaining (ETB2, & ETB3)
- ETBx PaRAM configuration
- Half ETB transferred in 1KByte frames per event
- Total transfer count is the number of ETB halves that fit into the provided drain buffer
- When all transfers into drain buffer are complete, ETB2 linked to start a memory to memory transfer for a buffer wrapped flag
- Chain event from ETB1 starts the transfer
- After the wrap flag transfer completes, if the buffer is configured for circular mode, ETB3 reloads ETB1 with initial configuration
- Application Requirements for using EDMA3 Drain Buffer
- The memory section "ETBLib_dmaData" should be non-cacheable and can be placed in local L2, MSMC or DDR3 memory.
- Application needs to provide three PaRAMs associated with EDMA3 CC to which the required ETB events are connected.
- Please, refer to keystone2 and C6657 datasheet for determining the EDMA3 CC to which the required ETB events are connected.
- Call the ETB_config_dma function after ETB_open and before ETB_enable.
- Call the ETB_flush function after tracing has stopped.
- Call the ETB_flush_dma function after ETB_flush and before ETB_read.