ETB Library
ETB-EDMA3 Drain Buffer Details
For all Keystone1 devices (except C6657):
ETB-EDMA3_HighLevel.jpg
Figure: High Level Diagram
ETB-EDMA3_Components.jpg
Figure: Components
ETB-EDMA3_PaRAMs.jpg
Figure: Parameter RAMs



The DMA channels that are specified in the DMA configuration structure must be channels that exist in the specified channel controller (cc) parameter.

Application Requirements for using EDMA3 Drain Buffer
  • The memory section "ETBLib_dmaData" should be non-cacheable and can be placed in local L2, MSMC or DDR3 memory.
  • Configure the PaRAM to DMA channel mapping registers.
  • Configure the INTC1 Channel Map Registers.
  • Configure the INTC1 input and output enable registers.
  • Call the ETB_config_dma function after ETB_open and before ETB_enable.
  • Call the ETB_flush function after tracing has stopped.
  • Call the ETB_flush_dma function after ETB_flush and before ETB_read.
For all Keystone2 devices and C6657:

In all keystone2 and C6657 devices, the ETB half-full and full events are directly hooked up to the EDMA3 CC. Hence, there is no need to route the ETB events via the chip interrupt controller (CIC).

ETB-EDMA3_PaRAMs_K2.jpg
Figure: Keystone2 and C6657 Parameter RAMs
Application Requirements for using EDMA3 Drain Buffer
  • The memory section "ETBLib_dmaData" should be non-cacheable and can be placed in local L2, MSMC or DDR3 memory.
  • Application needs to provide three PaRAMs associated with EDMA3 CC to which the required ETB events are connected.
  • Please, refer to keystone2 and C6657 datasheet for determining the EDMA3 CC to which the required ETB events are connected.
  • Call the ETB_config_dma function after ETB_open and before ETB_enable.
  • Call the ETB_flush function after tracing has stopped.
  • Call the ETB_flush_dma function after ETB_flush and before ETB_read.