Common Platform (CP) Tracer Library API Reference Guide (66AK2Gxx Version)
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CPT_Common.h
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1 #ifndef __CPT_COMMON_H
2 #define __CPT_COMMON_H
3 /*
4  * CPT_Common.h
5  *
6  * Common Platform (CP) Tracer Library Common definitions
7  *
8  * Copyright (C) 2009, 2010 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  *
15  * Redistributions of source code must retain the above copyright
16  * notice, this list of conditions and the following disclaimer.
17  *
18  * Redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the
21  * distribution.
22  *
23  * Neither the name of Texas Instruments Incorporated nor the names ofTC0
24  * its contributors may be used to endorse or promote products derived
25  * from this software without specific prior written permission.
26  *
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
40 
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47 
48 #ifndef _DOXYGEN_IGNORE
49 
50 #include <stdint.h>
51 
53 //
54 // Private Typedefs
55 //
57 
58 // CP Tracer register typedef
59 typedef volatile uint32_t reg32_t;
60 
62 //
63 // Private Definitions
64 //
66 
67 // Mutex ID definitions
68 
69 #define CPT_MUTEXID_MAJOR 1
70 #define CPT_MUTEXID_MINOR_MASK 0xFFFF
71 #define CPT_MUTEXID(CPT_ModId) (CPT_MUTEXID_MAJOR | (CPT_MUTEXID_MINOR_MASK & CPT_ModId))
72 
74 // Private device specific data
76 
77 typedef struct _eCPT_MultiMID {
78 #ifndef RUNTIME_DEVICE_SELECT
79  eCPT_MasterID Base_MID;
80 #else
81  int Base_MID;
82 #endif
83  int8_t NumMasterIDs; // Always 32 or less
84 }CPT_MultiMID_t;
85 
86 // Meta data Attribute definitions
87 
88 #define CPT_ATTR_BUFSIZE 256
89 
90 #if defined(_C6670)
91 
92 #ifdef _STM_Logging
93 static const char CPT_ModName_MSMC_0[] = "MSMC_0";
94 static const char CPT_ModName_MSMC_1[] = "MSMC_1";
95 static const char CPT_ModName_MSMC_2[] = "MSMC_2";
96 static const char CPT_ModName_MSMC_3[] = "MSMC_3";
97 static const char CPT_ModName_QM_MST[] = "QM_M";
98 static const char CPT_ModName_DDR[] = "DDR";
99 static const char CPT_ModName_SM[] = "SM";
100 static const char CPT_ModName_QM_CFG[] = "QM_CFG";
101 static const char CPT_ModName_CFG[] = "CFG";
102 static const char CPT_ModName_L2_0[] = "L2_0";
103 static const char CPT_ModName_L2_1[] = "L2_1";
104 static const char CPT_ModName_L2_2[] = "L2_2";
105 static const char CPT_ModName_L2_3[] = "L2_3";
106 static const char CPT_ModName_RAC[] = "RAC";
107 static const char CPT_ModName_RAC_CFG[] = "RAC_CFG";
108 static const char CPT_ModName_TAC[] = "TAC";
109 
110 //CP Tracer module mame strings indexed by eCPT_ModID
111 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
112  CPT_ModName_MSMC_1,
113  CPT_ModName_MSMC_2,
114  CPT_ModName_MSMC_3,
115  CPT_ModName_QM_MST,
116  CPT_ModName_DDR,
117  CPT_ModName_SM,
118  CPT_ModName_QM_CFG,
119  CPT_ModName_CFG,
120  CPT_ModName_L2_0,
121  CPT_ModName_L2_1,
122  CPT_ModName_L2_2,
123  CPT_ModName_L2_3,
124  CPT_ModName_RAC,
125  CPT_ModName_RAC_CFG,
126  CPT_ModName_TAC
127  };
128 
129 #endif //_STM_Logging
130 
131 
132 //Nyquist CP Tracer Address Table indexed by eCPT_ModID
133 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000, // eCPT_MSMC_0
134  0x01d08000, // eCPT_MSMC_1
135  0x01d10000, // eCPT_MSMC_2
136  0x01d18000, // eCPT_MSMC_3
137  0x01d20000, // eCPT_QM_MST
138  0x01d28000, // eCPT_DDR
139  0x01d30000, // eCPT_SM
140  0x01d38000, // eCPT_QM_PRI
141  0x01d40000, // eCPT_SCR3_CFG
142  0x01d48000, // eCPT_L2_0
143  0x01d50000, // eCPT_L2_1
144  0x01d58000, // eCPT_L2_2
145  0x01d60000, // eCPT_L2_3
146  0x01d68000, // eCPT_RAC
147  0x01d70000, // eCPT_RAC_CFG
148  0x01d78000 // eCPT_TAC
149  };
150 
151 //Nyquist CP Tracer clock rate divide-by-factors indexed by eCPT_ModID
152 const uint8_t CPT_ModDivByFactors[] = { 2, // eCPT_MSMC_0
153  2, // eCPT_MSMC_1
154  2, // eCPT_MSMC_2
155  2, // eCPT_MSMC_3
156  3, // eCPT_QM_MST
157  2, // eCPT_DDR
158  3, // eCPT_SM
159  3, // eCPT_QM_PRI
160  3, // eCPT_SCR3_CFG
161  3, // eCPT_L2_0
162  3, // eCPT_L2_1
163  3, // eCPT_L2_2
164  3, // eCPT_L2_3
165  3, // eCPT_RAC
166  3, // eCPT_RAC_CFG
167  3 // eCPT_TAC
168  };
169 
170 
171 
172 
173 const CPT_MultiMID_t CPT_MultiMID[] = { eCPT_MID_SRIO_PKTDMA_Grp0,
174  2,
175  eCPT_MID_QM_SS_Grp0,
176  4,
177  eCPT_MID_AIF_Grp0,
178  8,
179  eCPT_MID_QM_CDMA_Grp0,
180  4,
181  eCPT_MID_NETCP_Grp0,
182  2
183  };
184 #endif
185 #if defined(_C6671)
186 
187 #ifdef _STM_Logging
188 static const char CPT_ModName_MSMC_0[] = "MSMC_0";
189 static const char CPT_ModName_MSMC_1[] = "MSMC_1";
190 static const char CPT_ModName_MSMC_2[] = "MSMC_2";
191 static const char CPT_ModName_MSMC_3[] = "MSMC_3";
192 static const char CPT_ModName_QM_MST[] = "QM_M";
193 static const char CPT_ModName_DDR[] = "DDR";
194 static const char CPT_ModName_SM[] = "SM";
195 static const char CPT_ModName_QM_CFG[] = "QM_CFG";
196 static const char CPT_ModName_CFG[] = "CFG";
197 static const char CPT_ModName_L2_0[] = "L2_0";
198 
199 
200 //CP Tracer module mame strings indexed by eCPT_ModID
201 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
202  CPT_ModName_MSMC_1,
203  CPT_ModName_MSMC_2,
204  CPT_ModName_MSMC_3,
205  CPT_ModName_QM_MST,
206  CPT_ModName_DDR,
207  CPT_ModName_SM,
208  CPT_ModName_QM_CFG,
209  CPT_ModName_CFG,
210  CPT_ModName_L2_0
211  };
212 
213 #endif
214 
215 
216 //Nyquist CP Tracer Address Table indexed by eCPT_ModID
217 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000, // eCPT_MSMC_0
218  0x01d08000, // eCPT_MSMC_1
219  0x01d10000, // eCPT_MSMC_2
220  0x01d18000, // eCPT_MSMC_3
221  0x01d20000, // eCPT_QM_MST
222  0x01d28000, // eCPT_DDR
223  0x01d30000, // eCPT_SM
224  0x01d38000, // eCPT_QM_PRI
225  0x01d40000, // eCPT_SCR3_CFG
226  0x01d48000 // eCPT_L2_0
227  };
228 
229 //Nyquist CP Tracer clock rate divide-by-factors indexed by eCPT_ModID
230 const uint8_t CPT_ModDivByFactors[] = { 2, // eCPT_MSMC_0
231  2, // eCPT_MSMC_1
232  2, // eCPT_MSMC_2
233  2, // eCPT_MSMC_3
234  3, // eCPT_QM_MST
235  2, // eCPT_DDR
236  3, // eCPT_SM
237  3, // eCPT_QM_PRI
238  3, // eCPT_SCR3_CFG
239  3 // eCPT_L2_0
240  };
241 
242 
243 
244 
245 const CPT_MultiMID_t CPT_MultiMID[] = { eCPT_MID_SRIO_PKTDMA_Grp0,
246  2,
247  eCPT_MID_QM_CDMA_Grp0,
248  4,
249  eCPT_MID_QM_second_Grp0,
250  2,
251  eCPT_MID_NETCP_Grp0,
252  4
253  };
254 #endif
255 #if defined(_C6672)
256 
257 #ifdef _STM_Logging
258 static const char CPT_ModName_MSMC_0[] = "MSMC_0";
259 static const char CPT_ModName_MSMC_1[] = "MSMC_1";
260 static const char CPT_ModName_MSMC_2[] = "MSMC_2";
261 static const char CPT_ModName_MSMC_3[] = "MSMC_3";
262 static const char CPT_ModName_QM_MST[] = "QM_M";
263 static const char CPT_ModName_DDR[] = "DDR";
264 static const char CPT_ModName_SM[] = "SM";
265 static const char CPT_ModName_QM_CFG[] = "QM_CFG";
266 static const char CPT_ModName_CFG[] = "CFG";
267 static const char CPT_ModName_L2_0[] = "L2_0";
268 static const char CPT_ModName_L2_1[] = "L2_1";
269 
270 
271 //CP Tracer module mame strings indexed by eCPT_ModID
272 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
273  CPT_ModName_MSMC_1,
274  CPT_ModName_MSMC_2,
275  CPT_ModName_MSMC_3,
276  CPT_ModName_QM_MST,
277  CPT_ModName_DDR,
278  CPT_ModName_SM,
279  CPT_ModName_QM_CFG,
280  CPT_ModName_CFG,
281  CPT_ModName_L2_0,
282  CPT_ModName_L2_1
283  };
284 
285 #endif
286 
287 
288 //Nyquist CP Tracer Address Table indexed by eCPT_ModID
289 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000, // eCPT_MSMC_0
290  0x01d08000, // eCPT_MSMC_1
291  0x01d10000, // eCPT_MSMC_2
292  0x01d18000, // eCPT_MSMC_3
293  0x01d20000, // eCPT_QM_MST
294  0x01d28000, // eCPT_DDR
295  0x01d30000, // eCPT_SM
296  0x01d38000, // eCPT_QM_PRI
297  0x01d40000, // eCPT_SCR3_CFG
298  0x01d48000, // eCPT_L2_0
299  0x01d50000 // eCPT_L2_1
300  };
301 
302 //Nyquist CP Tracer clock rate divide-by-factors indexed by eCPT_ModID
303 const uint8_t CPT_ModDivByFactors[] = { 2, // eCPT_MSMC_0
304  2, // eCPT_MSMC_1
305  2, // eCPT_MSMC_2
306  2, // eCPT_MSMC_3
307  3, // eCPT_QM_MST
308  2, // eCPT_DDR
309  3, // eCPT_SM
310  3, // eCPT_QM_PRI
311  3, // eCPT_SCR3_CFG
312  3, // eCPT_L2_0
313  3 // eCPT_L2_1
314  };
315 
316 
317 
318 
319 const CPT_MultiMID_t CPT_MultiMID[] = { eCPT_MID_SRIO_PKTDMA_Grp0,
320  2,
321  eCPT_MID_QM_CDMA_Grp0,
322  4,
323  eCPT_MID_QM_second_Grp0,
324  2,
325  eCPT_MID_NETCP_Grp0,
326  4
327  };
328 #endif
329 #if defined(_C6674)
330 
331 #ifdef _STM_Logging
332 static const char CPT_ModName_MSMC_0[] = "MSMC_0";
333 static const char CPT_ModName_MSMC_1[] = "MSMC_1";
334 static const char CPT_ModName_MSMC_2[] = "MSMC_2";
335 static const char CPT_ModName_MSMC_3[] = "MSMC_3";
336 static const char CPT_ModName_QM_MST[] = "QM_M";
337 static const char CPT_ModName_DDR[] = "DDR";
338 static const char CPT_ModName_SM[] = "SM";
339 static const char CPT_ModName_QM_CFG[] = "QM_CFG";
340 static const char CPT_ModName_CFG[] = "CFG";
341 static const char CPT_ModName_L2_0[] = "L2_0";
342 static const char CPT_ModName_L2_1[] = "L2_1";
343 static const char CPT_ModName_L2_2[] = "L2_2";
344 static const char CPT_ModName_L2_3[] = "L2_3";
345 
346 
347 //CP Tracer module mame strings indexed by eCPT_ModID
348 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
349  CPT_ModName_MSMC_1,
350  CPT_ModName_MSMC_2,
351  CPT_ModName_MSMC_3,
352  CPT_ModName_QM_MST,
353  CPT_ModName_DDR,
354  CPT_ModName_SM,
355  CPT_ModName_QM_CFG,
356  CPT_ModName_CFG,
357  CPT_ModName_L2_0,
358  CPT_ModName_L2_1,
359  CPT_ModName_L2_2,
360  CPT_ModName_L2_3
361  };
362 
363 #endif
364 
365 
366 //Nyquist CP Tracer Address Table indexed by eCPT_ModID
367 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000, // eCPT_MSMC_0
368  0x01d08000, // eCPT_MSMC_1
369  0x01d10000, // eCPT_MSMC_2
370  0x01d18000, // eCPT_MSMC_3
371  0x01d20000, // eCPT_QM_MST
372  0x01d28000, // eCPT_DDR
373  0x01d30000, // eCPT_SM
374  0x01d38000, // eCPT_QM_PRI
375  0x01d40000, // eCPT_SCR3_CFG
376  0x01d48000, // eCPT_L2_0
377  0x01d50000, // eCPT_L2_1
378  0x01d58000, // eCPT_L2_2
379  0x01d60000 // eCPT_L2_3
380  };
381 
382 //Nyquist CP Tracer clock rate divide-by-factors indexed by eCPT_ModID
383 const uint8_t CPT_ModDivByFactors[] = { 2, // eCPT_MSMC_0
384  2, // eCPT_MSMC_1
385  2, // eCPT_MSMC_2
386  2, // eCPT_MSMC_3
387  3, // eCPT_QM_MST
388  2, // eCPT_DDR
389  3, // eCPT_SM
390  3, // eCPT_QM_PRI
391  3, // eCPT_SCR3_CFG
392  3, // eCPT_L2_0
393  3, // eCPT_L2_1
394  3, // eCPT_L2_2
395  3 // eCPT_L2_3
396  };
397 
398 
399 
400 
401 const CPT_MultiMID_t CPT_MultiMID[] = { eCPT_MID_SRIO_PKTDMA_Grp0,
402  2,
403  eCPT_MID_QM_CDMA_Grp0,
404  4,
405  eCPT_MID_QM_second_Grp0,
406  2,
407  eCPT_MID_NETCP_Grp0,
408  4
409  };
410 #endif
411 #if defined(_C6678)
412 
413 #ifdef _STM_Logging
414 static const char CPT_ModName_MSMC_0[] = "MSMC_0";
415 static const char CPT_ModName_MSMC_1[] = "MSMC_1";
416 static const char CPT_ModName_MSMC_2[] = "MSMC_2";
417 static const char CPT_ModName_MSMC_3[] = "MSMC_3";
418 static const char CPT_ModName_QM_MST[] = "QM_M";
419 static const char CPT_ModName_DDR[] = "DDR";
420 static const char CPT_ModName_SM[] = "SM";
421 static const char CPT_ModName_QM_CFG[] = "QM_CFG";
422 static const char CPT_ModName_CFG[] = "CFG";
423 static const char CPT_ModName_L2_0[] = "L2_0";
424 static const char CPT_ModName_L2_1[] = "L2_1";
425 static const char CPT_ModName_L2_2[] = "L2_2";
426 static const char CPT_ModName_L2_3[] = "L2_3";
427 static const char CPT_ModName_L2_4[] = "L2_4";
428 static const char CPT_ModName_L2_5[] = "L2_5";
429 static const char CPT_ModName_L2_6[] = "L2_6";
430 static const char CPT_ModName_L2_7[] = "L2_7";
431 
432 
433 //CP Tracer module mame strings indexed by eCPT_ModID
434 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
435  CPT_ModName_MSMC_1,
436  CPT_ModName_MSMC_2,
437  CPT_ModName_MSMC_3,
438  CPT_ModName_QM_MST,
439  CPT_ModName_DDR,
440  CPT_ModName_SM,
441  CPT_ModName_QM_CFG,
442  CPT_ModName_CFG,
443  CPT_ModName_L2_0,
444  CPT_ModName_L2_1,
445  CPT_ModName_L2_2,
446  CPT_ModName_L2_3,
447  CPT_ModName_L2_4,
448  CPT_ModName_L2_5,
449  CPT_ModName_L2_6,
450  CPT_ModName_L2_7
451  };
452 
453 #endif
454 
455 
456 //Nyquist CP Tracer Address Table indexed by eCPT_ModID
457 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000, // eCPT_MSMC_0
458  0x01d08000, // eCPT_MSMC_1
459  0x01d10000, // eCPT_MSMC_2
460  0x01d18000, // eCPT_MSMC_3
461  0x01d20000, // eCPT_QM_MST
462  0x01d28000, // eCPT_DDR
463  0x01d30000, // eCPT_SM
464  0x01d38000, // eCPT_QM_PRI
465  0x01d40000, // eCPT_SCR3_CFG
466  0x01d48000, // eCPT_L2_0
467  0x01d50000, // eCPT_L2_1
468  0x01d58000, // eCPT_L2_2
469  0x01d60000, // eCPT_L2_3
470  0x01d68000, // eCPT_L2_4
471  0x01d70000, // eCPT_L2_5
472  0x01d78000, // eCPT_L2_6
473  0x01d80000 // eCPT_L2_7
474  };
475 
476 //Nyquist CP Tracer clock rate divide-by-factors indexed by eCPT_ModID
477 const uint8_t CPT_ModDivByFactors[] = { 2, // eCPT_MSMC_0
478  2, // eCPT_MSMC_1
479  2, // eCPT_MSMC_2
480  2, // eCPT_MSMC_3
481  3, // eCPT_QM_MST
482  2, // eCPT_DDR
483  3, // eCPT_SM
484  3, // eCPT_QM_PRI
485  3, // eCPT_SCR3_CFG
486  3, // eCPT_L2_0
487  3, // eCPT_L2_1
488  3, // eCPT_L2_2
489  3, // eCPT_L2_3
490  3, // eCPT_L2_4
491  3, // eCPT_L2_5
492  3, // eCPT_L2_6
493  3 // eCPT_L2_7
494  };
495 
496 
497 
498 
499 const CPT_MultiMID_t CPT_MultiMID[] = { eCPT_MID_SRIO_PKTDMA_Grp0,
500  2,
501  eCPT_MID_QM_CDMA_Grp0,
502  4,
503  eCPT_MID_QM_second_Grp0,
504  2,
505  eCPT_MID_NETCP_Grp0,
506  4
507  };
508 
509 #endif
510 #if defined(_C6657)
511 
512 #ifdef _STM_Logging
513 static const char CPT_ModName_MSMC_0[] = "MSMC_0";
514 static const char CPT_ModName_MSMC_1[] = "MSMC_1";
515 static const char CPT_ModName_MSMC_2[] = "MSMC_2";
516 static const char CPT_ModName_MSMC_3[] = "MSMC_3";
517 static const char CPT_ModName_QM_MST[] = "QM_M";
518 static const char CPT_ModName_DDR[] = "DDR";
519 static const char CPT_ModName_SM[] = "SM";
520 static const char CPT_ModName_QM_CFG[] = "QM_P"; //for 6670 was called QM_CFG
521 static const char CPT_ModName_CFG[] = "CFG";
522 static const char CPT_ModName_L2_0[] = "L2_0";
523 static const char CPT_ModName_L2_1[] = "L2_1";
524 static const char CPT_ModName_SCR_6P_A[] = "SCR_6P_A";
525 
526 //CP Tracer module mame strings indexed by eCPT_ModID
527 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
528  CPT_ModName_MSMC_1,
529  CPT_ModName_MSMC_2,
530  CPT_ModName_MSMC_3,
531  CPT_ModName_QM_MST,
532  CPT_ModName_DDR,
533  CPT_ModName_SM,
534  CPT_ModName_QM_CFG,
535  CPT_ModName_CFG,
536  CPT_ModName_L2_0,
537  CPT_ModName_L2_1,
538  CPT_ModName_SCR_6P_A
539  };
540 
541 #endif
542 
543 
544 //Nyquist CP Tracer Address Table indexed by eCPT_ModID
545 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000, // eCPT_MSMC_0
546  0x01d08000, // eCPT_MSMC_1
547  0x01d10000, // eCPT_MSMC_2
548  0x01d18000, // eCPT_MSMC_3
549  0x01d20000, // eCPT_QM_MST
550  0x01d28000, // eCPT_DDR
551  0x01d30000, // eCPT_SM
552  0x01d38000, // eCPT_QM_PRI
553  0x01d40000, // eCPT_SCR3_CFG
554  0x01d48000, // eCPT_L2_0
555  0x01d50000, // eCPT_L2_1
556  0x01d58000 //eCPT_SCR_6P_A
557  };
558 
559 //Nyquist CP Tracer clock rate divide-by-factors indexed by eCPT_ModID
560 const uint8_t CPT_ModDivByFactors[] = { 2, // eCPT_MSMC_0
561  2, // eCPT_MSMC_1
562  2, // eCPT_MSMC_2
563  2, // eCPT_MSMC_3
564  3, // eCPT_QM_MST
565  2, // eCPT_DDR
566  3, // eCPT_SM
567  3, // eCPT_QM_PRI
568  3, // eCPT_SCR3_CFG
569  3, // eCPT_L2_0
570  3, // eCPT_L2_1
571  3 // eCPT_SCR_6P_A
572  };
573 
574 
575 
576 
577 const CPT_MultiMID_t CPT_MultiMID[] = { eCPT_MID_SRIO_PKTDMA_Grp0,
578  2,
579  eCPT_MID_EMAC_0,
580  4,
581  eCPT_MID_QM_CDMA_Grp0,
582  4,
583  eCPT_MID_QM_second_Grp0,
584  2
585  };
586 #endif
587 #if defined(_TCI6614)
588 
589 #if defined(_STM_Logging) || defined(RUNTIME_DEVICE_SELECT)
590 static const char CPT_TCI6614_ModName_MSMC_0[] = "MSMC_0";
591 static const char CPT_TCI6614_ModName_MSMC_1[] = "MSMC_1";
592 static const char CPT_TCI6614_ModName_MSMC_2[] = "MSMC_2";
593 static const char CPT_TCI6614_ModName_MSMC_3[] = "MSMC_3";
594 static const char CPT_TCI6614_ModName_QM_MST[] = "QM_M";
595 static const char CPT_TCI6614_ModName_DDR[] = "DDR";
596 static const char CPT_TCI6614_ModName_SM[] = "SM";
597 static const char CPT_TCI6614_ModName_QM_CFG[] = "QM_CFG";
598 static const char CPT_TCI6614_ModName_CFG[] = "CFG";
599 static const char CPT_TCI6614_ModName_L2_0[] = "L2_0";
600 static const char CPT_TCI6614_ModName_L2_1[] = "L2_1";
601 static const char CPT_TCI6614_ModName_L2_2[] = "L2_2";
602 static const char CPT_TCI6614_ModName_L2_3[] = "L2_3";
603 static const char CPT_TCI6614_ModName_RAC[] = "RAC";
604 static const char CPT_TCI6614_ModName_RAC_CFG[] = "RAC_CFG";
605 static const char CPT_TCI6614_ModName_TAC[] = "TAC";
606 static const char CPT_TCI6614_ModName_SCR_6P_A[] = "SCR_6P_A";
607 static const char CPT_TCI6614_ModName_DDR_2[] = "DDR_2";
608 
609 //CP Tracer module mame strings indexed by eCPT_ModID
610 #ifdef RUNTIME_DEVICE_SELECT
611 const char * pCPT_TCI6614_ModNames[] = {
612 #else
613 const char * pCPT_ModNames[] = {
614 #endif
615  CPT_TCI6614_ModName_MSMC_0,
616  CPT_TCI6614_ModName_MSMC_1,
617  CPT_TCI6614_ModName_MSMC_2,
618  CPT_TCI6614_ModName_MSMC_3,
619  CPT_TCI6614_ModName_QM_MST,
620  CPT_TCI6614_ModName_DDR,
621  CPT_TCI6614_ModName_SM,
622  CPT_TCI6614_ModName_QM_CFG,
623  CPT_TCI6614_ModName_CFG,
624  CPT_TCI6614_ModName_L2_0,
625  CPT_TCI6614_ModName_L2_1,
626  CPT_TCI6614_ModName_L2_2,
627  CPT_TCI6614_ModName_L2_3,
628  CPT_TCI6614_ModName_RAC,
629  CPT_TCI6614_ModName_RAC_CFG,
630  CPT_TCI6614_ModName_TAC,
631  CPT_TCI6614_ModName_SCR_6P_A,
632  CPT_TCI6614_ModName_DDR_2
633  };
634 
635 #endif //_STM_Logging
636 
637 
638 //CP Tracer Address Table indexed by eCPT_ModID
639 #ifdef RUNTIME_DEVICE_SELECT
640 const uint32_t CPT_TCI6614_BaseAddressTable[] = {
641 #else
642 const uint32_t CPT_BaseAddressTable[] = {
643 #endif
644  0x01d00000, // eCPT_MSMC_0
645  0x01d08000, // eCPT_MSMC_1
646  0x01d10000, // eCPT_MSMC_2
647  0x01d18000, // eCPT_MSMC_3
648  0x01d20000, // eCPT_QM_MST
649  0x01d28000, // eCPT_DDR
650  0x01d30000, // eCPT_SM
651  0x01d38000, // eCPT_QM_PRI
652  0x01d40000, // eCPT_SCR3_CFG
653  0x01d48000, // eCPT_L2_0
654  0x01d50000, // eCPT_L2_1
655  0x01d58000, // eCPT_L2_2
656  0x01d60000, // eCPT_L2_3
657  0x01d68000, // eCPT_RAC
658  0x01d70000, // eCPT_RAC_CFG
659  0x01d78000, // eCPT_TAC
660  0x01D80000, //eCPT_SCR_6P_A
661  0x01D88000 //eCPT_DDR_2
662  };
663 
664 //CP Tracer clock rate divide-by-factors indexed by eCPT_ModID
665 #ifdef RUNTIME_DEVICE_SELECT
666 const uint8_t CPT_TCI6614_ModDivByFactors[] = {
667 #else
668 const uint8_t CPT_ModDivByFactors[] = {
669 #endif
670  2, // eCPT_MSMC_0
671  2, // eCPT_MSMC_1
672  2, // eCPT_MSMC_2
673  2, // eCPT_MSMC_3
674  3, // eCPT_QM_MST
675  2, // eCPT_DDR
676  3, // eCPT_SM
677  3, // eCPT_QM_PRI
678  3, // eCPT_SCR3_CFG
679  3, // eCPT_L2_0
680  3, // eCPT_L2_1
681  3, // eCPT_L2_2
682  3, // eCPT_L2_3
683  3, // eCPT_RAC
684  3, // eCPT_RAC_CFG
685  3, // eCPT_TAC
686  3, // eCPT_SCR_6P_A
687  2 // eCPT_DDR_2
688  };
689 
690 #ifdef RUNTIME_DEVICE_SELECT
691 const CPT_MultiMID_t CPT_TCI6614_MultiMID[] = {
692  {eCPT_TCI6614_MID_SRIO_PKTDMA_Grp0, 2},
693  {eCPT_TCI6614_MID_QM_SS_Grp0, 4},
694  {eCPT_TCI6614_MID_AIF_Grp0, 8},
695  {eCPT_TCI6614_MID_QM_CDMA_Grp0, 4},
696  {eCPT_TCI6614_MID_NETCP_Grp0, 2},
697  {eCPT_TCI6614_MID_ARM_128_Grp0, 32}
698  };
699 #else
700 const CPT_MultiMID_t CPT_MultiMID[] = {
701  {eCPT_MID_SRIO_PKTDMA_Grp0, 2},
702  {eCPT_MID_QM_SS_Grp0, 4},
703  {eCPT_MID_AIF_Grp0, 8},
704  {eCPT_MID_QM_CDMA_Grp0, 4},
705  {eCPT_MID_NETCP_Grp0, 2},
706  {eCPT_MID_ARM_128_Grp0, 32}
707  };
708 
709 #endif
710 #endif
711 #if defined(_TCI6612)
712 
713 #if defined(_STM_Logging) || defined(RUNTIME_DEVICE_SELECT)
714 static const char CPT_TCI6612_ModName_MSMC_0[] = "MSMC_0";
715 static const char CPT_TCI6612_ModName_MSMC_1[] = "MSMC_1";
716 static const char CPT_TCI6612_ModName_MSMC_2[] = "MSMC_2";
717 static const char CPT_TCI6612_ModName_MSMC_3[] = "MSMC_3";
718 static const char CPT_TCI6612_ModName_QM_MST[] = "QM_M";
719 static const char CPT_TCI6612_ModName_DDR[] = "DDR";
720 static const char CPT_TCI6612_ModName_SM[] = "SM";
721 static const char CPT_TCI6612_ModName_QM_CFG[] = "QM_CFG";
722 static const char CPT_TCI6612_ModName_CFG[] = "CFG";
723 static const char CPT_TCI6612_ModName_L2_0[] = "L2_0";
724 static const char CPT_TCI6612_ModName_L2_1[] = "L2_1";
725 static const char CPT_TCI6612_ModName_RAC[] = "RAC";
726 static const char CPT_TCI6612_ModName_RAC_CFG[] = "RAC_CFG";
727 static const char CPT_TCI6612_ModName_TAC[] = "TAC";
728 static const char CPT_TCI6612_ModName_SCR_6P_A[] = "SCR_6P_A";
729 static const char CPT_TCI6612_ModName_DDR_2[] = "DDR_2";
730 
731 //CP Tracer module mame strings indexed by eCPT_ModID
732 #ifdef RUNTIME_DEVICE_SELECT
733 const char * pCPT_TCI6612_ModNames[] = {
734 #else
735 const char * pCPT_ModNames[] = {
736 #endif
737  CPT_TCI6612_ModName_MSMC_0,
738  CPT_TCI6612_ModName_MSMC_1,
739  CPT_TCI6612_ModName_MSMC_2,
740  CPT_TCI6612_ModName_MSMC_3,
741  CPT_TCI6612_ModName_QM_MST,
742  CPT_TCI6612_ModName_DDR,
743  CPT_TCI6612_ModName_SM,
744  CPT_TCI6612_ModName_QM_CFG,
745  CPT_TCI6612_ModName_CFG,
746  CPT_TCI6612_ModName_L2_0,
747  CPT_TCI6612_ModName_L2_1,
748  CPT_TCI6612_ModName_RAC,
749  CPT_TCI6612_ModName_RAC_CFG,
750  CPT_TCI6612_ModName_TAC,
751  CPT_TCI6612_ModName_SCR_6P_A,
752  CPT_TCI6612_ModName_DDR_2
753  };
754 
755 #endif //_STM_Logging
756 
757 
758 //Nyquist CP Tracer Address Table indexed by eCPT_ModID
759 #ifdef RUNTIME_DEVICE_SELECT
760 const uint32_t CPT_TCI6612_BaseAddressTable[] = {
761 #else
762 const uint32_t CPT_BaseAddressTable[] = {
763 #endif
764  0x01d00000, // eCPT_MSMC_0
765  0x01d08000, // eCPT_MSMC_1
766  0x01d10000, // eCPT_MSMC_2
767  0x01d18000, // eCPT_MSMC_3
768  0x01d20000, // eCPT_QM_MST
769  0x01d28000, // eCPT_DDR
770  0x01d30000, // eCPT_SM
771  0x01d38000, // eCPT_QM_PRI
772  0x01d40000, // eCPT_SCR3_CFG
773  0x01d48000, // eCPT_L2_0
774  0x01d50000, // eCPT_L2_1
775  0x01d68000, // eCPT_RAC
776  0x01d70000, // eCPT_RAC_CFG
777  0x01d78000, // eCPT_TAC
778  0x01D80000, //eCPT_SCR_6P_A
779  0x01D88000 //eCPT_DDR_2
780  };
781 
782 //Nyquist CP Tracer clock rate divide-by-factors indexed by eCPT_ModID
783 #ifdef RUNTIME_DEVICE_SELECT
784 const uint8_t CPT_TCI6612_ModDivByFactors[] = {
785 #else
786 const uint8_t CPT_ModDivByFactors[] = {
787 #endif
788  2, // eCPT_MSMC_0
789  2, // eCPT_MSMC_1
790  2, // eCPT_MSMC_2
791  2, // eCPT_MSMC_3
792  3, // eCPT_QM_MST
793  2, // eCPT_DDR
794  3, // eCPT_SM
795  3, // eCPT_QM_PRI
796  3, // eCPT_SCR3_CFG
797  3, // eCPT_L2_0
798  3, // eCPT_L2_1
799  3, // eCPT_RAC
800  3, // eCPT_RAC_CFG
801  3, // eCPT_TAC
802  3, // eCPT_SCR_6P_A
803  2 // eCPT_DDR_2
804  };
805 
806 #ifdef RUNTIME_DEVICE_SELECT
807 const CPT_MultiMID_t CPT_TCI6612_MultiMID[] = {
808  {eCPT_TCI6612_MID_SRIO_PKTDMA_Grp0, 2},
809  {eCPT_TCI6612_MID_QM_SS_Grp0, 4},
810  {eCPT_TCI6612_MID_AIF_Grp0, 8},
811  {eCPT_TCI6612_MID_QM_CDMA_Grp0, 4},
812  {eCPT_TCI6612_MID_NETCP_Grp0, 2},
813  {eCPT_TCI6612_MID_ARM_128_Grp0, 32}
814  };
815 #else
816 const CPT_MultiMID_t CPT_MultiMID[] = {
817  {eCPT_MID_SRIO_PKTDMA_Grp0, 2},
818  {eCPT_MID_QM_SS_Grp0, 4},
819  {eCPT_MID_AIF_Grp0, 8},
820  {eCPT_MID_QM_CDMA_Grp0, 4},
821  {eCPT_MID_NETCP_Grp0, 2},
822  {eCPT_MID_ARM_128_Grp0, 32}
823  };
824 #endif
825 
826 #endif
827 #if defined(_C66AK2Hxx)
828 
829 #ifdef _STM_Logging
830 static const char CPT_ModName_MSMC_0[] = "MSMC_0";
831 static const char CPT_ModName_MSMC_1[] = "MSMC_1";
832 static const char CPT_ModName_MSMC_2[] = "MSMC_2";
833 static const char CPT_ModName_MSMC_3[] = "MSMC_3";
834 static const char CPT_ModName_QM_MST[] = "QM_M";
835 static const char CPT_ModName_DDR3A[] = "DDR3A";
836 static const char CPT_ModName_SM[] = "SM";
837 static const char CPT_ModName_QM_CFG1[] = "QM_CFG1";
838 static const char CPT_ModName_CFG[] = "CFG";
839 static const char CPT_ModName_L2_0[] = "L2_0";
840 static const char CPT_ModName_L2_1[] = "L2_1";
841 static const char CPT_ModName_L2_2[] = "L2_2";
842 static const char CPT_ModName_L2_3[] = "L2_3";
843 static const char CPT_ModName_L2_4[] = "L2_4";
844 static const char CPT_ModName_L2_5[] = "L2_5";
845 static const char CPT_ModName_L2_6[] = "L2_6";
846 static const char CPT_ModName_L2_7[] = "L2_7";
847 static const char CPT_ModName_RAC[] = "RAC";
848 static const char CPT_ModName_RAC_CFG1[] = "RAC_CFG1";
849 static const char CPT_ModName_TAC[] = "TAC";
850 static const char CPT_ModName_QM_CFG2[] = "QM_CFG2";
851 static const char CPT_ModName_RAC_CFG2[] = "RAC_CFG2";
852 static const char CPT_ModName_DDR3B[] = "DDR3B";
853 static const char CPT_ModName_BCR_CFG[] = "BCR_CFG";
854 static const char CPT_ModName_TPCC_0_4[] = "TPCC_0_4";
855 static const char CPT_ModName_TPCC_1_2_3[] = "TPCC_1_2_3";
856 static const char CPT_ModName_INTC_CFG[] = "INTC_CFG";
857 static const char CPT_ModName_MSMC_4[] = "MSMC_4";
858 static const char CPT_ModName_MSMC_5[] = "MSMC_5";
859 static const char CPT_ModName_MSMC_6[] = "MSMC_6";
860 static const char CPT_ModName_MSMC_7[] = "MSMC_7";
861 static const char CPT_ModName_SPI_ROM_EMIF16[] = "SPI_ROM_EMIF16";
862 
863 //CP Tracer module mame strings indexed by eCPT_ModID
864 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
865  CPT_ModName_MSMC_1,
866  CPT_ModName_MSMC_2,
867  CPT_ModName_MSMC_3,
868  CPT_ModName_QM_MST,
869  CPT_ModName_DDR3A,
870  CPT_ModName_SM,
871  CPT_ModName_QM_CFG1,
872  CPT_ModName_CFG,
873  CPT_ModName_L2_0,
874  CPT_ModName_L2_1,
875  CPT_ModName_L2_2,
876  CPT_ModName_L2_3,
877  CPT_ModName_L2_4,
878  CPT_ModName_L2_5,
879  CPT_ModName_L2_6,
880  CPT_ModName_L2_7,
881  CPT_ModName_RAC,
882  CPT_ModName_RAC_CFG1,
883  CPT_ModName_TAC,
884  CPT_ModName_QM_CFG2,
885  CPT_ModName_RAC_CFG2,
886  CPT_ModName_DDR3B,
887  CPT_ModName_BCR_CFG,
888  CPT_ModName_TPCC_0_4,
889  CPT_ModName_TPCC_1_2_3,
890  CPT_ModName_INTC_CFG,
891  CPT_ModName_MSMC_4,
892  CPT_ModName_MSMC_5,
893  CPT_ModName_MSMC_6,
894  CPT_ModName_MSMC_7,
895  CPT_ModName_SPI_ROM_EMIF16
896  };
897 
898 #endif //_STM_Logging
899 
900 //Nyquist CP Tracer Address Table indexed by eCPT_ModID
901 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000, // eCPT_MSMC_0
902  0x01d08000, // eCPT_MSMC_1
903  0x01d10000, // eCPT_MSMC_2
904  0x01d18000, // eCPT_MSMC_3
905  0x01d20000, // eCPT_QM_MST
906  0x01d28000, // eCPT_DDR3A
907  0x01d30000, // eCPT_SM
908  0x01d38000, // eCPT_QM1_PRI
909  0x01d40000, // eCPT_SCR3_CFG
910  0x01d48000, // eCPT_L2_0
911  0x01d50000, // eCPT_L2_1
912  0x01d58000, // eCPT_L2_2
913  0x01d60000, // eCPT_L2_3
914  0x01D68000, // eCPT_L2_4
915  0x01D70000, // eCPT_L2_5
916  0x01D78000, // eCPT_L2_6
917  0x01D80000, // eCPT_L2_7
918  0x01D88000, // eCPT_RAC
919  0x01D90000, // eCPT_RAC_CFG1
920  0x01D98000, // eCPT_TAC
921  0x01DA0000, // eCPT_QM_CFG2
922  0x01DA8000, // eCPT_RAC_CFG2
923  0x01DB0000, // eCPT_DDR3B
924  0x01DB8000, // eCPT_BCR_CFG
925  0x01DC0000, // eCPT_TPCC_0_4
926  0x01DC8000, // eCPT_TPCC_1_2_3
927  0x01DD0000, // eCPT_INTC_CFG
928  0x01DD8000, // eCPT_MSMC_4
929  0x01DE0000, // eCPT_MSMC_5
930  0x01DE0400, // eCPT_MSMC_6
931  0x01DE0800, // eCPT_MSMC_7
932  0x01DE8000 // eCPT_SPI_ROM_EMIF16
933  };
934 
935 //Nyquist CP Tracer clock rate divide-by-factors indexed by eCPT_ModID
936 const uint8_t CPT_ModDivByFactors[] = { 1, // eCPT_MSMC_0
937  1, // eCPT_MSMC_1
938  1, // eCPT_MSMC_2
939  1, // eCPT_MSMC_3
940  3, // eCPT_QM_MST
941  1, // eCPT_DDR3A
942  3, // eCPT_SM
943  3, // eCPT_QM1_PRI
944  3, // eCPT_SCR3_CFG
945  3, // eCPT_L2_0
946  3, // eCPT_L2_1
947  3, // eCPT_L2_2
948  3, // eCPT_L2_3
949  3, // eCPT_L2_4
950  3, // eCPT_L2_5
951  3, // eCPT_L2_6
952  3, // eCPT_L2_7
953  3, // eCPT_RAC
954  3, // eCPT_RAC_CFG1
955  3, // eCPT_TAC
956  3, // eCPT_QM_CFG2
957  3, // eCPT_RAC_CFG2
958  3, // eCPT_DDR3B
959  3, // eCPT_BCR_CFG
960  3, // eCPT_TPCC_0_4
961  3, // eCPT_TPCC_1_2_3
962  3, // eCPT_INTC_CFG
963  1, // eCPT_MSMC_4
964  1, // eCPT_MSMC_5
965  1, // eCPT_MSMC_6
966  1, // eCPT_MSMC_7
967  3 // eCPT_SPI_ROM_EMIF16
968  };
969 
970 
971 
972 
973 const CPT_MultiMID_t CPT_MultiMID[] = { eCPT_MID_SRIO_PKTDMA_Grp0,
974  2,
975  eCPT_MID_QM_second_Grp0,
976  4,
977  eCPT_MID_AIF_Grp0,
978  8,
979  eCPT_MID_XGE_Grp0,
980  4,
981  eCPT_MID_QM2_CDMA_Grp0,
982  4,
983  eCPT_MID_QM1_CDMA_Grp0,
984  4,
985  eCPT_MID_NETCP_Grp0,
986  4
987  };
988 
989 #endif
990 
991 #if defined(_66AK2Exx)
992 
993 #ifdef _STM_Logging
994 static const char CPT_ModName_MSMC_0[] = "MSMC_0";
995 static const char CPT_ModName_MSMC_1[] = "MSMC_1";
996 static const char CPT_ModName_MSMC_2[] = "MSMC_2";
997 static const char CPT_ModName_MSMC_3[] = "MSMC_3";
998 static const char CPT_ModName_QM_MST[] = "QM_M";
999 static const char CPT_ModName_DDR3A[] = "DDR3A";
1000 static const char CPT_ModName_SM[] = "SM";
1001 static const char CPT_ModName_QM_CFG1[] = "QM_CFG1";
1002 static const char CPT_ModName_CFG[] = "SCR3_CFG";
1003 static const char CPT_ModName_L2_0[] = "L2_0";
1004 static const char CPT_ModName_QM_CFG2[] = "QM_CFG2";
1005 static const char CPT_ModName_TPCC_0_4[] = "TPCC_0_4";
1006 static const char CPT_ModName_TPCC_1_2_3[] = "TPCC_1_2_3";
1007 static const char CPT_ModName_INTC_CFG[] = "INTC_CFG";
1008 static const char CPT_ModName_MSMC_4[] = "MSMC_4";
1009 static const char CPT_ModName_MSMC_5[] = "MSMC_5";
1010 static const char CPT_ModName_MSMC_6[] = "MSMC_6";
1011 static const char CPT_ModName_MSMC_7[] = "MSMC_7";
1012 static const char CPT_ModName_SPI_ROM_EMIF16[] = "SPI_ROM_EMIF16";
1013 static const char CPT_ModName_NETCP_USB_CFG[] = "NETCP_USB_CFG";
1014 static const char CPT_ModName_PCIE1_CFG[] = "PCIE1_CFG";
1015 
1016 //CP Tracer module mame strings indexed by eCPT_ModID
1017 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
1018  CPT_ModName_MSMC_1,
1019  CPT_ModName_MSMC_2,
1020  CPT_ModName_MSMC_3,
1021  CPT_ModName_QM_MST,
1022  CPT_ModName_DDR3A,
1023  CPT_ModName_SM,
1024  CPT_ModName_QM_CFG1,
1025  CPT_ModName_CFG,
1026  CPT_ModName_L2_0,
1027  CPT_ModName_QM_CFG2,
1028  CPT_ModName_TPCC_0_4,
1029  CPT_ModName_TPCC_1_2_3,
1030  CPT_ModName_INTC_CFG,
1031  CPT_ModName_MSMC_4,
1032  CPT_ModName_MSMC_5,
1033  CPT_ModName_MSMC_6,
1034  CPT_ModName_MSMC_7,
1035  CPT_ModName_SPI_ROM_EMIF16,
1036  CPT_ModName_NETCP_USB_CFG,
1037  CPT_ModName_PCIE1_CFG
1038  };
1039 
1040 #endif //_STM_Logging
1041 
1042 //Nyquist CP Tracer Address Table indexed by eCPT_ModID
1043 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000, // eCPT_MSMC_0
1044  0x01d08000, // eCPT_MSMC_1
1045  0x01d10000, // eCPT_MSMC_2
1046  0x01d18000, // eCPT_MSMC_3
1047  0x01d20000, // eCPT_QM_MST
1048  0x01d28000, // eCPT_DDR3A
1049  0x01d30000, // eCPT_SM
1050  0x01d38000, // eCPT_QM1_PRI
1051  0x01d40000, // eCPT_SCR3_CFG
1052  0x01d48000, // eCPT_L2_0
1053  0x01DA0000, // eCPT_QM_CFG2
1054  0x01DC0000, // eCPT_TPCC_0_4
1055  0x01DC8000, // eCPT_TPCC_1_2_3
1056  0x01DD0000, // eCPT_INTC_CFG
1057  0x01DD8000, // eCPT_MSMC_4
1058  0x01DE0000, // eCPT_MSMC_5
1059  0x01DE0400, // eCPT_MSMC_6
1060  0x01DE0800, // eCPT_MSMC_7
1061  0x01DE8000, // eCPT_SPI_ROM_EMIF16
1062  0x021D0400, // NETCP_USB_CFG
1063  0x01d80000 // PCIE1_CFG
1064  };
1065 
1066 //Nyquist CP Tracer clock rate divide-by-factors indexed by eCPT_ModID
1067 const uint8_t CPT_ModDivByFactors[] = { 1, // eCPT_MSMC_0
1068  1, // eCPT_MSMC_1
1069  1, // eCPT_MSMC_2
1070  1, // eCPT_MSMC_3
1071  3, // eCPT_QM_MST
1072  1, // eCPT_DDR3A
1073  3, // eCPT_SM
1074  3, // eCPT_QM1_PRI
1075  3, // eCPT_SCR3_CFG
1076  3, // eCPT_L2_0
1077  3, // eCPT_QM_CFG2
1078  3, // eCPT_TPCC_0_4
1079  3, // eCPT_TPCC_1_2_3
1080  3, // eCPT_INTC_CFG
1081  1, // eCPT_MSMC_4
1082  1, // eCPT_MSMC_5
1083  1, // eCPT_MSMC_6
1084  1, // eCPT_MSMC_7
1085  3, // eCPT_SPI_ROM_EMIF16
1086  3, // eCPT_NETCP_USB_CFG
1087  3 // eCPT_PCIE1_CFG
1088  };
1089 
1090 
1091 
1092 
1093 const CPT_MultiMID_t CPT_MultiMID[] = {
1094  eCPT_MID_QM_second_Grp0,
1095  4,
1096  eCPT_MID_NETCP_GLOBAL1_Grp0,
1097  4,
1098  eCPT_MID_XGE_Grp0,
1099  4,
1100  eCPT_MID_QM1_CDMA_Grp0,
1101  4,
1102  eCPT_MID_NETCP_LOCAL_Grp0,
1103  8,
1104  eCPT_MID_NETCP_Grp0,
1105  4
1106  };
1107 
1108 #endif
1109 
1110 #if defined (_TCI6630K2L)
1111 
1112 #ifdef _STM_Logging
1113 static const char CPT_ModName_MSMC_0[] = "MSMC_0";
1114 static const char CPT_ModName_MSMC_1[] = "MSMC_1";
1115 static const char CPT_ModName_MSMC_2[] = "MSMC_2";
1116 static const char CPT_ModName_MSMC_3[] = "MSMC_3";
1117 static const char CPT_ModName_QM_MST[] = "QM_M";
1118 static const char CPT_ModName_DDR3A[] = "DDR3A";
1119 static const char CPT_ModName_SM[] = "SM";
1120 static const char CPT_ModName_QM_CFG1[] = "QM_CFG1";
1121 static const char CPT_ModName_CFG[] = "CFG";
1122 static const char CPT_ModName_L2_0[] = "L2_0";
1123 static const char CPT_ModName_L2_1[] = "L2_1";
1124 static const char CPT_ModName_L2_2[] = "L2_2";
1125 static const char CPT_ModName_L2_3[] = "L2_3";
1126 static const char CPT_ModName_RAC[] = "RAC";
1127 static const char CPT_ModName_RAC_CFG1[] = "RAC_CFG1";
1128 static const char CPT_ModName_TAC[] = "TAC";
1129 static const char CPT_ModName_QM_CFG2[] = "QM_CFG2";
1130 static const char CPT_ModName_OSR_PCIE1_CFG[] = "OSR_PCIE1_CFG";
1131 static const char CPT_ModName_TPCC_0_4[] = "TPCC_0";
1132 static const char CPT_ModName_TPCC_1_2_3[] = "TPCC_1_2";
1133 static const char CPT_ModName_INTC_CFG[] = "INTC_CFG";
1134 static const char CPT_ModName_MSMC_4[] = "MSMC_4";
1135 static const char CPT_ModName_MSMC_5[] = "MSMC_5";
1136 static const char CPT_ModName_MSMC_6[] = "MSMC_6";
1137 static const char CPT_ModName_MSMC_7[] = "MSMC_7";
1138 static const char CPT_ModName_SPI_ROM_EMIF16[] = "SPI_ROM_EMIF16";
1139 static const char CPT_ModName_CPT_CFG_3P_U[] = "CFG_3P_U";
1140 
1141 //CP Tracer module mame strings indexed by eCPT_ModID
1142 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
1143  CPT_ModName_MSMC_1,
1144  CPT_ModName_MSMC_2,
1145  CPT_ModName_MSMC_3,
1146  CPT_ModName_QM_MST,
1147  CPT_ModName_DDR3A,
1148  CPT_ModName_SM,
1149  CPT_ModName_QM_CFG1,
1150  CPT_ModName_CFG,
1151  CPT_ModName_L2_0,
1152  CPT_ModName_L2_1,
1153  CPT_ModName_L2_2,
1154  CPT_ModName_L2_3,
1155  CPT_ModName_RAC,
1156  CPT_ModName_RAC_CFG1,
1157  CPT_ModName_TAC,
1158  CPT_ModName_QM_CFG2,
1159  CPT_ModName_OSR_PCIE1_CFG,
1160  CPT_ModName_TPCC_0_4,
1161  CPT_ModName_TPCC_1_2_3,
1162  CPT_ModName_INTC_CFG,
1163  CPT_ModName_MSMC_4,
1164  CPT_ModName_MSMC_5,
1165  CPT_ModName_MSMC_6,
1166  CPT_ModName_MSMC_7,
1167  CPT_ModName_SPI_ROM_EMIF16,
1168  CPT_ModName_CPT_CFG_3P_U
1169  };
1170 
1171 #endif //_STM_Logging
1172 
1173 //Nyquist CP Tracer Address Table indexed by eCPT_ModID
1174 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000, // eCPT_MSMC_0
1175  0x01d08000, // eCPT_MSMC_1
1176  0x01d10000, // eCPT_MSMC_2
1177  0x01d18000, // eCPT_MSMC_3
1178  0x01d20000, // eCPT_QM_MST
1179  0x01d28000, // eCPT_DDR3A
1180  0x01d30000, // eCPT_SM
1181  0x01d38000, // eCPT_QM1_PRI
1182  0x01d40000, // eCPT_SCR3_CFG
1183  0x01d48000, // eCPT_L2_0
1184  0x01d50000, // eCPT_L2_1
1185  0x01d58000, // eCPT_L2_2
1186  0x01d60000, // eCPT_L2_3
1187  0x01D88000, // eCPT_RAC
1188  0x01D90000, // eCPT_RAC_CFG1
1189  0x01D98000, // eCPT_TAC
1190  0x01DA0000, // eCPT_QM_CFG2
1191  0x01DB0000, // eCPT_OSR_PCIE1_CFG
1192  0x01DC0000, // eCPT_TPCC_0
1193  0x01DC8000, // eCPT_TPCC_1_2
1194  0x01DD0000, // eCPT_INTC_CFG
1195  0x01DD8000, // eCPT_MSMC_4
1196  0x01DE0000, // eCPT_MSMC_5
1197  0x01DE0400, // eCPT_MSMC_6
1198  0x01DE0800, // eCPT_MSMC_7
1199  0x01DE8000, // eCPT_SPI_ROM_EMIF16
1200  0x02340800 // eCPT_CFG_3P_U
1201  };
1202 
1203 //Nyquist CP Tracer clock rate divide-by-factors indexed by eCPT_ModID
1204 const uint8_t CPT_ModDivByFactors[] = { 1, // eCPT_MSMC_0
1205  1, // eCPT_MSMC_1
1206  1, // eCPT_MSMC_2
1207  1, // eCPT_MSMC_3
1208  3, // eCPT_QM_MST
1209  1, // eCPT_DDR3A
1210  3, // eCPT_SM
1211  3, // eCPT_QM1_PRI
1212  3, // eCPT_SCR3_CFG
1213  3, // eCPT_L2_0
1214  3, // eCPT_L2_1
1215  3, // eCPT_L2_2
1216  3, // eCPT_L2_3
1217  3, // eCPT_RAC
1218  3, // eCPT_RAC_CFG1
1219  3, // eCPT_TAC
1220  3, // eCPT_QM_CFG2
1221  3, // eCPT_OSR_PCIE1_CFG
1222  3, // eCPT_TPCC_0_4
1223  3, // eCPT_TPCC_1_2_3
1224  3, // eCPT_INTC_CFG
1225  1, // eCPT_MSMC_4
1226  1, // eCPT_MSMC_5
1227  1, // eCPT_MSMC_6
1228  1, // eCPT_MSMC_7
1229  3, // eCPT_SPI_ROM_EMIF16
1230  3 // eCPT_CFG_3P_U
1231  };
1232 
1233 
1234 
1235 
1236 const CPT_MultiMID_t CPT_MultiMID[] = { eCPT_MID_QM_second_Grp0,
1237  4,
1238  eCPT_MID_IQN_CDMA_Grp0,
1239  4,
1240  eCPT_MID_QM1_CDMA_Grp0,
1241  4,
1242  eCPT_MID_NETCP_LOCAL_Grp0,
1243  8,
1244  eCPT_MID_NETCP_GLOBAL_Grp0,
1245  4
1246  };
1247 
1248 #endif
1249 #if defined (_66AK2Gxx)
1250 
1251 #ifdef _STM_Logging
1252 static const char CPT_ModName_MSMC_0[] = "MSMC_0";
1253 static const char CPT_ModName_DDR3[] = "DDR3";
1254 static const char CPT_ModName_L2_0[] = "L2_0";
1255 static const char CPT_ModName_PCIE[] = "PCIE";
1256 static const char CPT_ModName_DXB[] = "DXB";
1257 static const char CPT_ModName_MCASP_MCBSP[] = "MCASP_MCBSP";
1258 static const char CPT_ModName_GPMC_MMC_QSPI[] = "GPMC_MMC_QSPI";
1259 static const char CPT_ModName_TPCC[] = "TPCC0";
1260 static const char CPT_ModName_ALWAYSON_CFG[] ="ALWAYSON_CFG";
1261 static const char CPT_ModName_GIC[] ="GIC";
1262 static const char CPT_ModName_CIC[] ="CIC";
1263 static const char CPT_ModName_ROM_SPI[] ="ROM_SPI";
1264 static const char CPT_ModName_ALWAYSON_MAIN[] ="ALWAYSON_MAIN";
1265 static const char CPT_ModName_ICSS_ASRC[] ="ICSS_ASRC";
1266 static const char CPT_ModName_CFG[] ="CFG";
1267 
1268 //CP Tracer module mame strings indexed by eCPT_ModID
1269 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
1270  CPT_ModName_DDR3,
1271  CPT_ModName_L2_0,
1272  CPT_ModName_PCIE,
1273  CPT_ModName_DXB,
1274  CPT_ModName_MCASP_MCBSP,
1275  CPT_ModName_GPMC_MMC_QSPI,
1276  CPT_ModName_TPCC,
1277  CPT_ModName_CFG,
1278  CPT_ModName_ALWAYSON_CFG,
1279  CPT_ModName_GIC,
1280  CPT_ModName_CIC,
1281  CPT_ModName_ROM_SPI,
1282  CPT_ModName_ALWAYSON_MAIN,
1283  CPT_ModName_ICSS_ASRC
1284  };
1285 
1286 #endif //_STM_Logging
1287 
1288 //Nyquist CP Tracer Address Table indexed by eCPT_ModID
1289 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000, // eCPT_MSMC_0
1290  0x01d08000, // eCPT_DDR
1291  0x01d10000, // eCPT_L2_0
1292  0x01d18000, // eCPT_PCIE
1293  0x01d20000, // eCPT_DXB
1294  0x01d28000, // eCPT_MCASP_MCBSP
1295  0x01d30000, // eCPT_GPMC_MMC_QSPI
1296  0x01d38000, // eCPT_TPCC
1297  0x01d40000, // eCPT_CFG
1298  0x01d48000, // eCPT_ALWAYSON_CFG
1299  0x01d50000, // eCPT_GIC
1300  0x01d58000, // eCPT_CIC
1301  0x01d60000, // eCPT_ROM_SPI
1302  0x01D68000, // eCPT_ALWAYSON_MAIN
1303  0x01D70000 // eCPT_ICSS_ASRC
1304  };
1305 
1306 //Nyquist CP Tracer clock rate divide-by-factors indexed by eCPT_ModID
1307 const uint8_t CPT_ModDivByFactors[] = { 1, // eCPT_MSMC_0
1308  1, // eCPT_DDR
1309  3, // eCPT_L2_0
1310  3, // eCPT_PCIE
1311  3, // eCPT_DXB
1312  3, // eCPT_MCASP_MCBSP
1313  3, // eCPT_GPMC_MMC_QSPI
1314  3, // eCPT_TPCC
1315  3, // eCPT_CFG
1316  3, // eCPT_ALWAYSON_CFG
1317  3, // eCPT_GIC
1318  3, // eCPT_CIC
1319  3, // eCPT_ROM_SPI
1320  3, // eCPT_ALWAYSON_MAIN
1321  3 // eCPT_ICSS_ASRC
1322  };
1323 
1324 const CPT_MultiMID_t CPT_MultiMID[] = { eCPT_MID_NSSL_Grp0,
1325  4,
1327  32,
1329  16
1330  };
1331 
1332 #endif
1333 #ifdef RUNTIME_DEVICE_SELECT
1334 // Master names in eCPT_MasterID id order
1337 static const char CPT_MasterName_GEM0[] = "DSP0";
1338 static const char CPT_MasterName_GEM1[] = "DSP1";
1339 static const char CPT_MasterName_GEM2[] = "DSP2";
1340 static const char CPT_MasterName_GEM3[] = "DSP3";
1341 static const char CPT_MasterName_ARM_64[] = "ARM_64";
1342 static const char CPT_MasterName_GEM0_CFG[] = "DSP0_CFG";
1343 static const char CPT_MasterName_GEM1_CFG[] = "DSP1_CFG";
1344 static const char CPT_MasterName_GEM2_CFG[] = "DSP2_CFG";
1345 static const char CPT_MasterName_GEM3_CFG[] = "DSP3_CFG";
1346 static const char CPT_MasterName_EDMA0_TC0_RD[] = "EDMA0_TC0_RD";
1347 static const char CPT_MasterName_EDMA0_TC0_WR[] = "EDMA0_TC0_WR";
1348 static const char CPT_MasterName_EDMA0_TC1_RD[] = "EDMA0_TC1_RD";
1349 static const char CPT_MasterName_EDMA0_TC1_WR[] = "EDMA0_TC1_WR";
1350 static const char CPT_MasterName_EDMA1_TC0_RD[] = "EDMA1_TC0_RD";
1351 static const char CPT_MasterName_EDMA1_TC0_WR[] = "EDMA1_TC0_WR";
1352 static const char CPT_MasterName_EDMA1_TC1_RD[] = "EDMA1_TC1_RD";
1353 static const char CPT_MasterName_EDMA1_TC1_WR[] = "EDMA1_TC1_WR";
1354 static const char CPT_MasterName_EDMA1_TC2_RD[] = "EDMA1_TC2_RD";
1355 static const char CPT_MasterName_EDMA1_TC2_WR[] = "EDMA1_TC2_WR";
1356 static const char CPT_MasterName_EDMA1_TC3_RD[] = "EDMA1_TC3_RD";
1357 static const char CPT_MasterName_EDMA1_TC3_WR[] = "EDMA1_TC3_WR";
1358 static const char CPT_MasterName_EDMA2_TC0_RD[] = "EDMA2_TC0_RD";
1359 static const char CPT_MasterName_EDMA2_TC0_WR[] = "EDMA2_TC0_WR";
1360 static const char CPT_MasterName_EDMA2_TC1_RD[] = "EDMA2_TC1_RD";
1361 static const char CPT_MasterName_EDMA2_TC1_WR[] = "EDMA2_TC1_WR";
1362 static const char CPT_MasterName_EDMA2_TC2_RD[] = "EDMA2_TC2_RD";
1363 static const char CPT_MasterName_EDMA2_TC2_WR[] = "EDMA2_TC2_WR";
1364 static const char CPT_MasterName_EDMA2_TC3_RD[] = "EDMA2_TC3_RD";
1365 static const char CPT_MasterName_EDMA2_TC3_WR[] = "EDMA2_TC3_WR";
1366 static const char CPT_MasterName_SRIO_PKTDMA_Grp0[] = "SRIO_PKTDMA_0";
1367 static const char CPT_MasterName_SRIO_PKTDMA_Grp1[] = "SRIO_PKTDMA_1";
1368 static const char CPT_MasterName_DAP[] = "DAP";
1369 static const char CPT_MasterName_TPCC0[] = "TPCC0";
1370 static const char CPT_MasterName_TPCC1[] = "TPCC1";
1371 static const char CPT_MasterName_TPCC2[] = "TPCC2";
1372 static const char CPT_MasterName_MSMC[] = "MSMC";
1373 static const char CPT_MasterName_PCIe[] = "PCIE";
1374 static const char CPT_MasterName_SRIO_M[] = "SRIO_M";
1375 static const char CPT_MasterName_HyperBridge[] = "HYPERBRIDGE";
1376 static const char CPT_MasterName_QM_SS_Grp0[] = "QM_SS_0";
1377 static const char CPT_MasterName_QM_SS_Grp1[] = "QM_SS_1";
1378 static const char CPT_MasterName_QM_SS_Grp2[] = "QM_SS_2";
1379 static const char CPT_MasterName_QM_SS_Grp3[] = "QM_SS_3";
1380 static const char CPT_MasterName_AIF_Grp0[] = "AIF_0";
1381 static const char CPT_MasterName_AIF_Grp1[] = "AIF_1";
1382 static const char CPT_MasterName_AIF_Grp2[] = "AIF_2";
1383 static const char CPT_MasterName_AIF_Grp3[] = "AIF_3";
1384 static const char CPT_MasterName_AIF_Grp4[] = "AIF_4";
1385 static const char CPT_MasterName_AIF_Grp5[] = "AIF_5";
1386 static const char CPT_MasterName_AIF_Grp6[] = "AIF_6";
1387 static const char CPT_MasterName_AIF_Grp7[] = "AIF_7";
1388 static const char CPT_MasterName_QM_CDMA_Grp0[] = "QM_CDMA_0";
1389 static const char CPT_MasterName_QM_CDMA_Grp1[] = "QM_CDMA_1";
1390 static const char CPT_MasterName_QM_CDMA_Grp2[] = "QM_CDMA_2";
1391 static const char CPT_MasterName_QM_CDMA_Grp3[] = "QM_CDMA_3";
1392 static const char CPT_MasterName_NETCP_Grp0[] = "NETCP_0";
1393 static const char CPT_MasterName_NETCP_Grp1[] = "NETCP_1";
1394 static const char CPT_MasterName_TAC[] = "TAC";
1395 
1396 static const char CPT_MasterName_BCP_DIO1[] = "BCP_DIO1";
1397 static const char CPT_MasterName_BCP_CDMA[] = "BCP_CDMA";
1398 static const char CPT_MasterName_BCP_DIO0[] = "BCP_DIO0";
1399 
1400 static const char CPT_MasterName_ARM_128_Grp0[] = "ARM_128_0";
1401 
1402 
1403 const char * CPT_TCI6614_MasterNames[] = {
1404  CPT_MasterName_GEM0,
1405  CPT_MasterName_GEM1,
1406  CPT_MasterName_GEM2,
1407  CPT_MasterName_GEM3,
1408  CPT_MasterName_ARM_64,
1409  CPT_MasterName_GEM0_CFG,
1410  CPT_MasterName_GEM1_CFG,
1411  CPT_MasterName_GEM2_CFG,
1412  CPT_MasterName_GEM3_CFG,
1413  CPT_MasterName_EDMA0_TC0_RD,
1414  CPT_MasterName_EDMA0_TC0_WR,
1415  CPT_MasterName_EDMA0_TC1_RD,
1416  CPT_MasterName_EDMA0_TC1_WR,
1417  CPT_MasterName_EDMA1_TC0_RD,
1418  CPT_MasterName_EDMA1_TC0_WR,
1419  CPT_MasterName_EDMA1_TC1_RD,
1420  CPT_MasterName_EDMA1_TC1_WR,
1421  CPT_MasterName_EDMA1_TC2_RD,
1422  CPT_MasterName_EDMA1_TC2_WR,
1423  CPT_MasterName_EDMA1_TC3_RD,
1424  CPT_MasterName_EDMA1_TC3_WR,
1425  CPT_MasterName_EDMA2_TC0_RD,
1426  CPT_MasterName_EDMA2_TC0_WR,
1427  CPT_MasterName_EDMA2_TC1_RD,
1428  CPT_MasterName_EDMA2_TC1_WR,
1429  CPT_MasterName_EDMA2_TC2_RD,
1430  CPT_MasterName_EDMA2_TC2_WR,
1431  CPT_MasterName_EDMA2_TC3_RD,
1432  CPT_MasterName_EDMA2_TC3_WR,
1433  CPT_MasterName_SRIO_PKTDMA_Grp0,
1434  CPT_MasterName_SRIO_PKTDMA_Grp1,
1435  CPT_MasterName_DAP,
1436  CPT_MasterName_TPCC0,
1437  CPT_MasterName_TPCC1,
1438  CPT_MasterName_TPCC2,
1439  CPT_MasterName_MSMC,
1440  CPT_MasterName_PCIe,
1441  CPT_MasterName_SRIO_M,
1442  CPT_MasterName_HyperBridge,
1443  CPT_MasterName_QM_SS_Grp0,
1444  CPT_MasterName_QM_SS_Grp1,
1445  CPT_MasterName_QM_SS_Grp2,
1446  CPT_MasterName_QM_SS_Grp3,
1447  CPT_MasterName_AIF_Grp0,
1448  CPT_MasterName_AIF_Grp1,
1449  CPT_MasterName_AIF_Grp2,
1450  CPT_MasterName_AIF_Grp3,
1451  CPT_MasterName_AIF_Grp4,
1452  CPT_MasterName_AIF_Grp5,
1453  CPT_MasterName_AIF_Grp6,
1454  CPT_MasterName_AIF_Grp7,
1455  CPT_MasterName_QM_CDMA_Grp0,
1456  CPT_MasterName_QM_CDMA_Grp1,
1457  CPT_MasterName_QM_CDMA_Grp2,
1458  CPT_MasterName_QM_CDMA_Grp3,
1459  CPT_MasterName_NETCP_Grp0,
1460  CPT_MasterName_NETCP_Grp1,
1461  CPT_MasterName_TAC,
1462  CPT_MasterName_BCP_DIO1,
1463  CPT_MasterName_BCP_CDMA,
1464  CPT_MasterName_BCP_DIO0,
1465  CPT_MasterName_ARM_128_Grp0
1466 };
1467 
1468 const char * CPT_TCI6612_MasterNames[] = {
1469  CPT_MasterName_GEM0,
1470  CPT_MasterName_GEM1,
1471  CPT_MasterName_ARM_64,
1472  CPT_MasterName_GEM0_CFG,
1473  CPT_MasterName_GEM1_CFG,
1474  CPT_MasterName_EDMA0_TC0_RD,
1475  CPT_MasterName_EDMA0_TC0_WR,
1476  CPT_MasterName_EDMA0_TC1_RD,
1477  CPT_MasterName_EDMA0_TC1_WR,
1478  CPT_MasterName_EDMA1_TC0_RD,
1479  CPT_MasterName_EDMA1_TC0_WR,
1480  CPT_MasterName_EDMA1_TC1_RD,
1481  CPT_MasterName_EDMA1_TC1_WR,
1482  CPT_MasterName_EDMA1_TC2_RD,
1483  CPT_MasterName_EDMA1_TC2_WR,
1484  CPT_MasterName_EDMA1_TC3_RD,
1485  CPT_MasterName_EDMA1_TC3_WR,
1486  CPT_MasterName_EDMA2_TC0_RD,
1487  CPT_MasterName_EDMA2_TC0_WR,
1488  CPT_MasterName_EDMA2_TC1_RD,
1489  CPT_MasterName_EDMA2_TC1_WR,
1490  CPT_MasterName_EDMA2_TC2_RD,
1491  CPT_MasterName_EDMA2_TC2_WR,
1492  CPT_MasterName_EDMA2_TC3_RD,
1493  CPT_MasterName_EDMA2_TC3_WR,
1494  CPT_MasterName_SRIO_PKTDMA_Grp0,
1495  CPT_MasterName_SRIO_PKTDMA_Grp1,
1496  CPT_MasterName_DAP,
1497  CPT_MasterName_TPCC0,
1498  CPT_MasterName_TPCC1,
1499  CPT_MasterName_TPCC2,
1500  CPT_MasterName_MSMC,
1501  CPT_MasterName_PCIe,
1502  CPT_MasterName_SRIO_M,
1503  CPT_MasterName_HyperBridge,
1504  CPT_MasterName_QM_SS_Grp0,
1505  CPT_MasterName_QM_SS_Grp1,
1506  CPT_MasterName_QM_SS_Grp2,
1507  CPT_MasterName_QM_SS_Grp3,
1508  CPT_MasterName_AIF_Grp0,
1509  CPT_MasterName_AIF_Grp1,
1510  CPT_MasterName_AIF_Grp2,
1511  CPT_MasterName_AIF_Grp3,
1512  CPT_MasterName_AIF_Grp4,
1513  CPT_MasterName_AIF_Grp5,
1514  CPT_MasterName_AIF_Grp6,
1515  CPT_MasterName_AIF_Grp7,
1516  CPT_MasterName_QM_CDMA_Grp0,
1517  CPT_MasterName_QM_CDMA_Grp1,
1518  CPT_MasterName_QM_CDMA_Grp2,
1519  CPT_MasterName_QM_CDMA_Grp3,
1520  CPT_MasterName_NETCP_Grp0,
1521  CPT_MasterName_NETCP_Grp1,
1522  CPT_MasterName_TAC,
1523  CPT_MasterName_BCP_DIO1,
1524  CPT_MasterName_BCP_CDMA,
1525  CPT_MasterName_BCP_DIO0,
1526  CPT_MasterName_ARM_128_Grp0,
1527 };
1528 
1529 struct _CPT_MasterIdTable {
1530  int master_id;
1531  int group_cnt;
1532 };
1533 
1534 /* Note: The master id's in this table are indexed from the CPT_TCI6612_MasterNames tables */
1535 
1536 struct _CPT_MasterIdTable CPT_TCI6614_MasterIDTable[] = {
1537  {eCPT_TCI6614_MID_GEM0, 0},
1538  {eCPT_TCI6614_MID_GEM1, 0},
1539  {eCPT_TCI6614_MID_GEM2, 0},
1540  {eCPT_TCI6614_MID_GEM3, 0},
1541  {eCPT_TCI6614_MID_ARM_64, 0},
1542  {eCPT_TCI6614_MID_GEM0_CFG, 0},
1543  {eCPT_TCI6614_MID_GEM1_CFG, 0},
1544  {eCPT_TCI6614_MID_GEM2_CFG, 0},
1545  {eCPT_TCI6614_MID_GEM3_CFG, 0},
1546  {eCPT_TCI6614_MID_EDMA0_TC0_RD, 0},
1547  {eCPT_TCI6614_MID_EDMA0_TC0_WR, 0},
1548  {eCPT_TCI6614_MID_EDMA0_TC1_RD, 0},
1549  {eCPT_TCI6614_MID_EDMA0_TC1_WR, 0},
1550  {eCPT_TCI6614_MID_EDMA1_TC0_RD, 0},
1551  {eCPT_TCI6614_MID_EDMA1_TC0_WR, 0},
1552  {eCPT_TCI6614_MID_EDMA1_TC1_RD, 0},
1553  {eCPT_TCI6614_MID_EDMA1_TC1_WR, 0},
1554  {eCPT_TCI6614_MID_EDMA1_TC2_RD, 0},
1555  {eCPT_TCI6614_MID_EDMA1_TC2_WR, 0},
1556  {eCPT_TCI6614_MID_EDMA1_TC3_RD, 0},
1557  {eCPT_TCI6614_MID_EDMA1_TC3_WR, 0},
1558  {eCPT_TCI6614_MID_EDMA2_TC0_RD, 0},
1559  {eCPT_TCI6614_MID_EDMA2_TC0_WR, 0},
1560  {eCPT_TCI6614_MID_EDMA2_TC1_RD, 0},
1561  {eCPT_TCI6614_MID_EDMA2_TC1_WR, 0},
1562  {eCPT_TCI6614_MID_EDMA2_TC2_RD, 0},
1563  {eCPT_TCI6614_MID_EDMA2_TC2_WR, 0},
1564  {eCPT_TCI6614_MID_EDMA2_TC3_RD, 0},
1565  {eCPT_TCI6614_MID_EDMA2_TC3_WR, 0},
1566  {eCPT_TCI6614_MID_SRIO_PKTDMA_Grp0, 2},
1567  {eCPT_TCI6614_MID_SRIO_PKTDMA_Grp1, 0},
1568  {eCPT_TCI6614_MID_DAP, 0},
1569  {eCPT_TCI6614_MID_TPCC0, 0},
1570  {eCPT_TCI6614_MID_TPCC1, 0},
1571  {eCPT_TCI6614_MID_TPCC2, 0},
1572  {eCPT_TCI6614_MID_MSMC, 0},
1573  {eCPT_TCI6614_MID_PCIe, 0},
1574  {eCPT_TCI6614_MID_SRIO_M, 0},
1575  {eCPT_TCI6614_MID_HyperBridge, 0},
1576  {eCPT_TCI6614_MID_QM_SS_Grp0, 0},
1577  {eCPT_TCI6614_MID_QM_SS_Grp1, 0},
1578  {eCPT_TCI6614_MID_QM_SS_Grp2, 0},
1579  {eCPT_TCI6614_MID_QM_SS_Grp3, 0},
1580  {eCPT_TCI6614_MID_AIF_Grp0, 8},
1581  {eCPT_TCI6614_MID_AIF_Grp1, 0},
1582  {eCPT_TCI6614_MID_AIF_Grp2, 0},
1583  {eCPT_TCI6614_MID_AIF_Grp3, 0},
1584  {eCPT_TCI6614_MID_AIF_Grp4, 0},
1585  {eCPT_TCI6614_MID_AIF_Grp5, 0},
1586  {eCPT_TCI6614_MID_AIF_Grp6, 0},
1587  {eCPT_TCI6614_MID_AIF_Grp7, 0},
1588  {eCPT_TCI6614_MID_QM_CDMA_Grp0, 4},
1589  {eCPT_TCI6614_MID_QM_CDMA_Grp1, 0},
1590  {eCPT_TCI6614_MID_QM_CDMA_Grp2, 0},
1591  {eCPT_TCI6614_MID_QM_CDMA_Grp3, 0},
1592  {eCPT_TCI6614_MID_NETCP_Grp0, 2},
1593  {eCPT_TCI6614_MID_NETCP_Grp1, 0},
1594  {eCPT_TCI6614_MID_TAC, 0},
1595  {eCPT_TCI6614_MID_BCP_DIO1, 0},
1596  {eCPT_TCI6614_MID_BCP_CDMA, 0},
1597  {eCPT_TCI6614_MID_BCP_DIO0, 0},
1598  {eCPT_TCI6614_MID_ARM_128_Grp0, 32}
1599 };
1600 
1601 
1602 struct _CPT_MasterIdTable CPT_TCI6612_MasterIDTable[] = {
1603  {eCPT_TCI6612_MID_GEM0, 0},
1604  {eCPT_TCI6612_MID_GEM1, 0},
1605  {eCPT_TCI6612_MID_ARM_64, 0},
1606  {eCPT_TCI6612_MID_GEM0_CFG, 0},
1607  {eCPT_TCI6612_MID_GEM1_CFG, 0},
1608  {eCPT_TCI6612_MID_EDMA0_TC0_RD, 0},
1609  {eCPT_TCI6612_MID_EDMA0_TC0_WR, 0},
1610  {eCPT_TCI6612_MID_EDMA0_TC1_RD, 0},
1611  {eCPT_TCI6612_MID_EDMA0_TC1_WR, 0},
1612  {eCPT_TCI6612_MID_EDMA1_TC0_RD, 0},
1613  {eCPT_TCI6612_MID_EDMA1_TC0_WR, 0},
1614  {eCPT_TCI6612_MID_EDMA1_TC1_RD, 0},
1615  {eCPT_TCI6612_MID_EDMA1_TC1_WR, 0},
1616  {eCPT_TCI6612_MID_EDMA1_TC2_RD, 0},
1617  {eCPT_TCI6612_MID_EDMA1_TC2_WR, 0},
1618  {eCPT_TCI6612_MID_EDMA1_TC3_RD, 0},
1619  {eCPT_TCI6612_MID_EDMA1_TC3_WR, 0},
1620  {eCPT_TCI6612_MID_EDMA2_TC0_RD, 0},
1621  {eCPT_TCI6612_MID_EDMA2_TC0_WR, 0},
1622  {eCPT_TCI6612_MID_EDMA2_TC1_RD, 0},
1623  {eCPT_TCI6612_MID_EDMA2_TC1_WR, 0},
1624  {eCPT_TCI6612_MID_EDMA2_TC2_RD, 0},
1625  {eCPT_TCI6612_MID_EDMA2_TC2_WR, 0},
1626  {eCPT_TCI6612_MID_EDMA2_TC3_RD, 0},
1627  {eCPT_TCI6612_MID_EDMA2_TC3_WR, 0},
1628  {eCPT_TCI6612_MID_SRIO_PKTDMA_Grp0, 2},
1629  {eCPT_TCI6612_MID_SRIO_PKTDMA_Grp1, 0},
1630  {eCPT_TCI6612_MID_DAP, 0},
1631  {eCPT_TCI6612_MID_TPCC0, 0},
1632  {eCPT_TCI6612_MID_TPCC1, 0},
1633  {eCPT_TCI6612_MID_TPCC2, 0},
1634  {eCPT_TCI6612_MID_MSMC, 0},
1635  {eCPT_TCI6612_MID_PCIe, 0},
1636  {eCPT_TCI6612_MID_SRIO_M, 0},
1637  {eCPT_TCI6612_MID_HyperBridge, 0},
1638  {eCPT_TCI6612_MID_QM_SS_Grp0, 0},
1639  {eCPT_TCI6612_MID_QM_SS_Grp1, 0},
1640  {eCPT_TCI6612_MID_QM_SS_Grp2, 0},
1641  {eCPT_TCI6612_MID_QM_SS_Grp3, 0},
1642  {eCPT_TCI6612_MID_AIF_Grp0, 8},
1643  {eCPT_TCI6612_MID_AIF_Grp1, 0},
1644  {eCPT_TCI6612_MID_AIF_Grp2, 0},
1645  {eCPT_TCI6612_MID_AIF_Grp3, 0},
1646  {eCPT_TCI6612_MID_AIF_Grp4, 0},
1647  {eCPT_TCI6612_MID_AIF_Grp5, 0},
1648  {eCPT_TCI6612_MID_AIF_Grp6, 0},
1649  {eCPT_TCI6612_MID_AIF_Grp7, 0},
1650  {eCPT_TCI6612_MID_QM_CDMA_Grp1, 0},
1651  {eCPT_TCI6612_MID_QM_CDMA_Grp3, 0},
1652  {eCPT_TCI6612_MID_NETCP_Grp0, 2},
1653  {eCPT_TCI6612_MID_NETCP_Grp1, 0},
1654  {eCPT_TCI6612_MID_TAC, 0},
1655  {eCPT_TCI6612_MID_BCP_DIO1, 0},
1656  {eCPT_TCI6612_MID_BCP_CDMA, 0},
1657  {eCPT_TCI6612_MID_BCP_DIO0, 0},
1658  {eCPT_TCI6612_MID_ARM_128_Grp0, 32}
1659 };
1660 
1661 #if 0
1662 /* Master id table */
1663 struct _CPT_MasterIdTable {
1664  const char * name;
1665  int master_id;
1666  int group_cnt;
1667 };
1668 
1669 
1670 struct _CPT_MasterIdTable CPT_TCI6614_MasterIDTable[] = {
1671  {CPT_MasterName_GEM0, eCPT_TCI6614_MID_GEM0, 0},
1672  {CPT_MasterName_GEM1, eCPT_TCI6614_MID_GEM1, 0},
1673  {CPT_MasterName_GEM2, eCPT_TCI6614_MID_GEM2, 0},
1674  {CPT_MasterName_GEM3, eCPT_TCI6614_MID_GEM3, 0},
1675  {CPT_MasterName_ARM_64, eCPT_TCI6614_MID_ARM_64, 0},
1676  {CPT_MasterName_GEM0_CFG, eCPT_TCI6614_MID_GEM0_CFG, 0},
1677  {CPT_MasterName_GEM1_CFG, eCPT_TCI6614_MID_GEM1_CFG, 0},
1678  {CPT_MasterName_GEM2_CFG, eCPT_TCI6614_MID_GEM2_CFG, 0},
1679  {CPT_MasterName_GEM3_CFG, eCPT_TCI6614_MID_GEM3_CFG, 0},
1680  {CPT_MasterName_EDMA0_TC0_RD, eCPT_TCI6614_MID_EDMA0_TC0_RD, 0},
1681  {CPT_MasterName_EDMA0_TC0_WR, eCPT_TCI6614_MID_EDMA0_TC0_WR, 0},
1682  {CPT_MasterName_EDMA0_TC1_RD, eCPT_TCI6614_MID_EDMA0_TC1_RD, 0},
1683  {CPT_MasterName_EDMA0_TC1_WR, eCPT_TCI6614_MID_EDMA0_TC1_WR, 0},
1684  {CPT_MasterName_EDMA1_TC0_RD, eCPT_TCI6614_MID_EDMA1_TC0_RD, 0},
1685  {CPT_MasterName_EDMA1_TC0_WR, eCPT_TCI6614_MID_EDMA1_TC0_WR, 0},
1686  {CPT_MasterName_EDMA1_TC1_RD, eCPT_TCI6614_MID_EDMA1_TC1_RD, 0},
1687  {CPT_MasterName_EDMA1_TC1_WR, eCPT_TCI6614_MID_EDMA1_TC1_WR, 0},
1688  {CPT_MasterName_EDMA1_TC2_RD, eCPT_TCI6614_MID_EDMA1_TC2_RD, 0},
1689  {CPT_MasterName_EDMA1_TC2_WR, eCPT_TCI6614_MID_EDMA1_TC2_WR, 0},
1690  {CPT_MasterName_EDMA1_TC3_RD, eCPT_TCI6614_MID_EDMA1_TC3_RD, 0},
1691  {CPT_MasterName_EDMA1_TC3_WR, eCPT_TCI6614_MID_EDMA1_TC3_WR, 0},
1692  {CPT_MasterName_EDMA2_TC0_RD, eCPT_TCI6614_MID_EDMA2_TC0_RD, 0},
1693  {CPT_MasterName_EDMA2_TC0_WR, eCPT_TCI6614_MID_EDMA2_TC0_WR, 0},
1694  {CPT_MasterName_EDMA2_TC1_RD, eCPT_TCI6614_MID_EDMA2_TC1_RD, 0},
1695  {CPT_MasterName_EDMA2_TC1_WR, eCPT_TCI6614_MID_EDMA2_TC1_WR, 0},
1696  {CPT_MasterName_EDMA2_TC2_RD, eCPT_TCI6614_MID_EDMA2_TC2_RD, 0},
1697  {CPT_MasterName_EDMA2_TC2_WR, eCPT_TCI6614_MID_EDMA2_TC2_WR, 0},
1698  {CPT_MasterName_EDMA2_TC3_RD, eCPT_TCI6614_MID_EDMA2_TC3_RD, 0},
1699  {CPT_MasterName_EDMA2_TC3_WR, eCPT_TCI6614_MID_EDMA2_TC3_WR, 0},
1700  {CPT_MasterName_SRIO_PKTDMA_Grp0, eCPT_TCI6614_MID_SRIO_PKTDMA_Grp0, 2},
1701  {CPT_MasterName_SRIO_PKTDMA_Grp1, eCPT_TCI6614_MID_SRIO_PKTDMA_Grp1, 0},
1702  {CPT_MasterName_DAP, eCPT_TCI6614_MID_DAP, 0},
1703  {CPT_MasterName_TPCC0, eCPT_TCI6614_MID_TPCC0, 0},
1704  {CPT_MasterName_TPCC1, eCPT_TCI6614_MID_TPCC1, 0},
1705  {CPT_MasterName_TPCC2, eCPT_TCI6614_MID_TPCC2, 0},
1706  {CPT_MasterName_MSMC, eCPT_TCI6614_MID_MSMC, 0},
1707  {CPT_MasterName_PCIe, eCPT_TCI6614_MID_PCIe, 0},
1708  {CPT_MasterName_SRIO_M, eCPT_TCI6614_MID_SRIO_M, 0},
1709  {CPT_MasterName_HyperBridge, eCPT_TCI6614_MID_HyperBridge, 0},
1710  {CPT_MasterName_QM_SS_Grp0, eCPT_TCI6614_MID_QM_SS_Grp0, 0},
1711  {CPT_MasterName_QM_SS_Grp1, eCPT_TCI6614_MID_QM_SS_Grp1, 0},
1712  {CPT_MasterName_QM_SS_Grp2, eCPT_TCI6614_MID_QM_SS_Grp2, 0},
1713  {CPT_MasterName_QM_SS_Grp3, eCPT_TCI6614_MID_QM_SS_Grp3, 0},
1714  {CPT_MasterName_AIF_Grp0, eCPT_TCI6614_MID_AIF_Grp0, 8},
1715  {CPT_MasterName_AIF_Grp1, eCPT_TCI6614_MID_AIF_Grp1, 0},
1716  {CPT_MasterName_AIF_Grp2, eCPT_TCI6614_MID_AIF_Grp2, 0},
1717  {CPT_MasterName_AIF_Grp3, eCPT_TCI6614_MID_AIF_Grp3, 0},
1718  {CPT_MasterName_AIF_Grp4, eCPT_TCI6614_MID_AIF_Grp4, 0},
1719  {CPT_MasterName_AIF_Grp5, eCPT_TCI6614_MID_AIF_Grp5, 0},
1720  {CPT_MasterName_AIF_Grp6, eCPT_TCI6614_MID_AIF_Grp6, 0},
1721  {CPT_MasterName_AIF_Grp7, eCPT_TCI6614_MID_AIF_Grp7, 0},
1722  {CPT_MasterName_QM_CDMA_Grp0, eCPT_TCI6614_MID_QM_CDMA_Grp0, 4},
1723  {CPT_MasterName_QM_CDMA_Grp1, eCPT_TCI6614_MID_QM_CDMA_Grp1, 0},
1724  {CPT_MasterName_QM_CDMA_Grp2, eCPT_TCI6614_MID_QM_CDMA_Grp2, 0},
1725  {CPT_MasterName_QM_CDMA_Grp3, eCPT_TCI6614_MID_QM_CDMA_Grp3, 0},
1726  {CPT_MasterName_NETCP_Grp0, eCPT_TCI6614_MID_NETCP_Grp0, 2},
1727  {CPT_MasterName_NETCP_Grp1, eCPT_TCI6614_MID_NETCP_Grp1, 0},
1728  {CPT_MasterName_TAC, eCPT_TCI6614_MID_TAC, 0},
1729  {CPT_MasterName_BCP_DIO1, eCPT_TCI6614_MID_BCP_DIO1, 0},
1730  {CPT_MasterName_BCP_CDMA, eCPT_TCI6614_MID_BCP_CDMA, 0},
1731  {CPT_MasterName_BCP_DIO0, eCPT_TCI6614_MID_BCP_DIO0, 0},
1732  {CPT_MasterName_ARM_128_Grp0, eCPT_TCI6614_MID_ARM_128_Grp0, 32}
1733 };
1734 
1735 
1736 struct _CPT_MasterIdTable CPT_TCI6612_MasterIDTable[] = {
1737  {CPT_MasterName_GEM0, eCPT_TCI6612_MID_GEM0, 0},
1738  {CPT_MasterName_GEM1, eCPT_TCI6612_MID_GEM1, 0},
1739  {CPT_MasterName_ARM_64, eCPT_TCI6612_MID_ARM_64, 0},
1740  {CPT_MasterName_GEM0_CFG, eCPT_TCI6612_MID_GEM0_CFG, 0},
1741  {CPT_MasterName_GEM1_CFG, eCPT_TCI6612_MID_GEM1_CFG, 0},
1742  {CPT_MasterName_EDMA0_TC0_RD, eCPT_TCI6612_MID_EDMA0_TC0_RD, 0},
1743  {CPT_MasterName_EDMA0_TC0_WR, eCPT_TCI6612_MID_EDMA0_TC0_WR, 0},
1744  {CPT_MasterName_EDMA0_TC1_RD, eCPT_TCI6612_MID_EDMA0_TC1_RD, 0},
1745  {CPT_MasterName_EDMA0_TC1_WR, eCPT_TCI6612_MID_EDMA0_TC1_WR, 0},
1746  {CPT_MasterName_EDMA1_TC0_RD, eCPT_TCI6612_MID_EDMA1_TC0_RD, 0},
1747  {CPT_MasterName_EDMA1_TC0_WR, eCPT_TCI6612_MID_EDMA1_TC0_WR, 0},
1748  {CPT_MasterName_EDMA1_TC1_RD, eCPT_TCI6612_MID_EDMA1_TC1_RD, 0},
1749  {CPT_MasterName_EDMA1_TC1_WR, eCPT_TCI6612_MID_EDMA1_TC1_WR, 0},
1750  {CPT_MasterName_EDMA1_TC2_RD, eCPT_TCI6612_MID_EDMA1_TC2_RD, 0},
1751  {CPT_MasterName_EDMA1_TC2_WR, eCPT_TCI6612_MID_EDMA1_TC2_WR, 0},
1752  {CPT_MasterName_EDMA1_TC3_RD, eCPT_TCI6612_MID_EDMA1_TC3_RD, 0},
1753  {CPT_MasterName_EDMA1_TC3_WR, eCPT_TCI6612_MID_EDMA1_TC3_WR, 0},
1754  {CPT_MasterName_EDMA2_TC0_RD, eCPT_TCI6612_MID_EDMA2_TC0_RD, 0},
1755  {CPT_MasterName_EDMA2_TC0_WR, eCPT_TCI6612_MID_EDMA2_TC0_WR, 0},
1756  {CPT_MasterName_EDMA2_TC1_RD, eCPT_TCI6612_MID_EDMA2_TC1_RD, 0},
1757  {CPT_MasterName_EDMA2_TC1_WR, eCPT_TCI6612_MID_EDMA2_TC1_WR, 0},
1758  {CPT_MasterName_EDMA2_TC2_RD, eCPT_TCI6612_MID_EDMA2_TC2_RD, 0},
1759  {CPT_MasterName_EDMA2_TC2_WR, eCPT_TCI6612_MID_EDMA2_TC2_WR, 0},
1760  {CPT_MasterName_EDMA2_TC3_RD, eCPT_TCI6612_MID_EDMA2_TC3_RD, 0},
1761  {CPT_MasterName_EDMA2_TC3_WR, eCPT_TCI6612_MID_EDMA2_TC3_WR, 0},
1762  {CPT_MasterName_SRIO_PKTDMA_Grp0, eCPT_TCI6612_MID_SRIO_PKTDMA_Grp0, 2},
1763  {CPT_MasterName_SRIO_PKTDMA_Grp1, eCPT_TCI6612_MID_SRIO_PKTDMA_Grp1, 0},
1764  {CPT_MasterName_DAP, eCPT_TCI6612_MID_DAP, 0},
1765  {CPT_MasterName_TPCC0, eCPT_TCI6612_MID_TPCC0, 0},
1766  {CPT_MasterName_TPCC1, eCPT_TCI6612_MID_TPCC1, 0},
1767  {CPT_MasterName_TPCC2, eCPT_TCI6612_MID_TPCC2, 0},
1768  {CPT_MasterName_MSMC, eCPT_TCI6612_MID_MSMC, 0},
1769  {CPT_MasterName_PCIe, eCPT_TCI6612_MID_PCIe, 0},
1770  {CPT_MasterName_SRIO_M, eCPT_TCI6612_MID_SRIO_M, 0},
1771  {CPT_MasterName_HyperBridge, eCPT_TCI6612_MID_HyperBridge, 0},
1772  {CPT_MasterName_QM_SS_Grp0, eCPT_TCI6612_MID_QM_SS_Grp0, 0},
1773  {CPT_MasterName_QM_SS_Grp1, eCPT_TCI6612_MID_QM_SS_Grp1, 0},
1774  {CPT_MasterName_QM_SS_Grp2, eCPT_TCI6612_MID_QM_SS_Grp2, 0},
1775  {CPT_MasterName_QM_SS_Grp3, eCPT_TCI6612_MID_QM_SS_Grp3, 0},
1776  {CPT_MasterName_AIF_Grp0, eCPT_TCI6612_MID_AIF_Grp0, 8},
1777  {CPT_MasterName_AIF_Grp1, eCPT_TCI6612_MID_AIF_Grp1, 0},
1778  {CPT_MasterName_AIF_Grp2, eCPT_TCI6612_MID_AIF_Grp2, 0},
1779  {CPT_MasterName_AIF_Grp3, eCPT_TCI6612_MID_AIF_Grp3, 0},
1780  {CPT_MasterName_AIF_Grp4, eCPT_TCI6612_MID_AIF_Grp4, 0},
1781  {CPT_MasterName_AIF_Grp5, eCPT_TCI6612_MID_AIF_Grp5, 0},
1782  {CPT_MasterName_AIF_Grp6, eCPT_TCI6612_MID_AIF_Grp6, 0},
1783  {CPT_MasterName_AIF_Grp7, eCPT_TCI6612_MID_AIF_Grp7, 0},
1784  {CPT_MasterName_QM_CDMA_Grp0, eCPT_TCI6612_MID_QM_CDMA_Grp0, 4},
1785  {CPT_MasterName_QM_CDMA_Grp1, eCPT_TCI6612_MID_QM_CDMA_Grp1, 0},
1786  {CPT_MasterName_QM_CDMA_Grp2, eCPT_TCI6612_MID_QM_CDMA_Grp2, 0},
1787  {CPT_MasterName_QM_CDMA_Grp3, eCPT_TCI6612_MID_QM_CDMA_Grp3, 0},
1788  {CPT_MasterName_NETCP_Grp0, eCPT_TCI6612_MID_NETCP_Grp0, 2},
1789  {CPT_MasterName_NETCP_Grp1, eCPT_TCI6612_MID_NETCP_Grp1, 0},
1790  {CPT_MasterName_TAC, eCPT_TCI6612_MID_TAC, 0},
1791  {CPT_MasterName_BCP_DIO1, eCPT_TCI6612_MID_BCP_DIO1, 0},
1792  {CPT_MasterName_BCP_CDMA, eCPT_TCI6612_MID_BCP_CDMA, 0},
1793  {CPT_MasterName_BCP_DIO0, eCPT_TCI6612_MID_BCP_DIO0, 0},
1794  {CPT_MasterName_ARM_128_Grp0, eCPT_TCI6612_MID_ARM_128_Grp0, 32}
1795 };
1796 #endif
1797 #endif
1798 //
1800 // Common Register Maps
1801 //
1803 #ifdef RUNTIME_DEVICE_SELECT
1804 #define reg_rd32(addr) cTools_reg_rd32((uint32_t)addr)
1805 #define reg_wr32(addr, value) cTools_reg_wr32((uint32_t)addr, value)
1806 #else
1807 #define reg_rd32(addr) (*addr)
1808 #define reg_wr32(addr,value) (*addr = value)
1809 #endif
1810 
1811 
1812 
1813 //CP Tracer must know address (Destination Register) of STM unit to forward messages
1814 // This must be set to the channel zero timestamp address.
1815 const uint32_t STM_BaseAddress = 0x20000000;
1816 const uint32_t STM_ChResolution = 0x1000;
1817 const uint32_t STM_Ch0MsgEnd = 0x20000800;
1818 
1819 //PSC_Base & register definitions
1820 #define PSC_BASE 0x02350000
1821 
1822 #define CPT_POWER_DOMAIN 1
1823 #define CPT_POWER_TRANSITION (1 << CPT_POWER_DOMAIN)
1824 #define CPT_LPCS_NUM 5
1825 #define CPT_TIMEOUT_CNT 0xFFFF
1826 #define CPT_PDSTAT_ON 0x1
1827 #define CPT_PDSTAT_POR_VALID 0x300
1828 #define CPT_MDSTAT_ENABLED 0x3
1829 
1830 //Common Power and Domain definitions
1831 #define PSC_PTCMD ((volatile uint32_t *) (PSC_BASE+ 0x120))
1832 #define PSC_PTSTAT ((volatile uint32_t *) (PSC_BASE+ 0x128))
1833 
1834 #define PSC_PDSTAT(n) ((volatile uint32_t *) (PSC_BASE+0x200+4*n))
1835 #define PSC_PDCTL(n) ((volatile uint32_t *) (PSC_BASE+0x300+4*n))
1836 #define PSC_PDCFG(n) ((volatile uint32_t *) (PSC_BASE+0x400+4*n))
1837 
1838 #define PSC_MDCFG(n) ((volatile uint32_t *) (PSC_BASE+0x600+4*n))
1839 #define PSC_MDSTAT(n) ((volatile uint32_t *) (PSC_BASE+0x800+4*n))
1840 #define PSC_MDCTL(n) ((volatile uint32_t *) (PSC_BASE+0xA00+4*n))
1841 
1842 //CP Tracer register offsets
1843 #define CPT_REGOFF_Identification 0x00
1844 #define CPT_REGOFF_TransactionQualifier 0x04
1845 #define CPT_REGOFF_ModuleControlAndStatus 0x08
1846 #define CPT_REGOFF_SlidingTimeWindow 0x0C
1847 #define CPT_REGOFF_BusMasterSelect_TP0_A 0x10
1848 #define CPT_REGOFF_BusMasterSelect_TP0_B 0x14
1849 #define CPT_REGOFF_BusMasterSelect_TP0_C 0x18
1850 #define CPT_REGOFF_BusMasterSelect_TP0_D 0x1C
1851 #define CPT_REGOFF_BusMasterSelect_TP1_A 0x20
1852 #define CPT_REGOFF_BusMasterSelect_TP1_B 0x24
1853 #define CPT_REGOFF_BusMasterSelect_TP1_C 0x28
1854 #define CPT_REGOFF_BusMasterSelect_TP1_D 0x2C
1855 #define CPT_REGOFF_EndAddress 0x30
1856 #define CPT_REGOFF_StartAddress 0x34
1857 #define CPT_REGOFF_AccessStatus 0x38
1858 #define CPT_REGOFF_AccessStatusPacing 0x3C
1859 #define CPT_REGOFF_AddressMask 0x40
1860 #define CPT_REGOFF_DestinationAddress 0x44
1861 #define CPT_REGOFF_MessagePriority 0x48
1862 #define CPT_REGOFF_Ownership 0x4c
1863 #define CPT_REGOFF_ThroughPut0 0x50
1864 #define CPT_REGOFF_ThroughPut1 0x54
1865 #define CPT_REGOFF_AccumulatedWaitTime 0x58
1866 #define CPT_REGOFF_NumberOfGrants 0x5c
1867 #define CPT_REGOFF_InterruptRawStatus 0x60
1868 #define CPT_REGOFF_InterruptMaskStatus 0x64
1869 #define CPT_REGOFF_InterruptMaskSet 0x68
1870 #define CPT_REGOFF_InterruptMaskClear 0x6C
1871 #define CPT_REGOFF_InterruptEOI 0x70
1872 
1873 #define CPT_REGSPACE_BYTES 128
1874 
1875 
1876 // CP Tracer register definitions
1877 // Note that ba may be passed as an unsigned int *
1878 #define CPT_ID_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_Identification ))
1879 #define CPT_QUAL_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_TransactionQualifier ))
1880 #define CPT_MODCTL_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_ModuleControlAndStatus ))
1881 #define CPT_STWINDOW_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_SlidingTimeWindow))
1882 #define CPT_MSTSELA_TP0_REGIndex(ba, r) ((volatile uint32_t *)((uint32_t)(ba) + ((r) * 4) + CPT_REGOFF_BusMasterSelect_TP0_A))
1883 #define CPT_MSTSELA_TP0_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP0_A))
1884 #define CPT_MSTSELB_TP0_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP0_B))
1885 #define CPT_MSTSELC_TP0_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP0_C))
1886 #define CPT_MSTSELD_TP0_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP0_D))
1887 #define CPT_MSTSELA_TP1_REGIndex(ba, r) ((volatile uint32_t *)((uint32_t)(ba) + ((r) * 4) + CPT_REGOFF_BusMasterSelect_TP1_A))
1888 #define CPT_MSTSELA_TP1_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP1_A))
1889 #define CPT_MSTSELB_TP1_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP1_B))
1890 #define CPT_MSTSELC_TP1_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP1_C))
1891 #define CPT_MSTSELD_TP1_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP1_D))
1892 #define CPT_ENDADDR(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_EndAddress ))
1893 #define CPT_STARTADDR(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_StartAddress ))
1894 #define CPT_ACCSTATUS(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_AccessStatus ))
1895 #define CPT_PACING(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_AccessStatusPacing ))
1896 #define CPT_ADDRMASK(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_AddressMask ))
1897 #define CPT_DSTADDR(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_DestinationAddress ))
1898 #define CPT_MSGPRI(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_MessagePriority ))
1899 #define CPT_OWNERSHIP(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_Ownership ))
1900 #define CPT_TP0(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_ThroughPut0 ))
1901 #define CPT_TP1(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_ThroughPut1 ))
1902 #define CPT_ACCUMWAIT(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_AccumulatedWaitTime ))
1903 #define CPT_GRANTCNT(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_NumberOfGrants ))
1904 #define CPT_INTRAW(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_InterruptRawStatus ))
1905 #define CPT_INTSTATUS(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_InterruptMaskStatus ))
1906 #define CPT_INTSET(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_InterruptMaskSet ))
1907 #define CPT_INTCLR(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_InterruptMaskClear ))
1908 #define CPT_INTEOI(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_InterruptEOI ))
1909 
1910 // Type Key
1911 // R - read only
1912 // W - write only
1913 // R/W - read or write
1914 // WC - Write-to-clear (Write 1 to clear bit, write 0 has no effect)
1915 // WS - Write-to-set (Write 1 to set bit, write 0 has no effect)
1916 // WD - Write-to-decrement field (Decrement register field by value written - reads have no effect)
1917 
1918 //Identification and Version Register - Read only
1919 //Bits Type Reset Name Description
1920 //31 R 1 ID Scheme Id register format
1921 //29:28 X 0 Reserved
1922 //27:16 R 0xE89 ID
1923 //15:11 R 0 RTL Version Changes with Spec changes and bug fixes. Resets to 0 when
1924 // Major or Minor numbers updated.
1925 //10:8 R 0x1 Major Version Major feature addition, does not change for bug fixes or
1926 // feature scaling (ex: size of a RAM)
1927 //7:6 R 0 Custom Version Special version for a specific device
1928 //5:0 R 0x2 Minor Version Changes with feature scaling (ex: size of a RAM), does not
1929 // change for bug fixes
1930 // Note - one may be tempted to replace reg with CPT_ID_REG(ba) but in the code this would not allow
1931 // reading the register once and then checking multiple bits
1932 #define CPT_GET_IDREG_MINOR(reg) ( reg & 0x1F )
1933 #define CPT_GET_IDREG_CUSTOM(reg) ( ( reg & 0xC0 ) >> 6 )
1934 #define CPT_GET_IDREG_MAJOR(reg) ( ( reg & 0xE00 ) >> 8 )
1935 #define CPT_GET_IDREG_RTL(reg) ( ( reg & 0xF800 ) >> 11 )
1936 #define CPT_GET_IDREG_FUNC(reg) ( ( reg & 0x0FFF0000 ) >> 16 )
1937 #define CPT_GET_IDREG_IDSCH(reg) ( ( reg & 0x80000000 ) >> 31 )
1938 
1939 //Transaction Qualifier Register - All bits are read/write except Emu_status bit
1940 //Bits Type Reset Name Description
1941 //31:28 X Reserved
1942 //27 R/W 0 Emu0_trig 1: emu0_out is asserted when event B has occurred
1943 // 0: emu0_out is not asserted by CP_tracer
1944 //26 R/W 0 Emu1_trig 1: emu1_out is asserted when qualified event B has occurred
1945 // 0: emu1_out is not asserted by CP_tracer
1946 //25 R 1 Emu_status Set by the hardware and read only
1947 // 1: CP_tracer is enabled to monitor CBA events
1948 // 0: CP_tracer is not enabled to monitor CBA events.
1949 // When Qualif_EMU = 0, EMU_status is set to 1.
1950 // When Qualif_EMU= 1, EMU_status is set to 1 when EMU0 is asserted. EMU_status is set to 0 when EMU1 is asserted.
1951 //24 R/W 0 Qualif_EMU 1: only the CBA events happening between assertion of EMU0 and assertion of EMU1 are sent to qualifier.
1952 // 0: all CBA events sent to qualifier
1953 //23:20 R/W 0 Qualif_dtype_trig 0bxxx0: Capture event Bs with dtype 0 (CPU Data Access) for emu0/1_out triggering
1954 // 0bxxx1: Exclude event Bs with dtype 0 (CPU Data Access) from emu0/1_out triggering
1955 // 0bxx0x: Capture event Bs with dtype 1 (CPU Instruction Access) for emu0/1_out triggering
1956 // 0bxx1x: Exclude event Bs with dtype 1 (CPU Instruction Access) from emu0/1_out triggering
1957 // 0bx0xx: Capture event Bs with dtype 2 (DMA Access) for emu0/1_out triggering
1958 // 0bx1xx: Exclude event Bs with dtype 2 (DMA Access) from emu0/1_out triggering
1959 // 0b0xxx: Capture event Bs with dtype 3 (RESERVED) for emu0/1_out triggering
1960 // 0b1xxx: Exclude event Bs with dtype 3 (RESERVED) from emu0/1_out triggering
1961 //19:16 R/W 0 Qualif_dtype_TH1 0bxxx0: Capture event Bs with dtype 0 (CPU Data Access) for throughput 1 calculation
1962 // 0bxxx1: Exclude event Bs with dtype 0 (CPU Data Access) from throughput 1 calculation
1963 // 0bxx0x: Capture event Bs with dtype 1 (CPU Instruction Access) for throughput 1 calculation
1964 // 0bxx1x: Exclude event Bs with dtype 1 (CPU Instruction Access) from throughput 1 calculation
1965 // 0bx0xx: Capture event Bs with dtype 2 (DMA Access) for throughput 1 calculation
1966 // 0bx1xx: Exclude event Bs with dtype 2 (DMA Access) from throughput 1 calculation
1967 // 0b0xxx: Capture event Bs with dtype 3 (RESERVED) for throughput 1 calculation
1968 // 0b1xxx: Exclude event Bs with dtype 3 (RESERVED) from throughput 1 calculation
1969 //15:12 R/W 0 Qualif_dtype_TH0 0bxxx0: Capture event Bs with dtype 0 (CPU Data Access) for throughput 0 calculation
1970 // 0bxxx1: Exclude event Bs with dtype 0 (CPU Data Access) from throughput 0 calculation
1971 // 0bxx0x: Capture event Bs with dtype 1 (CPU Instruction Access) for throughput 0 calculation
1972 // 0bxx1x: Exclude event Bs with dtype 1 (CPU Instruction Access) from throughput 0 calculation
1973 // 0bx0xx: Capture event Bs with dtype 2 (DMA Access) for throughput 0 calculation
1974 // 0bx1xx: Exclude event Bs with dtype 2 (DMA Access) from throughput 0 calculation
1975 // 0b0xxx: Capture event Bs with dtype 3 (RESERVED) for throughput 0 calculation
1976 // 0b1xxx: Exclude event Bs with dtype 3 (RESERVED) from throughput 0 calculation
1977 //11:8 R/W 0 Qualif_dtype_trace 0bxxx0: Capture event Bs with dtype 0 (CPU Data Access) for event B export
1978 // 0bxxx1: Exclude event Bs with dtype 0 (CPU Data Access) from event B export
1979 // 0bxx0x: Capture event Bs with dtype 1 (CPU Instruction Access) for event B export
1980 // 0bxx1x: Exclude event Bs with dtype 1 (CPU Instruction Access) from event B export
1981 // 0bx0xx: Capture event Bs with dtype 2 (DMA Access) for event B export
1982 // 0bx1xx: Exclude event Bs with dtype 2 (DMA Access) from event B export
1983 // 0b0xxx: Capture event Bs with dtype 3 (RESERVED) for event B export
1984 // 0b1xxx: Exclude event Bs with dtype 3 (RESERVED) from event B export
1985 //7:6 R/W 0 Qualif_trig 0b11: Capture both read and write transactions for emu0/1_out trigger
1986 // 0b01: Only capture read transactions for emu0/1_out trigger
1987 // 0b10: Only capture write transactions for emu0/1_out trigger
1988 // 0b00: Do not capture either read or write transaction for emu0/1_out trigger (Disables emu0/1_out triggering)
1989 //5:4 R/W 0 Qualif_TH1 0b11: Capture both read and write transactions for throughput 1
1990 // 0b01: Only capture read transactions for throughput 1
1991 // 0b10: Only capture write transactions for throughput 1
1992 // 0b00: Do not capture either read or write transaction for throughput 1 (Disables throughput count 1)
1993 //3:2 R/W 0 Qualif_TH0 0b11: Capture both read and write transactions for throughput 0
1994 // 0b01: Only capture read transactions for throughput 0
1995 // 0b10: Only capture write transactions for throughput 0
1996 // 0b00: Do not capture either read or write transaction for throughput 0 (Disables throughput count 0)
1997 //1:0 R/W 0 Qualif_trace 0b11: Capture both read and write transactions for event B trace export
1998 // 0b01: Only capture read transactions for event B trace export
1999 // 0b10: Only capture write transactions for event B trace export
2000 // 0b00: Do not capture either read or write transaction for event B trace export
2001 #define CPT_GET_QUAL_TRIGOUT(reg) ( ( reg & 0xC0000000 ) >> 26 )
2002 #define CPT_GET_QUAL_TRIGSTAT(reg) ( ( reg & 0x02000000 ) >> 25 )
2003 #define CPT_GET_QUAL_TRIGIN(reg) ( ( reg & 0x01000000 ) >> 24 )
2004 #define CPT_GET_QUAL_TRIGOUTDTYPE(reg) ( ( reg & 0x00F00000 ) >> 20 )
2005 #define CPT_GET_QUAL_TH1DTYPE(reg) ( ( reg & 0x000F0000 ) >> 16 )
2006 #define CPT_GET_QUAL_TH0DTYPE(reg) ( ( reg & 0x0000F000 ) >> 12 )
2007 #define CPT_GET_QUAL_EVTBDTYPE(reg) ( ( reg & 0x00000F00 ) >> 8 )
2008 #define CPT_GET_QUAL_TRIGOUTRW(reg) ( ( reg & 0x000000C0 ) >> 6 )
2009 #define CPT_GET_QUAL_TH1RW(reg) ( ( reg & 0x00000030 ) >> 4 )
2010 #define CPT_GET_QUAL_TH0RW(reg) ( ( reg & 0x0000000C ) >> 2 )
2011 #define CPT_GET_QUAL_EVTBRW(reg) ( reg & 0x3 )
2012 
2013 #define CPT_SET_QUAL_TRIGOUT(qual) ( ( qual & 0x3 ) << 26 )
2014 #define CPT_SET_QUAL_TRIGIN(qual) ( ( qual & 1 ) << 24 )
2015 #define CPT_SET_QUAL_TRIGOUTDTYPE(qual) ( ( qual & 0xF ) << 20 )
2016 #define CPT_SET_QUAL_TH1DTYPE(qual) ( ( qual & 0xF ) << 16 )
2017 #define CPT_SET_QUAL_TH0DTYPE(qual) ( ( qual & 0xF ) << 12 )
2018 #define CPT_SET_QUAL_EVTBDTYPE(qual) ( ( qual & 0xF ) << 8 )
2019 #define CPT_SET_QUAL_TRIGOUTRW(qual) ( ( qual & 0x3 ) << 6 )
2020 #define CPT_SET_QUAL_TH1RW(qual) ( ( qual & 0x3 ) << 4 )
2021 #define CPT_SET_QUAL_TH0RW(qual) ( ( qual & 0x3 ) << 2 )
2022 #define CPT_SET_QUAL_EVTBRW(qual) ( qual & 0x3 )
2023 
2024 #define CPT_QUAL_TRIGOUT_MASK ( 0x3 << 26 )
2025 #define CPT_QUAL_TRIGIN_MASK ( 0x1 << 24 )
2026 #define CPT_QUAL_TRIGOUTDTYPE_MASK ( 0xF << 20 )
2027 #define CPT_QUAL_TH1DTYPE_MASK ( 0xF << 16 )
2028 #define CPT_QUAL_TH0DTYPE_MASK ( 0xF << 12 )
2029 #define CPT_QUAL_EVTBDTYPE_MASK ( 0xF << 8 )
2030 #define CPT_QUAL_TRIGOUTRW_MASK ( 0x3 << 6 )
2031 #define CPT_QUAL_TH1RW_MASK ( 0x3 << 4 )
2032 #define CPT_QUAL_TH0RW_MASK ( 0x3 << 2 )
2033 #define CPT_QUAL_EVTBRW_MASK ( 0x3 )
2034 
2035 #define CPT_SET_QUAL_ALLDISABLED 0x000000FF
2036 #define CPT_TRIG_QUAL_MASK 0x0DF000C0
2037 #define CPT_TH1_QUAL_MASK 0x000F0030
2038 #define CPT_TH0_QUAL_MASK 0x0000F00C
2039 #define CPT_EVTB_QUAL_MASK 0x00000F03
2040 
2041 //Module Control and Status Register
2042 //Bits Type Reset Name Description
2043 //31:16 R/W 0 Upper_address_bits These are the upper address bits used for all address filtering.
2044 // They function as the MSBs [47:32] of both start address and end
2045 // address. See the definition of the address_mode field for which
2046 // bits of this address are valid. Only the valid bits as indicated
2047 // by the address_mode field are writable, all other bits are
2048 // read-only 0.
2049 //15 R/W 0 Excl_addr_filter_en 1: Enable exclusive address filtering
2050 // 0: Disable exclusive address filtering
2051 //14 R/W 0 Acc_wait_cnt_en 1: Enables accumulated wait counter
2052 // 0: Disables accumulated wait counter
2053 //13 R/W 0 Num_grant_Cnt_en 1: Enables num grant counter
2054 // 0: Disables num grant counter
2055 //12:8 R/W 0 Export_select 0b00000: no export capability
2056 // 0bxxxx1: export statistics message when the sliding time window is expired.
2057 // 0bxxx1x: export event trace based on filtering for event B
2058 // 0bxx1xx: export event trace for event C
2059 // 0bx1xxx: export event trace for event E
2060 // 0b1xxxx: export access status message based on pacing
2061 //7:5 R Tie-Off Address_mode This register reflects the value of the address_mode_mode tie off and is read-only. The value indicates how many address bits on the event_<slv>_arb_address are valid. For example, if it indicates 32 bits then bits 31:0 are used for address filtering and all others must be tied to 0. 36 bits means 35:0 are used etc...
2062 // 0'b000: 32 bit address
2063 // 0'b001: 36 bit address
2064 // 0'b010: 40 bit address
2065 // 0'b011: 44 bit address
2066 // 0'b100: 48 bit address
2067 // Other values reserved.
2068 //
2069 // Note: event_<slv>_arb_address bits that are not used must be tied to zero.
2070 // If they are non-zero, address filtering will not work correctly.
2071 //4:0 R Tie-Off SID Read only. It is used to differentiate the CP_tracer modules if a
2072 // device has multiple CP_tracers on chip. It is a tie-off value.
2073 #define CPT_GET_MODCTL_UPPERADDRBITS(reg) ( ( reg & 0xFFFF0000 ) >> 16 )
2074 #define CPT_GET_MODCTL_ADDRFLTEN(reg) ( ( reg & 0x00008000 ) >> 15 )
2075 #define CPT_GET_MODCTL_WAITCNTEN(reg) ( ( reg & 0x00004000 ) >> 14 )
2076 #define CPT_GET_MODCTL_GRANTCNTEN(reg) ( ( reg & 0x00002000 ) >> 13 )
2077 #define CPT_GET_MODCTL_EXPSEL(reg) ( ( reg & 0x00001F00 ) >> 8 )
2078 #define CPT_GET_MODCTL_ADDRMODE(reg) ( ( reg & 0x000000E0 ) >> 5 )
2079 #define CPT_GET_MODCTL_SID(reg) ( reg & 0x1F )
2080 
2081 #define CPT_SET_MODCTL_UPPERADDRBITS(cntl) ( ( cntl & 0xFFFF ) << 16 )
2082 #define CPT_SET_MODCTL_ADDRFLTEN(cntl) ( ( cntl & 0x1 ) << 15 )
2083 #define CPT_SET_MODCTL_WAITCNTEN(cntl) ( ( cntl & 0x1 ) << 14 )
2084 #define CPT_SET_MODCTL_GRANTCNTEN(cntl) ( ( cntl & 0x1 ) << 13 )
2085 #define CPT_SET_MODCTL_EXPSEL(cntl) ( ( cntl & 0x1F ) << 8 )
2086 
2087 #define CPT_SET_MODCTL_CNTEN(cntl) ( ( cntl & 0x3 ) << 13 )
2088 
2089 #define CPT_MODCTL_UPPERADDRBITS_MASK ( 0xFFFF << 16)
2090 #define CPT_MODCTL_ADDRFLTEN_MASK ( 0x1 << 15 )
2091 #define CPT_MODCTL_WAITCNTEN_MASK ( 0x1 << 14 )
2092 #define CPT_MODCTL_GRANTCNTEN_MASK ( 0x1 << 13 )
2093 #define CPT_MODCTL_EXPSEL_MASK ( 0x1F << 8 )
2094 
2095 #define CPT_MODCTL_ADDRMODE_32_TEST(value) ( 0xFFFFFFFF & value )
2096 #define CPT_MODCTL_ADDRMODE_36_TEST(value) ( 0xFFFFFFF0 & value )
2097 #define CPT_MODCTL_ADDRMODE_40_TEST(value) ( 0xFFFFFF00 & value )
2098 #define CPT_MODCTL_ADDRMODE_44_TEST(value) ( 0xFFFFF000 & value )
2099 #define CPT_MODCTL_ADDRMODE_48_TEST(value) ( 0xFFFF0000 & value )
2100 
2101 
2102 
2103 
2104 #define CPT_SET_MODCTL_ALLDISABLED 0x0
2105 
2106 
2107 //Sliding Time Window
2108 //Bits Type Reset Name Description
2109 //31:0 R/W 0xFFFFFFFF Sliding Time Window Specifies a sliding window in terms of the CP_TRACER clock
2110 // over which the statistics are to be collected. An interrupt
2111 // is generated (if enabled) when the sliding time window expires.
2112 // * Value is in cp_tracer clocks
2113 // * Counter starts as soon as a non-zero value is written to
2114 // this register
2115 // * Writing a 0x00000000 to this register will disable the
2116 // sliding time window counter
2117 // * Counter is disabled at reset despite having a non-zero value
2118 
2119 //Master ID Select Register A for Throughput0 and Event Trace
2120 //Bits Type Reset Name Description
2121 //31:0 R/W 0 Master ID Select Grp A Master ID select Group A contains the master ID select for master
2122 // ID 0 to 31. Bit 0 enables mstid 0, bit 1 enables mstid 1 etc.
2123 // If enabled, the corresponding mstid is selected for throughput0
2124 // calculation. The selected mstid is also used to filter event B
2125 // and E for event trace export.
2126 
2127 #define CPT_SET_MASTER_SEL_NONE 0
2128 #define CPT_SET_MASTER_SEL_ALL 0xFFFFFFFF
2129 #define CPT_NUM_MASTER_SEL_REGS 4
2130 
2131 //Master ID Select Register B for Throughput0 and Event Trace
2132 //Bits Type Reset Name Description
2133 //31:0 R/W 0 Master ID Select Grp B Master ID select Group A contains the master ID select for master
2134 // ID 32 to 63. Bit 0 enables mstid 32, bit 1 enables mstid 33 etc.
2135 // If enabled, the corresponding mstid is selected for throughput0
2136 // calculation. The selected mstid is also used to filter event B
2137 // and E for event trace export.
2138 
2139 //Master ID Select Register C for Throughput0 and Event Trace
2140 //Bits Type Reset Name Description
2141 //31:0 R/W 0 Master ID Select Grp C Master ID select Group A contains the master ID select for master
2142 // ID 64 to 95. Bit 0 enables mstid 64, bit 1 enables mstid 65 etc.
2143 // If enabled, the corresponding mstid is selected for throughput0
2144 // calculation. The selected mstid is also used to filter event B
2145 // and E for event trace export.
2146 
2147 //Master ID Select Register D for Throughput0 and Event Trace
2148 //Bits Type Reset Name Description
2149 //31:0 R/W 0 Master ID Select Grp D Master ID select Group A contains the master ID select for master
2150 // ID 96 to 127. Bit 0 enables mstid 96, bit 1 enables mstid 97 etc.
2151 // If enabled, the corresponding mstid is selected for throughput0
2152 // calculation. The selected mstid is also used to filter event B
2153 // and E for event trace export.
2154 
2155 //Master ID Select Register A for Throughput1 and Event Trace
2156 //Bits Type Reset Name Description
2157 //31:0 R/W 0 Master ID Select Grp A Master ID select Group A contains the master ID select for master
2158 // ID 0 to 31. Bit 0 enables mstid 0, bit 1 enables mstid 1 etc.
2159 // If enabled, the corresponding mstid is selected for throughput0
2160 // calculation.
2161 
2162 //Master ID Select Register B for Throughput1 and Event Trace
2163 //Bits Type Reset Name Description
2164 //31:0 R/W 0 Master ID Select Grp B Master ID select Group A contains the master ID select for master
2165 // ID 32 to 63. Bit 0 enables mstid 32, bit 1 enables mstid 33 etc.
2166 // If enabled, the corresponding mstid is selected for throughput1
2167 // calculation.
2168 
2169 //Master ID Select Register C for Throughput1 and Event Trace
2170 //Bits Type Reset Name Description
2171 //31:0 R/W 0 Master ID Select Grp C Master ID select Group A contains the master ID select for master
2172 // ID 64 to 95. Bit 0 enables mstid 64, bit 1 enables mstid 65 etc.
2173 // If enabled, the corresponding mstid is selected for throughput1
2174 // calculation.
2175 
2176 //Master ID Select Register D for Throughput1 and Event Trace
2177 //Bits Type Reset Name Description
2178 //31:0 R/W 0 Master ID Select Grp D Master ID select Group A contains the master ID select for master
2179 // ID 96 to 127. Bit 0 enables mstid 96, bit 1 enables mstid 97 etc.
2180 // If enabled, the corresponding mstid is selected for throughput1
2181 // calculation.
2182 
2183 //End Address Register
2184 //Bits Type Reset Name Description
2185 //31:0 R/W 0 End Address Memory address. Combined with the start address register, it
2186 // provides the address range for filtering function for both
2187 // throughput statistics and event B export. Only the transactions
2188 // within the address range between and including [start address,
2189 // end address] will be captured for throughput. For event trace
2190 // export, the event which overlaps [start address, end address]
2191 // will be captured to export. When the end address is set to 0x0,
2192 // it disables the address filtering function. When the address
2193 // filtering is disabled, the transactions are captured regardless
2194 // of the memory range.
2195 
2196 //Start Address Register
2197 //Bits Type Reset Name Description
2198 //31:0 R/W 0 Start Address Memory address for the low address range.
2199 
2200 //Access Status Register
2201 //Bits Type Reset Name Description
2202 //31:0 R/W 0 Access Status Each bit is correspondent to one master event I/F.
2203 // 1: means a transaction arrived in that master event I/F
2204 // during the previous time sliding window
2205 // 0: means no transactions arrived in that master event I/F
2206 // during the previous time sliding window
2207 // The access status is set by the hardware when event A arrives
2208 // at the master event I/F. The access status is reset to 0x0 when
2209 // the sliding window has expired.
2210 
2211 //Access Pacing Register
2212 //Bits Type Reset Name Description
2213 //31:0 R/W 0 Pacing 0x000000: If export_select[4] is set and an access has occurred
2214 // since the previous access status message was sent,
2215 // then the access status message is sent out whenever
2216 // the sliding time window expires.
2217 // 0xXXXXXX: If this field is non-zero, export_select[4] is set,
2218 // and an access has occurred since the previous access
2219 // status message was sent, then the access status message
2220 // is sent out as long as X cycles have occurred since the
2221 // last message where X is the value of this field.
2222 // NOTE: if the sliding time window expires, then the access
2223 // status message will be sent out regardless of pacing,
2224 // and the pacing counter will be reset. If this value is
2225 // greater than the sliding time window then the access
2226 // status message will only be sent out whenever the
2227 // sliding time window expires.
2228 
2229 #define CPT_GET_PACING(reg) ( reg & 0x00FFFFFF )
2230 #define CPT_SET_PACING(reg) ( reg & 0x00FFFFFF )
2231 
2232 //Address Mask Register
2233 //Bits Type Reset Name Description
2234 //5:0 R/W 0 Address Bits Select Event messages export 10 bits of the address associated with the
2235 // event. This field indicates which 10 contiguous bits of the
2236 // possible 48 bits are exported. The value indicates the lowest bit
2237 // and the next 9 bits are exported also:
2238 // * 0 – Bits 09:0 are exported
2239 // * 1 – Bits 10:1 are exported
2240 // * 2 – Bits 11:2 are exported
2241 // * 3-36 - …..
2242 // * 37 – Bits 46:37 are exported
2243 // * 38 – Bits 47:38 are exported
2244 // * 63-38 – Reserved. Behavior undefined.
2245 //
2246 #define CPT_GET_ADDRESSMASK(reg) ( reg & 0x1F )
2247 #define CPT_SET_ADDRESSMASK(mask) ( mask & 0x1F )
2248 
2249 //Destination Address Register
2250 //Bits Type Reset Name Description
2251 //31:2 R/W 0 Destination Address Destination Address bits 31:2 for the outgoing VBUSP
2252 // transactions from the master interface. The address must be word
2253 // aligned, so the 2 LSBS (1:0) are always 0
2254 //1:0 R 0 Reserved
2255 
2256 //This register simply needs to be set to the address of the debug_SS_STM module
2257 
2258 //Message Priority Register
2259 //Bits Type Reset Name Description
2260 //31:15 R 0 Reserved
2261 //14:12 R/W 0x7 Stat_msg_prio Vbusp priority and epriority associated with statistics messages
2262 //11:9 R/W 0x7 Event_e_msg_prio Vbusp priority and epriority associated with event e message export
2263 //8:6 R/W 0x7 Event_c_msg_prio Vbusp priority and epriority associated with event c message export
2264 //5:3 R/W 0x7 Event_b_msg_prio Vbusp priority and epriority associated with event b message export
2265 //2:0 R/W 0x7 Access_msg_prio Vbusp priority and epriority associated with access status message export
2266 #define CPT_GET_MSGPRI_STAT(reg) ( ( reg & 0x00007000 ) >> 12 )
2267 #define CPT_GET_MSGPRI_EVTE(reg) ( ( reg & 0x00000E00 ) >> 9 )
2268 #define CPT_GET_MSGPRI_EVTB(reg) ( ( reg & 0x00000038 ) >> 3 )
2269 #define CPT_GET_MSGPRI_ACC(reg) ( reg & 0x7 )
2270 #define CPT_SET_MSGPRI_STAT(msgpri) ( ( msgpri & 0x7 ) << 12 )
2271 #define CPT_SET_MSGPRI_EVTE(msgpri) ( ( msgpri & 7 ) << 9 )
2272 #define CPT_SET_MSGPRI_EVTC(msgpri) ( ( msgpri & 7 ) << 6 )
2273 #define CPT_SET_MSGPRI_EVTB(msgpri) ( ( msgpri & 7 ) << 3 )
2274 #define CPT_SET_MSGPRI_ACC(msgpri) ( msgpri & 0x7 )
2275 
2276 
2277 //Ownership Register
2278 //Bits Type Reset Name Description
2279 //31:1 R 0 Reserved
2280 //0 R/W 0 Ownership This bit can be used by software to indicate that this cp_tracer
2281 // is “owned” by a process for configuration. It is simply a
2282 // read/write register that is read as the last value written.
2283 // It provides no interlock capability so software is responsible
2284 // for implementing a semaphore using this bit and handle any possible
2285 // race conditions that may occur.
2286 #define CPT_GET_OWNERSHIP(reg) ( reg & 0x1 )
2287 #define CPT_SET_OWNERSHIP ( 0x1 )
2288 #define CPT_CLR_OWNERSHIP ( 0x0 )
2289 
2290 //Throughput0 Register
2291 //Bits Type Reset Name Description
2292 //31:24 R 0 Reserved
2293 //23:0 R 0 Throughput The accumulated throughput during the last sliding time window
2294 // based on all throughput0 qualifiers and filters.
2295 #define CPT_GET_THROUGHPUTCNT0(reg) ( reg & 0xFFFFFF )
2296 
2297 //Throughput1 Register
2298 //Bits Type Reset Name Description
2299 //31:24 R 0 Reserved
2300 //23:0 R 0 Throughput The accumulated throughput during the last sliding time window
2301 // based on all throughput1 qualifiers and filters.
2302 #define CPT_GET_THROUGHPUTCNT1(reg) ( reg & 0xFFFFFF )
2303 
2304 
2305 //Accumulative Waiting Time Register
2306 //Bits Type Reset Name Description
2307 //31:24 R 0 Reserved
2308 //23:0 R 0 Accum Waiting Time The accumulative time that arbiter is busy during a sliding
2309 // time window. It is set when the sliding time window is expired.
2310 #define CPT_GET_WAITTIMECNT(reg) ( reg & 0xFFFFFF )
2311 
2312 
2313 //Number of Grants Register
2314 //Bits Type Reset Name Description
2315 //31:24 R 0 Reserved
2316 //23:0 R 0 Number of Grants The number of times that arbiter made grants during a sliding
2317 // timing window. It is set when the sliding timing window is expired.
2318 #define CPT_GET_GRANTCNT(reg) ( reg & 0xFFFFFF )
2319 
2320 //5.25 Interrupt Raw Status Register
2321 //Bits Type Reset Name Description
2322 //31:1 R 0 Reserved
2323 //0 R/WS 0 Interrupt_Raw This bit is set when the sliding time window expires regardless
2324 // of the interrupt mask set bit in the Interrupt Mask Set register.
2325 // This bit remains set until the host CPU clears it. Writing a 1 to
2326 // this bit sets it and writing a 0 has no effect.
2327 #define CPT_GET_RAWINTSTATE(reg) ( reg & 0x1 )
2328 #define CPT_SET_RAWINTSTATE ( 0x1 )
2329 
2330 //Interrupt Masked Status Register
2331 //Bits Type Reset Name Description
2332 //31:1 R 0 Reserved
2333 //0 R/WC 0 Interrupt_Masked This bit is set when the sliding time window expires and the
2334 // interrupt mask set bit in the Interrupt Mask Set register is set.
2335 // This bit remains set until the host CPU clears the raw status bit.
2336 // This bit also drives the module output port. Writing a 1 to this
2337 // bit clears the raw status (and therefore this status) and writing
2338 // a 0 has no effect.
2339 #define CPT_GET_MASKINTSTATE(reg) ( reg & 0x1 )
2340 #define CPT_CLR_MASKINTSTATE ( 0x1 )
2341 
2342 
2343 //Interrupt Masked Set Register
2344 //Bits Type Reset Name Description
2345 //31:1 R 0 Reserved
2346 //0 R/WS 0 Interrupt Mask When set to 1, this bit enables the Interrupt_Masked Status bit.
2347 // Writing a 1 to this bit sets it and writing a 0 has no effect.
2348 #define CPT_GET_MASKINTENABLE(reg) ( reg & 0x1 )
2349 #define CPT_SET_MASKINTENABLE ( 0x1 )
2350 
2351 //Interrupt Masked Clear Register
2352 //Bits Type Reset Name Description
2353 //31:1 R 0 Reserved
2354 //0 R/WC 0 Interrupt Mask Writing a 1 to this bit clears the Interrupt Mask and disables
2355 // the Interrupt_Masked bit. Writing a 0 has no effect
2356 #define CPT_GET_MASKINTDISABLE(reg) ( reg & 0x1 )
2357 #define CPT_SET_MASKINTDISABLE ( 0x1 )
2358 
2359 #endif // _DOXYGEN_IGNORE
2360 #endif //__CPT_COMMON_H
2361 
2362 #ifdef __cplusplus
2363 }
2364 #endif