48 #ifndef _DOXYGEN_IGNORE
59 typedef volatile uint32_t reg32_t;
69 #define CPT_MUTEXID_MAJOR 1
70 #define CPT_MUTEXID_MINOR_MASK 0xFFFF
71 #define CPT_MUTEXID(CPT_ModId) (CPT_MUTEXID_MAJOR | (CPT_MUTEXID_MINOR_MASK & CPT_ModId))
77 typedef struct _eCPT_MultiMID {
78 #ifndef RUNTIME_DEVICE_SELECT
88 #define CPT_ATTR_BUFSIZE 256
93 static const char CPT_ModName_MSMC_0[] =
"MSMC_0";
94 static const char CPT_ModName_MSMC_1[] =
"MSMC_1";
95 static const char CPT_ModName_MSMC_2[] =
"MSMC_2";
96 static const char CPT_ModName_MSMC_3[] =
"MSMC_3";
97 static const char CPT_ModName_QM_MST[] =
"QM_M";
98 static const char CPT_ModName_DDR[] =
"DDR";
99 static const char CPT_ModName_SM[] =
"SM";
100 static const char CPT_ModName_QM_CFG[] =
"QM_CFG";
101 static const char CPT_ModName_CFG[] =
"CFG";
102 static const char CPT_ModName_L2_0[] =
"L2_0";
103 static const char CPT_ModName_L2_1[] =
"L2_1";
104 static const char CPT_ModName_L2_2[] =
"L2_2";
105 static const char CPT_ModName_L2_3[] =
"L2_3";
106 static const char CPT_ModName_RAC[] =
"RAC";
107 static const char CPT_ModName_RAC_CFG[] =
"RAC_CFG";
108 static const char CPT_ModName_TAC[] =
"TAC";
111 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
129 #endif //_STM_Logging
133 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000,
152 const uint8_t CPT_ModDivByFactors[] = { 2,
188 static const char CPT_ModName_MSMC_0[] =
"MSMC_0";
189 static const char CPT_ModName_MSMC_1[] =
"MSMC_1";
190 static const char CPT_ModName_MSMC_2[] =
"MSMC_2";
191 static const char CPT_ModName_MSMC_3[] =
"MSMC_3";
192 static const char CPT_ModName_QM_MST[] =
"QM_M";
193 static const char CPT_ModName_DDR[] =
"DDR";
194 static const char CPT_ModName_SM[] =
"SM";
195 static const char CPT_ModName_QM_CFG[] =
"QM_CFG";
196 static const char CPT_ModName_CFG[] =
"CFG";
197 static const char CPT_ModName_L2_0[] =
"L2_0";
201 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
217 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000,
230 const uint8_t CPT_ModDivByFactors[] = { 2,
258 static const char CPT_ModName_MSMC_0[] =
"MSMC_0";
259 static const char CPT_ModName_MSMC_1[] =
"MSMC_1";
260 static const char CPT_ModName_MSMC_2[] =
"MSMC_2";
261 static const char CPT_ModName_MSMC_3[] =
"MSMC_3";
262 static const char CPT_ModName_QM_MST[] =
"QM_M";
263 static const char CPT_ModName_DDR[] =
"DDR";
264 static const char CPT_ModName_SM[] =
"SM";
265 static const char CPT_ModName_QM_CFG[] =
"QM_CFG";
266 static const char CPT_ModName_CFG[] =
"CFG";
267 static const char CPT_ModName_L2_0[] =
"L2_0";
268 static const char CPT_ModName_L2_1[] =
"L2_1";
272 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
289 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000,
303 const uint8_t CPT_ModDivByFactors[] = { 2,
332 static const char CPT_ModName_MSMC_0[] =
"MSMC_0";
333 static const char CPT_ModName_MSMC_1[] =
"MSMC_1";
334 static const char CPT_ModName_MSMC_2[] =
"MSMC_2";
335 static const char CPT_ModName_MSMC_3[] =
"MSMC_3";
336 static const char CPT_ModName_QM_MST[] =
"QM_M";
337 static const char CPT_ModName_DDR[] =
"DDR";
338 static const char CPT_ModName_SM[] =
"SM";
339 static const char CPT_ModName_QM_CFG[] =
"QM_CFG";
340 static const char CPT_ModName_CFG[] =
"CFG";
341 static const char CPT_ModName_L2_0[] =
"L2_0";
342 static const char CPT_ModName_L2_1[] =
"L2_1";
343 static const char CPT_ModName_L2_2[] =
"L2_2";
344 static const char CPT_ModName_L2_3[] =
"L2_3";
348 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
367 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000,
383 const uint8_t CPT_ModDivByFactors[] = { 2,
414 static const char CPT_ModName_MSMC_0[] =
"MSMC_0";
415 static const char CPT_ModName_MSMC_1[] =
"MSMC_1";
416 static const char CPT_ModName_MSMC_2[] =
"MSMC_2";
417 static const char CPT_ModName_MSMC_3[] =
"MSMC_3";
418 static const char CPT_ModName_QM_MST[] =
"QM_M";
419 static const char CPT_ModName_DDR[] =
"DDR";
420 static const char CPT_ModName_SM[] =
"SM";
421 static const char CPT_ModName_QM_CFG[] =
"QM_CFG";
422 static const char CPT_ModName_CFG[] =
"CFG";
423 static const char CPT_ModName_L2_0[] =
"L2_0";
424 static const char CPT_ModName_L2_1[] =
"L2_1";
425 static const char CPT_ModName_L2_2[] =
"L2_2";
426 static const char CPT_ModName_L2_3[] =
"L2_3";
427 static const char CPT_ModName_L2_4[] =
"L2_4";
428 static const char CPT_ModName_L2_5[] =
"L2_5";
429 static const char CPT_ModName_L2_6[] =
"L2_6";
430 static const char CPT_ModName_L2_7[] =
"L2_7";
434 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
457 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000,
477 const uint8_t CPT_ModDivByFactors[] = { 2,
513 static const char CPT_ModName_MSMC_0[] =
"MSMC_0";
514 static const char CPT_ModName_MSMC_1[] =
"MSMC_1";
515 static const char CPT_ModName_MSMC_2[] =
"MSMC_2";
516 static const char CPT_ModName_MSMC_3[] =
"MSMC_3";
517 static const char CPT_ModName_QM_MST[] =
"QM_M";
518 static const char CPT_ModName_DDR[] =
"DDR";
519 static const char CPT_ModName_SM[] =
"SM";
520 static const char CPT_ModName_QM_CFG[] =
"QM_P";
521 static const char CPT_ModName_CFG[] =
"CFG";
522 static const char CPT_ModName_L2_0[] =
"L2_0";
523 static const char CPT_ModName_L2_1[] =
"L2_1";
524 static const char CPT_ModName_SCR_6P_A[] =
"SCR_6P_A";
527 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
545 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000,
560 const uint8_t CPT_ModDivByFactors[] = { 2,
587 #if defined(_TCI6614)
589 #if defined(_STM_Logging) || defined(RUNTIME_DEVICE_SELECT)
590 static const char CPT_TCI6614_ModName_MSMC_0[] =
"MSMC_0";
591 static const char CPT_TCI6614_ModName_MSMC_1[] =
"MSMC_1";
592 static const char CPT_TCI6614_ModName_MSMC_2[] =
"MSMC_2";
593 static const char CPT_TCI6614_ModName_MSMC_3[] =
"MSMC_3";
594 static const char CPT_TCI6614_ModName_QM_MST[] =
"QM_M";
595 static const char CPT_TCI6614_ModName_DDR[] =
"DDR";
596 static const char CPT_TCI6614_ModName_SM[] =
"SM";
597 static const char CPT_TCI6614_ModName_QM_CFG[] =
"QM_CFG";
598 static const char CPT_TCI6614_ModName_CFG[] =
"CFG";
599 static const char CPT_TCI6614_ModName_L2_0[] =
"L2_0";
600 static const char CPT_TCI6614_ModName_L2_1[] =
"L2_1";
601 static const char CPT_TCI6614_ModName_L2_2[] =
"L2_2";
602 static const char CPT_TCI6614_ModName_L2_3[] =
"L2_3";
603 static const char CPT_TCI6614_ModName_RAC[] =
"RAC";
604 static const char CPT_TCI6614_ModName_RAC_CFG[] =
"RAC_CFG";
605 static const char CPT_TCI6614_ModName_TAC[] =
"TAC";
606 static const char CPT_TCI6614_ModName_SCR_6P_A[] =
"SCR_6P_A";
607 static const char CPT_TCI6614_ModName_DDR_2[] =
"DDR_2";
610 #ifdef RUNTIME_DEVICE_SELECT
611 const char * pCPT_TCI6614_ModNames[] = {
613 const char * pCPT_ModNames[] = {
615 CPT_TCI6614_ModName_MSMC_0,
616 CPT_TCI6614_ModName_MSMC_1,
617 CPT_TCI6614_ModName_MSMC_2,
618 CPT_TCI6614_ModName_MSMC_3,
619 CPT_TCI6614_ModName_QM_MST,
620 CPT_TCI6614_ModName_DDR,
621 CPT_TCI6614_ModName_SM,
622 CPT_TCI6614_ModName_QM_CFG,
623 CPT_TCI6614_ModName_CFG,
624 CPT_TCI6614_ModName_L2_0,
625 CPT_TCI6614_ModName_L2_1,
626 CPT_TCI6614_ModName_L2_2,
627 CPT_TCI6614_ModName_L2_3,
628 CPT_TCI6614_ModName_RAC,
629 CPT_TCI6614_ModName_RAC_CFG,
630 CPT_TCI6614_ModName_TAC,
631 CPT_TCI6614_ModName_SCR_6P_A,
632 CPT_TCI6614_ModName_DDR_2
635 #endif //_STM_Logging
639 #ifdef RUNTIME_DEVICE_SELECT
640 const uint32_t CPT_TCI6614_BaseAddressTable[] = {
642 const uint32_t CPT_BaseAddressTable[] = {
665 #ifdef RUNTIME_DEVICE_SELECT
666 const uint8_t CPT_TCI6614_ModDivByFactors[] = {
668 const uint8_t CPT_ModDivByFactors[] = {
690 #ifdef RUNTIME_DEVICE_SELECT
691 const CPT_MultiMID_t CPT_TCI6614_MultiMID[] = {
692 {eCPT_TCI6614_MID_SRIO_PKTDMA_Grp0, 2},
693 {eCPT_TCI6614_MID_QM_SS_Grp0, 4},
694 {eCPT_TCI6614_MID_AIF_Grp0, 8},
695 {eCPT_TCI6614_MID_QM_CDMA_Grp0, 4},
696 {eCPT_TCI6614_MID_NETCP_Grp0, 2},
697 {eCPT_TCI6614_MID_ARM_128_Grp0, 32}
700 const CPT_MultiMID_t CPT_MultiMID[] = {
702 {eCPT_MID_QM_SS_Grp0, 4},
703 {eCPT_MID_AIF_Grp0, 8},
705 {eCPT_MID_NETCP_Grp0, 2},
706 {eCPT_MID_ARM_128_Grp0, 32}
711 #if defined(_TCI6612)
713 #if defined(_STM_Logging) || defined(RUNTIME_DEVICE_SELECT)
714 static const char CPT_TCI6612_ModName_MSMC_0[] =
"MSMC_0";
715 static const char CPT_TCI6612_ModName_MSMC_1[] =
"MSMC_1";
716 static const char CPT_TCI6612_ModName_MSMC_2[] =
"MSMC_2";
717 static const char CPT_TCI6612_ModName_MSMC_3[] =
"MSMC_3";
718 static const char CPT_TCI6612_ModName_QM_MST[] =
"QM_M";
719 static const char CPT_TCI6612_ModName_DDR[] =
"DDR";
720 static const char CPT_TCI6612_ModName_SM[] =
"SM";
721 static const char CPT_TCI6612_ModName_QM_CFG[] =
"QM_CFG";
722 static const char CPT_TCI6612_ModName_CFG[] =
"CFG";
723 static const char CPT_TCI6612_ModName_L2_0[] =
"L2_0";
724 static const char CPT_TCI6612_ModName_L2_1[] =
"L2_1";
725 static const char CPT_TCI6612_ModName_RAC[] =
"RAC";
726 static const char CPT_TCI6612_ModName_RAC_CFG[] =
"RAC_CFG";
727 static const char CPT_TCI6612_ModName_TAC[] =
"TAC";
728 static const char CPT_TCI6612_ModName_SCR_6P_A[] =
"SCR_6P_A";
729 static const char CPT_TCI6612_ModName_DDR_2[] =
"DDR_2";
732 #ifdef RUNTIME_DEVICE_SELECT
733 const char * pCPT_TCI6612_ModNames[] = {
735 const char * pCPT_ModNames[] = {
737 CPT_TCI6612_ModName_MSMC_0,
738 CPT_TCI6612_ModName_MSMC_1,
739 CPT_TCI6612_ModName_MSMC_2,
740 CPT_TCI6612_ModName_MSMC_3,
741 CPT_TCI6612_ModName_QM_MST,
742 CPT_TCI6612_ModName_DDR,
743 CPT_TCI6612_ModName_SM,
744 CPT_TCI6612_ModName_QM_CFG,
745 CPT_TCI6612_ModName_CFG,
746 CPT_TCI6612_ModName_L2_0,
747 CPT_TCI6612_ModName_L2_1,
748 CPT_TCI6612_ModName_RAC,
749 CPT_TCI6612_ModName_RAC_CFG,
750 CPT_TCI6612_ModName_TAC,
751 CPT_TCI6612_ModName_SCR_6P_A,
752 CPT_TCI6612_ModName_DDR_2
755 #endif //_STM_Logging
759 #ifdef RUNTIME_DEVICE_SELECT
760 const uint32_t CPT_TCI6612_BaseAddressTable[] = {
762 const uint32_t CPT_BaseAddressTable[] = {
783 #ifdef RUNTIME_DEVICE_SELECT
784 const uint8_t CPT_TCI6612_ModDivByFactors[] = {
786 const uint8_t CPT_ModDivByFactors[] = {
806 #ifdef RUNTIME_DEVICE_SELECT
807 const CPT_MultiMID_t CPT_TCI6612_MultiMID[] = {
808 {eCPT_TCI6612_MID_SRIO_PKTDMA_Grp0, 2},
809 {eCPT_TCI6612_MID_QM_SS_Grp0, 4},
810 {eCPT_TCI6612_MID_AIF_Grp0, 8},
811 {eCPT_TCI6612_MID_QM_CDMA_Grp0, 4},
812 {eCPT_TCI6612_MID_NETCP_Grp0, 2},
813 {eCPT_TCI6612_MID_ARM_128_Grp0, 32}
816 const CPT_MultiMID_t CPT_MultiMID[] = {
818 {eCPT_MID_QM_SS_Grp0, 4},
819 {eCPT_MID_AIF_Grp0, 8},
821 {eCPT_MID_NETCP_Grp0, 2},
822 {eCPT_MID_ARM_128_Grp0, 32}
827 #if defined(_C66AK2Hxx)
830 static const char CPT_ModName_MSMC_0[] =
"MSMC_0";
831 static const char CPT_ModName_MSMC_1[] =
"MSMC_1";
832 static const char CPT_ModName_MSMC_2[] =
"MSMC_2";
833 static const char CPT_ModName_MSMC_3[] =
"MSMC_3";
834 static const char CPT_ModName_QM_MST[] =
"QM_M";
835 static const char CPT_ModName_DDR3A[] =
"DDR3A";
836 static const char CPT_ModName_SM[] =
"SM";
837 static const char CPT_ModName_QM_CFG1[] =
"QM_CFG1";
838 static const char CPT_ModName_CFG[] =
"CFG";
839 static const char CPT_ModName_L2_0[] =
"L2_0";
840 static const char CPT_ModName_L2_1[] =
"L2_1";
841 static const char CPT_ModName_L2_2[] =
"L2_2";
842 static const char CPT_ModName_L2_3[] =
"L2_3";
843 static const char CPT_ModName_L2_4[] =
"L2_4";
844 static const char CPT_ModName_L2_5[] =
"L2_5";
845 static const char CPT_ModName_L2_6[] =
"L2_6";
846 static const char CPT_ModName_L2_7[] =
"L2_7";
847 static const char CPT_ModName_RAC[] =
"RAC";
848 static const char CPT_ModName_RAC_CFG1[] =
"RAC_CFG1";
849 static const char CPT_ModName_TAC[] =
"TAC";
850 static const char CPT_ModName_QM_CFG2[] =
"QM_CFG2";
851 static const char CPT_ModName_RAC_CFG2[] =
"RAC_CFG2";
852 static const char CPT_ModName_DDR3B[] =
"DDR3B";
853 static const char CPT_ModName_BCR_CFG[] =
"BCR_CFG";
854 static const char CPT_ModName_TPCC_0_4[] =
"TPCC_0_4";
855 static const char CPT_ModName_TPCC_1_2_3[] =
"TPCC_1_2_3";
856 static const char CPT_ModName_INTC_CFG[] =
"INTC_CFG";
857 static const char CPT_ModName_MSMC_4[] =
"MSMC_4";
858 static const char CPT_ModName_MSMC_5[] =
"MSMC_5";
859 static const char CPT_ModName_MSMC_6[] =
"MSMC_6";
860 static const char CPT_ModName_MSMC_7[] =
"MSMC_7";
861 static const char CPT_ModName_SPI_ROM_EMIF16[] =
"SPI_ROM_EMIF16";
864 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
882 CPT_ModName_RAC_CFG1,
885 CPT_ModName_RAC_CFG2,
888 CPT_ModName_TPCC_0_4,
889 CPT_ModName_TPCC_1_2_3,
890 CPT_ModName_INTC_CFG,
895 CPT_ModName_SPI_ROM_EMIF16
898 #endif //_STM_Logging
901 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000,
936 const uint8_t CPT_ModDivByFactors[] = { 1,
981 eCPT_MID_QM2_CDMA_Grp0,
983 eCPT_MID_QM1_CDMA_Grp0,
991 #if defined(_66AK2Exx)
994 static const char CPT_ModName_MSMC_0[] =
"MSMC_0";
995 static const char CPT_ModName_MSMC_1[] =
"MSMC_1";
996 static const char CPT_ModName_MSMC_2[] =
"MSMC_2";
997 static const char CPT_ModName_MSMC_3[] =
"MSMC_3";
998 static const char CPT_ModName_QM_MST[] =
"QM_M";
999 static const char CPT_ModName_DDR3A[] =
"DDR3A";
1000 static const char CPT_ModName_SM[] =
"SM";
1001 static const char CPT_ModName_QM_CFG1[] =
"QM_CFG1";
1002 static const char CPT_ModName_CFG[] =
"SCR3_CFG";
1003 static const char CPT_ModName_L2_0[] =
"L2_0";
1004 static const char CPT_ModName_QM_CFG2[] =
"QM_CFG2";
1005 static const char CPT_ModName_TPCC_0_4[] =
"TPCC_0_4";
1006 static const char CPT_ModName_TPCC_1_2_3[] =
"TPCC_1_2_3";
1007 static const char CPT_ModName_INTC_CFG[] =
"INTC_CFG";
1008 static const char CPT_ModName_MSMC_4[] =
"MSMC_4";
1009 static const char CPT_ModName_MSMC_5[] =
"MSMC_5";
1010 static const char CPT_ModName_MSMC_6[] =
"MSMC_6";
1011 static const char CPT_ModName_MSMC_7[] =
"MSMC_7";
1012 static const char CPT_ModName_SPI_ROM_EMIF16[] =
"SPI_ROM_EMIF16";
1013 static const char CPT_ModName_NETCP_USB_CFG[] =
"NETCP_USB_CFG";
1014 static const char CPT_ModName_PCIE1_CFG[] =
"PCIE1_CFG";
1017 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
1024 CPT_ModName_QM_CFG1,
1027 CPT_ModName_QM_CFG2,
1028 CPT_ModName_TPCC_0_4,
1029 CPT_ModName_TPCC_1_2_3,
1030 CPT_ModName_INTC_CFG,
1035 CPT_ModName_SPI_ROM_EMIF16,
1036 CPT_ModName_NETCP_USB_CFG,
1037 CPT_ModName_PCIE1_CFG
1040 #endif //_STM_Logging
1043 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000,
1067 const uint8_t CPT_ModDivByFactors[] = { 1,
1093 const CPT_MultiMID_t CPT_MultiMID[] = {
1096 eCPT_MID_NETCP_GLOBAL1_Grp0,
1100 eCPT_MID_QM1_CDMA_Grp0,
1102 eCPT_MID_NETCP_LOCAL_Grp0,
1104 eCPT_MID_NETCP_Grp0,
1110 #if defined (_TCI6630K2L)
1113 static const char CPT_ModName_MSMC_0[] =
"MSMC_0";
1114 static const char CPT_ModName_MSMC_1[] =
"MSMC_1";
1115 static const char CPT_ModName_MSMC_2[] =
"MSMC_2";
1116 static const char CPT_ModName_MSMC_3[] =
"MSMC_3";
1117 static const char CPT_ModName_QM_MST[] =
"QM_M";
1118 static const char CPT_ModName_DDR3A[] =
"DDR3A";
1119 static const char CPT_ModName_SM[] =
"SM";
1120 static const char CPT_ModName_QM_CFG1[] =
"QM_CFG1";
1121 static const char CPT_ModName_CFG[] =
"CFG";
1122 static const char CPT_ModName_L2_0[] =
"L2_0";
1123 static const char CPT_ModName_L2_1[] =
"L2_1";
1124 static const char CPT_ModName_L2_2[] =
"L2_2";
1125 static const char CPT_ModName_L2_3[] =
"L2_3";
1126 static const char CPT_ModName_RAC[] =
"RAC";
1127 static const char CPT_ModName_RAC_CFG1[] =
"RAC_CFG1";
1128 static const char CPT_ModName_TAC[] =
"TAC";
1129 static const char CPT_ModName_QM_CFG2[] =
"QM_CFG2";
1130 static const char CPT_ModName_OSR_PCIE1_CFG[] =
"OSR_PCIE1_CFG";
1131 static const char CPT_ModName_TPCC_0_4[] =
"TPCC_0";
1132 static const char CPT_ModName_TPCC_1_2_3[] =
"TPCC_1_2";
1133 static const char CPT_ModName_INTC_CFG[] =
"INTC_CFG";
1134 static const char CPT_ModName_MSMC_4[] =
"MSMC_4";
1135 static const char CPT_ModName_MSMC_5[] =
"MSMC_5";
1136 static const char CPT_ModName_MSMC_6[] =
"MSMC_6";
1137 static const char CPT_ModName_MSMC_7[] =
"MSMC_7";
1138 static const char CPT_ModName_SPI_ROM_EMIF16[] =
"SPI_ROM_EMIF16";
1139 static const char CPT_ModName_CPT_CFG_3P_U[] =
"CFG_3P_U";
1142 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
1149 CPT_ModName_QM_CFG1,
1156 CPT_ModName_RAC_CFG1,
1158 CPT_ModName_QM_CFG2,
1159 CPT_ModName_OSR_PCIE1_CFG,
1160 CPT_ModName_TPCC_0_4,
1161 CPT_ModName_TPCC_1_2_3,
1162 CPT_ModName_INTC_CFG,
1167 CPT_ModName_SPI_ROM_EMIF16,
1168 CPT_ModName_CPT_CFG_3P_U
1171 #endif //_STM_Logging
1174 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000,
1204 const uint8_t CPT_ModDivByFactors[] = { 1,
1238 eCPT_MID_IQN_CDMA_Grp0,
1240 eCPT_MID_QM1_CDMA_Grp0,
1242 eCPT_MID_NETCP_LOCAL_Grp0,
1244 eCPT_MID_NETCP_GLOBAL_Grp0,
1249 #if defined (_66AK2Gxx)
1252 static const char CPT_ModName_MSMC_0[] =
"MSMC_0";
1253 static const char CPT_ModName_DDR3[] =
"DDR3";
1254 static const char CPT_ModName_L2_0[] =
"L2_0";
1255 static const char CPT_ModName_PCIE[] =
"PCIE";
1256 static const char CPT_ModName_DXB[] =
"DXB";
1257 static const char CPT_ModName_MCASP_MCBSP[] =
"MCASP_MCBSP";
1258 static const char CPT_ModName_GPMC_MMC_QSPI[] =
"GPMC_MMC_QSPI";
1259 static const char CPT_ModName_TPCC[] =
"TPCC0";
1260 static const char CPT_ModName_ALWAYSON_CFG[] =
"ALWAYSON_CFG";
1261 static const char CPT_ModName_GIC[] =
"GIC";
1262 static const char CPT_ModName_CIC[] =
"CIC";
1263 static const char CPT_ModName_ROM_SPI[] =
"ROM_SPI";
1264 static const char CPT_ModName_ALWAYSON_MAIN[] =
"ALWAYSON_MAIN";
1265 static const char CPT_ModName_ICSS_ASRC[] =
"ICSS_ASRC";
1266 static const char CPT_ModName_CFG[] =
"CFG";
1269 const char * pCPT_ModNames[] = { CPT_ModName_MSMC_0,
1274 CPT_ModName_MCASP_MCBSP,
1275 CPT_ModName_GPMC_MMC_QSPI,
1278 CPT_ModName_ALWAYSON_CFG,
1281 CPT_ModName_ROM_SPI,
1282 CPT_ModName_ALWAYSON_MAIN,
1283 CPT_ModName_ICSS_ASRC
1286 #endif //_STM_Logging
1289 const uint32_t CPT_BaseAddressTable[] = { 0x01d00000,
1307 const uint8_t CPT_ModDivByFactors[] = { 1,
1324 const CPT_MultiMID_t CPT_MultiMID[] = { eCPT_MID_NSSL_Grp0,
1328 eCPT_MID_DSSUL_Grp0,
1333 #ifdef RUNTIME_DEVICE_SELECT
1337 static const char CPT_MasterName_GEM0[] =
"DSP0";
1338 static const char CPT_MasterName_GEM1[] =
"DSP1";
1339 static const char CPT_MasterName_GEM2[] =
"DSP2";
1340 static const char CPT_MasterName_GEM3[] =
"DSP3";
1341 static const char CPT_MasterName_ARM_64[] =
"ARM_64";
1342 static const char CPT_MasterName_GEM0_CFG[] =
"DSP0_CFG";
1343 static const char CPT_MasterName_GEM1_CFG[] =
"DSP1_CFG";
1344 static const char CPT_MasterName_GEM2_CFG[] =
"DSP2_CFG";
1345 static const char CPT_MasterName_GEM3_CFG[] =
"DSP3_CFG";
1346 static const char CPT_MasterName_EDMA0_TC0_RD[] =
"EDMA0_TC0_RD";
1347 static const char CPT_MasterName_EDMA0_TC0_WR[] =
"EDMA0_TC0_WR";
1348 static const char CPT_MasterName_EDMA0_TC1_RD[] =
"EDMA0_TC1_RD";
1349 static const char CPT_MasterName_EDMA0_TC1_WR[] =
"EDMA0_TC1_WR";
1350 static const char CPT_MasterName_EDMA1_TC0_RD[] =
"EDMA1_TC0_RD";
1351 static const char CPT_MasterName_EDMA1_TC0_WR[] =
"EDMA1_TC0_WR";
1352 static const char CPT_MasterName_EDMA1_TC1_RD[] =
"EDMA1_TC1_RD";
1353 static const char CPT_MasterName_EDMA1_TC1_WR[] =
"EDMA1_TC1_WR";
1354 static const char CPT_MasterName_EDMA1_TC2_RD[] =
"EDMA1_TC2_RD";
1355 static const char CPT_MasterName_EDMA1_TC2_WR[] =
"EDMA1_TC2_WR";
1356 static const char CPT_MasterName_EDMA1_TC3_RD[] =
"EDMA1_TC3_RD";
1357 static const char CPT_MasterName_EDMA1_TC3_WR[] =
"EDMA1_TC3_WR";
1358 static const char CPT_MasterName_EDMA2_TC0_RD[] =
"EDMA2_TC0_RD";
1359 static const char CPT_MasterName_EDMA2_TC0_WR[] =
"EDMA2_TC0_WR";
1360 static const char CPT_MasterName_EDMA2_TC1_RD[] =
"EDMA2_TC1_RD";
1361 static const char CPT_MasterName_EDMA2_TC1_WR[] =
"EDMA2_TC1_WR";
1362 static const char CPT_MasterName_EDMA2_TC2_RD[] =
"EDMA2_TC2_RD";
1363 static const char CPT_MasterName_EDMA2_TC2_WR[] =
"EDMA2_TC2_WR";
1364 static const char CPT_MasterName_EDMA2_TC3_RD[] =
"EDMA2_TC3_RD";
1365 static const char CPT_MasterName_EDMA2_TC3_WR[] =
"EDMA2_TC3_WR";
1366 static const char CPT_MasterName_SRIO_PKTDMA_Grp0[] =
"SRIO_PKTDMA_0";
1367 static const char CPT_MasterName_SRIO_PKTDMA_Grp1[] =
"SRIO_PKTDMA_1";
1368 static const char CPT_MasterName_DAP[] =
"DAP";
1369 static const char CPT_MasterName_TPCC0[] =
"TPCC0";
1370 static const char CPT_MasterName_TPCC1[] =
"TPCC1";
1371 static const char CPT_MasterName_TPCC2[] =
"TPCC2";
1372 static const char CPT_MasterName_MSMC[] =
"MSMC";
1373 static const char CPT_MasterName_PCIe[] =
"PCIE";
1374 static const char CPT_MasterName_SRIO_M[] =
"SRIO_M";
1375 static const char CPT_MasterName_HyperBridge[] =
"HYPERBRIDGE";
1376 static const char CPT_MasterName_QM_SS_Grp0[] =
"QM_SS_0";
1377 static const char CPT_MasterName_QM_SS_Grp1[] =
"QM_SS_1";
1378 static const char CPT_MasterName_QM_SS_Grp2[] =
"QM_SS_2";
1379 static const char CPT_MasterName_QM_SS_Grp3[] =
"QM_SS_3";
1380 static const char CPT_MasterName_AIF_Grp0[] =
"AIF_0";
1381 static const char CPT_MasterName_AIF_Grp1[] =
"AIF_1";
1382 static const char CPT_MasterName_AIF_Grp2[] =
"AIF_2";
1383 static const char CPT_MasterName_AIF_Grp3[] =
"AIF_3";
1384 static const char CPT_MasterName_AIF_Grp4[] =
"AIF_4";
1385 static const char CPT_MasterName_AIF_Grp5[] =
"AIF_5";
1386 static const char CPT_MasterName_AIF_Grp6[] =
"AIF_6";
1387 static const char CPT_MasterName_AIF_Grp7[] =
"AIF_7";
1388 static const char CPT_MasterName_QM_CDMA_Grp0[] =
"QM_CDMA_0";
1389 static const char CPT_MasterName_QM_CDMA_Grp1[] =
"QM_CDMA_1";
1390 static const char CPT_MasterName_QM_CDMA_Grp2[] =
"QM_CDMA_2";
1391 static const char CPT_MasterName_QM_CDMA_Grp3[] =
"QM_CDMA_3";
1392 static const char CPT_MasterName_NETCP_Grp0[] =
"NETCP_0";
1393 static const char CPT_MasterName_NETCP_Grp1[] =
"NETCP_1";
1394 static const char CPT_MasterName_TAC[] =
"TAC";
1396 static const char CPT_MasterName_BCP_DIO1[] =
"BCP_DIO1";
1397 static const char CPT_MasterName_BCP_CDMA[] =
"BCP_CDMA";
1398 static const char CPT_MasterName_BCP_DIO0[] =
"BCP_DIO0";
1400 static const char CPT_MasterName_ARM_128_Grp0[] =
"ARM_128_0";
1403 const char * CPT_TCI6614_MasterNames[] = {
1404 CPT_MasterName_GEM0,
1405 CPT_MasterName_GEM1,
1406 CPT_MasterName_GEM2,
1407 CPT_MasterName_GEM3,
1408 CPT_MasterName_ARM_64,
1409 CPT_MasterName_GEM0_CFG,
1410 CPT_MasterName_GEM1_CFG,
1411 CPT_MasterName_GEM2_CFG,
1412 CPT_MasterName_GEM3_CFG,
1413 CPT_MasterName_EDMA0_TC0_RD,
1414 CPT_MasterName_EDMA0_TC0_WR,
1415 CPT_MasterName_EDMA0_TC1_RD,
1416 CPT_MasterName_EDMA0_TC1_WR,
1417 CPT_MasterName_EDMA1_TC0_RD,
1418 CPT_MasterName_EDMA1_TC0_WR,
1419 CPT_MasterName_EDMA1_TC1_RD,
1420 CPT_MasterName_EDMA1_TC1_WR,
1421 CPT_MasterName_EDMA1_TC2_RD,
1422 CPT_MasterName_EDMA1_TC2_WR,
1423 CPT_MasterName_EDMA1_TC3_RD,
1424 CPT_MasterName_EDMA1_TC3_WR,
1425 CPT_MasterName_EDMA2_TC0_RD,
1426 CPT_MasterName_EDMA2_TC0_WR,
1427 CPT_MasterName_EDMA2_TC1_RD,
1428 CPT_MasterName_EDMA2_TC1_WR,
1429 CPT_MasterName_EDMA2_TC2_RD,
1430 CPT_MasterName_EDMA2_TC2_WR,
1431 CPT_MasterName_EDMA2_TC3_RD,
1432 CPT_MasterName_EDMA2_TC3_WR,
1433 CPT_MasterName_SRIO_PKTDMA_Grp0,
1434 CPT_MasterName_SRIO_PKTDMA_Grp1,
1436 CPT_MasterName_TPCC0,
1437 CPT_MasterName_TPCC1,
1438 CPT_MasterName_TPCC2,
1439 CPT_MasterName_MSMC,
1440 CPT_MasterName_PCIe,
1441 CPT_MasterName_SRIO_M,
1442 CPT_MasterName_HyperBridge,
1443 CPT_MasterName_QM_SS_Grp0,
1444 CPT_MasterName_QM_SS_Grp1,
1445 CPT_MasterName_QM_SS_Grp2,
1446 CPT_MasterName_QM_SS_Grp3,
1447 CPT_MasterName_AIF_Grp0,
1448 CPT_MasterName_AIF_Grp1,
1449 CPT_MasterName_AIF_Grp2,
1450 CPT_MasterName_AIF_Grp3,
1451 CPT_MasterName_AIF_Grp4,
1452 CPT_MasterName_AIF_Grp5,
1453 CPT_MasterName_AIF_Grp6,
1454 CPT_MasterName_AIF_Grp7,
1455 CPT_MasterName_QM_CDMA_Grp0,
1456 CPT_MasterName_QM_CDMA_Grp1,
1457 CPT_MasterName_QM_CDMA_Grp2,
1458 CPT_MasterName_QM_CDMA_Grp3,
1459 CPT_MasterName_NETCP_Grp0,
1460 CPT_MasterName_NETCP_Grp1,
1462 CPT_MasterName_BCP_DIO1,
1463 CPT_MasterName_BCP_CDMA,
1464 CPT_MasterName_BCP_DIO0,
1465 CPT_MasterName_ARM_128_Grp0
1468 const char * CPT_TCI6612_MasterNames[] = {
1469 CPT_MasterName_GEM0,
1470 CPT_MasterName_GEM1,
1471 CPT_MasterName_ARM_64,
1472 CPT_MasterName_GEM0_CFG,
1473 CPT_MasterName_GEM1_CFG,
1474 CPT_MasterName_EDMA0_TC0_RD,
1475 CPT_MasterName_EDMA0_TC0_WR,
1476 CPT_MasterName_EDMA0_TC1_RD,
1477 CPT_MasterName_EDMA0_TC1_WR,
1478 CPT_MasterName_EDMA1_TC0_RD,
1479 CPT_MasterName_EDMA1_TC0_WR,
1480 CPT_MasterName_EDMA1_TC1_RD,
1481 CPT_MasterName_EDMA1_TC1_WR,
1482 CPT_MasterName_EDMA1_TC2_RD,
1483 CPT_MasterName_EDMA1_TC2_WR,
1484 CPT_MasterName_EDMA1_TC3_RD,
1485 CPT_MasterName_EDMA1_TC3_WR,
1486 CPT_MasterName_EDMA2_TC0_RD,
1487 CPT_MasterName_EDMA2_TC0_WR,
1488 CPT_MasterName_EDMA2_TC1_RD,
1489 CPT_MasterName_EDMA2_TC1_WR,
1490 CPT_MasterName_EDMA2_TC2_RD,
1491 CPT_MasterName_EDMA2_TC2_WR,
1492 CPT_MasterName_EDMA2_TC3_RD,
1493 CPT_MasterName_EDMA2_TC3_WR,
1494 CPT_MasterName_SRIO_PKTDMA_Grp0,
1495 CPT_MasterName_SRIO_PKTDMA_Grp1,
1497 CPT_MasterName_TPCC0,
1498 CPT_MasterName_TPCC1,
1499 CPT_MasterName_TPCC2,
1500 CPT_MasterName_MSMC,
1501 CPT_MasterName_PCIe,
1502 CPT_MasterName_SRIO_M,
1503 CPT_MasterName_HyperBridge,
1504 CPT_MasterName_QM_SS_Grp0,
1505 CPT_MasterName_QM_SS_Grp1,
1506 CPT_MasterName_QM_SS_Grp2,
1507 CPT_MasterName_QM_SS_Grp3,
1508 CPT_MasterName_AIF_Grp0,
1509 CPT_MasterName_AIF_Grp1,
1510 CPT_MasterName_AIF_Grp2,
1511 CPT_MasterName_AIF_Grp3,
1512 CPT_MasterName_AIF_Grp4,
1513 CPT_MasterName_AIF_Grp5,
1514 CPT_MasterName_AIF_Grp6,
1515 CPT_MasterName_AIF_Grp7,
1516 CPT_MasterName_QM_CDMA_Grp0,
1517 CPT_MasterName_QM_CDMA_Grp1,
1518 CPT_MasterName_QM_CDMA_Grp2,
1519 CPT_MasterName_QM_CDMA_Grp3,
1520 CPT_MasterName_NETCP_Grp0,
1521 CPT_MasterName_NETCP_Grp1,
1523 CPT_MasterName_BCP_DIO1,
1524 CPT_MasterName_BCP_CDMA,
1525 CPT_MasterName_BCP_DIO0,
1526 CPT_MasterName_ARM_128_Grp0,
1529 struct _CPT_MasterIdTable {
1536 struct _CPT_MasterIdTable CPT_TCI6614_MasterIDTable[] = {
1537 {eCPT_TCI6614_MID_GEM0, 0},
1538 {eCPT_TCI6614_MID_GEM1, 0},
1539 {eCPT_TCI6614_MID_GEM2, 0},
1540 {eCPT_TCI6614_MID_GEM3, 0},
1541 {eCPT_TCI6614_MID_ARM_64, 0},
1542 {eCPT_TCI6614_MID_GEM0_CFG, 0},
1543 {eCPT_TCI6614_MID_GEM1_CFG, 0},
1544 {eCPT_TCI6614_MID_GEM2_CFG, 0},
1545 {eCPT_TCI6614_MID_GEM3_CFG, 0},
1546 {eCPT_TCI6614_MID_EDMA0_TC0_RD, 0},
1547 {eCPT_TCI6614_MID_EDMA0_TC0_WR, 0},
1548 {eCPT_TCI6614_MID_EDMA0_TC1_RD, 0},
1549 {eCPT_TCI6614_MID_EDMA0_TC1_WR, 0},
1550 {eCPT_TCI6614_MID_EDMA1_TC0_RD, 0},
1551 {eCPT_TCI6614_MID_EDMA1_TC0_WR, 0},
1552 {eCPT_TCI6614_MID_EDMA1_TC1_RD, 0},
1553 {eCPT_TCI6614_MID_EDMA1_TC1_WR, 0},
1554 {eCPT_TCI6614_MID_EDMA1_TC2_RD, 0},
1555 {eCPT_TCI6614_MID_EDMA1_TC2_WR, 0},
1556 {eCPT_TCI6614_MID_EDMA1_TC3_RD, 0},
1557 {eCPT_TCI6614_MID_EDMA1_TC3_WR, 0},
1558 {eCPT_TCI6614_MID_EDMA2_TC0_RD, 0},
1559 {eCPT_TCI6614_MID_EDMA2_TC0_WR, 0},
1560 {eCPT_TCI6614_MID_EDMA2_TC1_RD, 0},
1561 {eCPT_TCI6614_MID_EDMA2_TC1_WR, 0},
1562 {eCPT_TCI6614_MID_EDMA2_TC2_RD, 0},
1563 {eCPT_TCI6614_MID_EDMA2_TC2_WR, 0},
1564 {eCPT_TCI6614_MID_EDMA2_TC3_RD, 0},
1565 {eCPT_TCI6614_MID_EDMA2_TC3_WR, 0},
1566 {eCPT_TCI6614_MID_SRIO_PKTDMA_Grp0, 2},
1567 {eCPT_TCI6614_MID_SRIO_PKTDMA_Grp1, 0},
1568 {eCPT_TCI6614_MID_DAP, 0},
1569 {eCPT_TCI6614_MID_TPCC0, 0},
1570 {eCPT_TCI6614_MID_TPCC1, 0},
1571 {eCPT_TCI6614_MID_TPCC2, 0},
1572 {eCPT_TCI6614_MID_MSMC, 0},
1573 {eCPT_TCI6614_MID_PCIe, 0},
1574 {eCPT_TCI6614_MID_SRIO_M, 0},
1575 {eCPT_TCI6614_MID_HyperBridge, 0},
1576 {eCPT_TCI6614_MID_QM_SS_Grp0, 0},
1577 {eCPT_TCI6614_MID_QM_SS_Grp1, 0},
1578 {eCPT_TCI6614_MID_QM_SS_Grp2, 0},
1579 {eCPT_TCI6614_MID_QM_SS_Grp3, 0},
1580 {eCPT_TCI6614_MID_AIF_Grp0, 8},
1581 {eCPT_TCI6614_MID_AIF_Grp1, 0},
1582 {eCPT_TCI6614_MID_AIF_Grp2, 0},
1583 {eCPT_TCI6614_MID_AIF_Grp3, 0},
1584 {eCPT_TCI6614_MID_AIF_Grp4, 0},
1585 {eCPT_TCI6614_MID_AIF_Grp5, 0},
1586 {eCPT_TCI6614_MID_AIF_Grp6, 0},
1587 {eCPT_TCI6614_MID_AIF_Grp7, 0},
1588 {eCPT_TCI6614_MID_QM_CDMA_Grp0, 4},
1589 {eCPT_TCI6614_MID_QM_CDMA_Grp1, 0},
1590 {eCPT_TCI6614_MID_QM_CDMA_Grp2, 0},
1591 {eCPT_TCI6614_MID_QM_CDMA_Grp3, 0},
1592 {eCPT_TCI6614_MID_NETCP_Grp0, 2},
1593 {eCPT_TCI6614_MID_NETCP_Grp1, 0},
1594 {eCPT_TCI6614_MID_TAC, 0},
1595 {eCPT_TCI6614_MID_BCP_DIO1, 0},
1596 {eCPT_TCI6614_MID_BCP_CDMA, 0},
1597 {eCPT_TCI6614_MID_BCP_DIO0, 0},
1598 {eCPT_TCI6614_MID_ARM_128_Grp0, 32}
1602 struct _CPT_MasterIdTable CPT_TCI6612_MasterIDTable[] = {
1603 {eCPT_TCI6612_MID_GEM0, 0},
1604 {eCPT_TCI6612_MID_GEM1, 0},
1605 {eCPT_TCI6612_MID_ARM_64, 0},
1606 {eCPT_TCI6612_MID_GEM0_CFG, 0},
1607 {eCPT_TCI6612_MID_GEM1_CFG, 0},
1608 {eCPT_TCI6612_MID_EDMA0_TC0_RD, 0},
1609 {eCPT_TCI6612_MID_EDMA0_TC0_WR, 0},
1610 {eCPT_TCI6612_MID_EDMA0_TC1_RD, 0},
1611 {eCPT_TCI6612_MID_EDMA0_TC1_WR, 0},
1612 {eCPT_TCI6612_MID_EDMA1_TC0_RD, 0},
1613 {eCPT_TCI6612_MID_EDMA1_TC0_WR, 0},
1614 {eCPT_TCI6612_MID_EDMA1_TC1_RD, 0},
1615 {eCPT_TCI6612_MID_EDMA1_TC1_WR, 0},
1616 {eCPT_TCI6612_MID_EDMA1_TC2_RD, 0},
1617 {eCPT_TCI6612_MID_EDMA1_TC2_WR, 0},
1618 {eCPT_TCI6612_MID_EDMA1_TC3_RD, 0},
1619 {eCPT_TCI6612_MID_EDMA1_TC3_WR, 0},
1620 {eCPT_TCI6612_MID_EDMA2_TC0_RD, 0},
1621 {eCPT_TCI6612_MID_EDMA2_TC0_WR, 0},
1622 {eCPT_TCI6612_MID_EDMA2_TC1_RD, 0},
1623 {eCPT_TCI6612_MID_EDMA2_TC1_WR, 0},
1624 {eCPT_TCI6612_MID_EDMA2_TC2_RD, 0},
1625 {eCPT_TCI6612_MID_EDMA2_TC2_WR, 0},
1626 {eCPT_TCI6612_MID_EDMA2_TC3_RD, 0},
1627 {eCPT_TCI6612_MID_EDMA2_TC3_WR, 0},
1628 {eCPT_TCI6612_MID_SRIO_PKTDMA_Grp0, 2},
1629 {eCPT_TCI6612_MID_SRIO_PKTDMA_Grp1, 0},
1630 {eCPT_TCI6612_MID_DAP, 0},
1631 {eCPT_TCI6612_MID_TPCC0, 0},
1632 {eCPT_TCI6612_MID_TPCC1, 0},
1633 {eCPT_TCI6612_MID_TPCC2, 0},
1634 {eCPT_TCI6612_MID_MSMC, 0},
1635 {eCPT_TCI6612_MID_PCIe, 0},
1636 {eCPT_TCI6612_MID_SRIO_M, 0},
1637 {eCPT_TCI6612_MID_HyperBridge, 0},
1638 {eCPT_TCI6612_MID_QM_SS_Grp0, 0},
1639 {eCPT_TCI6612_MID_QM_SS_Grp1, 0},
1640 {eCPT_TCI6612_MID_QM_SS_Grp2, 0},
1641 {eCPT_TCI6612_MID_QM_SS_Grp3, 0},
1642 {eCPT_TCI6612_MID_AIF_Grp0, 8},
1643 {eCPT_TCI6612_MID_AIF_Grp1, 0},
1644 {eCPT_TCI6612_MID_AIF_Grp2, 0},
1645 {eCPT_TCI6612_MID_AIF_Grp3, 0},
1646 {eCPT_TCI6612_MID_AIF_Grp4, 0},
1647 {eCPT_TCI6612_MID_AIF_Grp5, 0},
1648 {eCPT_TCI6612_MID_AIF_Grp6, 0},
1649 {eCPT_TCI6612_MID_AIF_Grp7, 0},
1650 {eCPT_TCI6612_MID_QM_CDMA_Grp1, 0},
1651 {eCPT_TCI6612_MID_QM_CDMA_Grp3, 0},
1652 {eCPT_TCI6612_MID_NETCP_Grp0, 2},
1653 {eCPT_TCI6612_MID_NETCP_Grp1, 0},
1654 {eCPT_TCI6612_MID_TAC, 0},
1655 {eCPT_TCI6612_MID_BCP_DIO1, 0},
1656 {eCPT_TCI6612_MID_BCP_CDMA, 0},
1657 {eCPT_TCI6612_MID_BCP_DIO0, 0},
1658 {eCPT_TCI6612_MID_ARM_128_Grp0, 32}
1663 struct _CPT_MasterIdTable {
1670 struct _CPT_MasterIdTable CPT_TCI6614_MasterIDTable[] = {
1671 {CPT_MasterName_GEM0, eCPT_TCI6614_MID_GEM0, 0},
1672 {CPT_MasterName_GEM1, eCPT_TCI6614_MID_GEM1, 0},
1673 {CPT_MasterName_GEM2, eCPT_TCI6614_MID_GEM2, 0},
1674 {CPT_MasterName_GEM3, eCPT_TCI6614_MID_GEM3, 0},
1675 {CPT_MasterName_ARM_64, eCPT_TCI6614_MID_ARM_64, 0},
1676 {CPT_MasterName_GEM0_CFG, eCPT_TCI6614_MID_GEM0_CFG, 0},
1677 {CPT_MasterName_GEM1_CFG, eCPT_TCI6614_MID_GEM1_CFG, 0},
1678 {CPT_MasterName_GEM2_CFG, eCPT_TCI6614_MID_GEM2_CFG, 0},
1679 {CPT_MasterName_GEM3_CFG, eCPT_TCI6614_MID_GEM3_CFG, 0},
1680 {CPT_MasterName_EDMA0_TC0_RD, eCPT_TCI6614_MID_EDMA0_TC0_RD, 0},
1681 {CPT_MasterName_EDMA0_TC0_WR, eCPT_TCI6614_MID_EDMA0_TC0_WR, 0},
1682 {CPT_MasterName_EDMA0_TC1_RD, eCPT_TCI6614_MID_EDMA0_TC1_RD, 0},
1683 {CPT_MasterName_EDMA0_TC1_WR, eCPT_TCI6614_MID_EDMA0_TC1_WR, 0},
1684 {CPT_MasterName_EDMA1_TC0_RD, eCPT_TCI6614_MID_EDMA1_TC0_RD, 0},
1685 {CPT_MasterName_EDMA1_TC0_WR, eCPT_TCI6614_MID_EDMA1_TC0_WR, 0},
1686 {CPT_MasterName_EDMA1_TC1_RD, eCPT_TCI6614_MID_EDMA1_TC1_RD, 0},
1687 {CPT_MasterName_EDMA1_TC1_WR, eCPT_TCI6614_MID_EDMA1_TC1_WR, 0},
1688 {CPT_MasterName_EDMA1_TC2_RD, eCPT_TCI6614_MID_EDMA1_TC2_RD, 0},
1689 {CPT_MasterName_EDMA1_TC2_WR, eCPT_TCI6614_MID_EDMA1_TC2_WR, 0},
1690 {CPT_MasterName_EDMA1_TC3_RD, eCPT_TCI6614_MID_EDMA1_TC3_RD, 0},
1691 {CPT_MasterName_EDMA1_TC3_WR, eCPT_TCI6614_MID_EDMA1_TC3_WR, 0},
1692 {CPT_MasterName_EDMA2_TC0_RD, eCPT_TCI6614_MID_EDMA2_TC0_RD, 0},
1693 {CPT_MasterName_EDMA2_TC0_WR, eCPT_TCI6614_MID_EDMA2_TC0_WR, 0},
1694 {CPT_MasterName_EDMA2_TC1_RD, eCPT_TCI6614_MID_EDMA2_TC1_RD, 0},
1695 {CPT_MasterName_EDMA2_TC1_WR, eCPT_TCI6614_MID_EDMA2_TC1_WR, 0},
1696 {CPT_MasterName_EDMA2_TC2_RD, eCPT_TCI6614_MID_EDMA2_TC2_RD, 0},
1697 {CPT_MasterName_EDMA2_TC2_WR, eCPT_TCI6614_MID_EDMA2_TC2_WR, 0},
1698 {CPT_MasterName_EDMA2_TC3_RD, eCPT_TCI6614_MID_EDMA2_TC3_RD, 0},
1699 {CPT_MasterName_EDMA2_TC3_WR, eCPT_TCI6614_MID_EDMA2_TC3_WR, 0},
1700 {CPT_MasterName_SRIO_PKTDMA_Grp0, eCPT_TCI6614_MID_SRIO_PKTDMA_Grp0, 2},
1701 {CPT_MasterName_SRIO_PKTDMA_Grp1, eCPT_TCI6614_MID_SRIO_PKTDMA_Grp1, 0},
1702 {CPT_MasterName_DAP, eCPT_TCI6614_MID_DAP, 0},
1703 {CPT_MasterName_TPCC0, eCPT_TCI6614_MID_TPCC0, 0},
1704 {CPT_MasterName_TPCC1, eCPT_TCI6614_MID_TPCC1, 0},
1705 {CPT_MasterName_TPCC2, eCPT_TCI6614_MID_TPCC2, 0},
1706 {CPT_MasterName_MSMC, eCPT_TCI6614_MID_MSMC, 0},
1707 {CPT_MasterName_PCIe, eCPT_TCI6614_MID_PCIe, 0},
1708 {CPT_MasterName_SRIO_M, eCPT_TCI6614_MID_SRIO_M, 0},
1709 {CPT_MasterName_HyperBridge, eCPT_TCI6614_MID_HyperBridge, 0},
1710 {CPT_MasterName_QM_SS_Grp0, eCPT_TCI6614_MID_QM_SS_Grp0, 0},
1711 {CPT_MasterName_QM_SS_Grp1, eCPT_TCI6614_MID_QM_SS_Grp1, 0},
1712 {CPT_MasterName_QM_SS_Grp2, eCPT_TCI6614_MID_QM_SS_Grp2, 0},
1713 {CPT_MasterName_QM_SS_Grp3, eCPT_TCI6614_MID_QM_SS_Grp3, 0},
1714 {CPT_MasterName_AIF_Grp0, eCPT_TCI6614_MID_AIF_Grp0, 8},
1715 {CPT_MasterName_AIF_Grp1, eCPT_TCI6614_MID_AIF_Grp1, 0},
1716 {CPT_MasterName_AIF_Grp2, eCPT_TCI6614_MID_AIF_Grp2, 0},
1717 {CPT_MasterName_AIF_Grp3, eCPT_TCI6614_MID_AIF_Grp3, 0},
1718 {CPT_MasterName_AIF_Grp4, eCPT_TCI6614_MID_AIF_Grp4, 0},
1719 {CPT_MasterName_AIF_Grp5, eCPT_TCI6614_MID_AIF_Grp5, 0},
1720 {CPT_MasterName_AIF_Grp6, eCPT_TCI6614_MID_AIF_Grp6, 0},
1721 {CPT_MasterName_AIF_Grp7, eCPT_TCI6614_MID_AIF_Grp7, 0},
1722 {CPT_MasterName_QM_CDMA_Grp0, eCPT_TCI6614_MID_QM_CDMA_Grp0, 4},
1723 {CPT_MasterName_QM_CDMA_Grp1, eCPT_TCI6614_MID_QM_CDMA_Grp1, 0},
1724 {CPT_MasterName_QM_CDMA_Grp2, eCPT_TCI6614_MID_QM_CDMA_Grp2, 0},
1725 {CPT_MasterName_QM_CDMA_Grp3, eCPT_TCI6614_MID_QM_CDMA_Grp3, 0},
1726 {CPT_MasterName_NETCP_Grp0, eCPT_TCI6614_MID_NETCP_Grp0, 2},
1727 {CPT_MasterName_NETCP_Grp1, eCPT_TCI6614_MID_NETCP_Grp1, 0},
1728 {CPT_MasterName_TAC, eCPT_TCI6614_MID_TAC, 0},
1729 {CPT_MasterName_BCP_DIO1, eCPT_TCI6614_MID_BCP_DIO1, 0},
1730 {CPT_MasterName_BCP_CDMA, eCPT_TCI6614_MID_BCP_CDMA, 0},
1731 {CPT_MasterName_BCP_DIO0, eCPT_TCI6614_MID_BCP_DIO0, 0},
1732 {CPT_MasterName_ARM_128_Grp0, eCPT_TCI6614_MID_ARM_128_Grp0, 32}
1736 struct _CPT_MasterIdTable CPT_TCI6612_MasterIDTable[] = {
1737 {CPT_MasterName_GEM0, eCPT_TCI6612_MID_GEM0, 0},
1738 {CPT_MasterName_GEM1, eCPT_TCI6612_MID_GEM1, 0},
1739 {CPT_MasterName_ARM_64, eCPT_TCI6612_MID_ARM_64, 0},
1740 {CPT_MasterName_GEM0_CFG, eCPT_TCI6612_MID_GEM0_CFG, 0},
1741 {CPT_MasterName_GEM1_CFG, eCPT_TCI6612_MID_GEM1_CFG, 0},
1742 {CPT_MasterName_EDMA0_TC0_RD, eCPT_TCI6612_MID_EDMA0_TC0_RD, 0},
1743 {CPT_MasterName_EDMA0_TC0_WR, eCPT_TCI6612_MID_EDMA0_TC0_WR, 0},
1744 {CPT_MasterName_EDMA0_TC1_RD, eCPT_TCI6612_MID_EDMA0_TC1_RD, 0},
1745 {CPT_MasterName_EDMA0_TC1_WR, eCPT_TCI6612_MID_EDMA0_TC1_WR, 0},
1746 {CPT_MasterName_EDMA1_TC0_RD, eCPT_TCI6612_MID_EDMA1_TC0_RD, 0},
1747 {CPT_MasterName_EDMA1_TC0_WR, eCPT_TCI6612_MID_EDMA1_TC0_WR, 0},
1748 {CPT_MasterName_EDMA1_TC1_RD, eCPT_TCI6612_MID_EDMA1_TC1_RD, 0},
1749 {CPT_MasterName_EDMA1_TC1_WR, eCPT_TCI6612_MID_EDMA1_TC1_WR, 0},
1750 {CPT_MasterName_EDMA1_TC2_RD, eCPT_TCI6612_MID_EDMA1_TC2_RD, 0},
1751 {CPT_MasterName_EDMA1_TC2_WR, eCPT_TCI6612_MID_EDMA1_TC2_WR, 0},
1752 {CPT_MasterName_EDMA1_TC3_RD, eCPT_TCI6612_MID_EDMA1_TC3_RD, 0},
1753 {CPT_MasterName_EDMA1_TC3_WR, eCPT_TCI6612_MID_EDMA1_TC3_WR, 0},
1754 {CPT_MasterName_EDMA2_TC0_RD, eCPT_TCI6612_MID_EDMA2_TC0_RD, 0},
1755 {CPT_MasterName_EDMA2_TC0_WR, eCPT_TCI6612_MID_EDMA2_TC0_WR, 0},
1756 {CPT_MasterName_EDMA2_TC1_RD, eCPT_TCI6612_MID_EDMA2_TC1_RD, 0},
1757 {CPT_MasterName_EDMA2_TC1_WR, eCPT_TCI6612_MID_EDMA2_TC1_WR, 0},
1758 {CPT_MasterName_EDMA2_TC2_RD, eCPT_TCI6612_MID_EDMA2_TC2_RD, 0},
1759 {CPT_MasterName_EDMA2_TC2_WR, eCPT_TCI6612_MID_EDMA2_TC2_WR, 0},
1760 {CPT_MasterName_EDMA2_TC3_RD, eCPT_TCI6612_MID_EDMA2_TC3_RD, 0},
1761 {CPT_MasterName_EDMA2_TC3_WR, eCPT_TCI6612_MID_EDMA2_TC3_WR, 0},
1762 {CPT_MasterName_SRIO_PKTDMA_Grp0, eCPT_TCI6612_MID_SRIO_PKTDMA_Grp0, 2},
1763 {CPT_MasterName_SRIO_PKTDMA_Grp1, eCPT_TCI6612_MID_SRIO_PKTDMA_Grp1, 0},
1764 {CPT_MasterName_DAP, eCPT_TCI6612_MID_DAP, 0},
1765 {CPT_MasterName_TPCC0, eCPT_TCI6612_MID_TPCC0, 0},
1766 {CPT_MasterName_TPCC1, eCPT_TCI6612_MID_TPCC1, 0},
1767 {CPT_MasterName_TPCC2, eCPT_TCI6612_MID_TPCC2, 0},
1768 {CPT_MasterName_MSMC, eCPT_TCI6612_MID_MSMC, 0},
1769 {CPT_MasterName_PCIe, eCPT_TCI6612_MID_PCIe, 0},
1770 {CPT_MasterName_SRIO_M, eCPT_TCI6612_MID_SRIO_M, 0},
1771 {CPT_MasterName_HyperBridge, eCPT_TCI6612_MID_HyperBridge, 0},
1772 {CPT_MasterName_QM_SS_Grp0, eCPT_TCI6612_MID_QM_SS_Grp0, 0},
1773 {CPT_MasterName_QM_SS_Grp1, eCPT_TCI6612_MID_QM_SS_Grp1, 0},
1774 {CPT_MasterName_QM_SS_Grp2, eCPT_TCI6612_MID_QM_SS_Grp2, 0},
1775 {CPT_MasterName_QM_SS_Grp3, eCPT_TCI6612_MID_QM_SS_Grp3, 0},
1776 {CPT_MasterName_AIF_Grp0, eCPT_TCI6612_MID_AIF_Grp0, 8},
1777 {CPT_MasterName_AIF_Grp1, eCPT_TCI6612_MID_AIF_Grp1, 0},
1778 {CPT_MasterName_AIF_Grp2, eCPT_TCI6612_MID_AIF_Grp2, 0},
1779 {CPT_MasterName_AIF_Grp3, eCPT_TCI6612_MID_AIF_Grp3, 0},
1780 {CPT_MasterName_AIF_Grp4, eCPT_TCI6612_MID_AIF_Grp4, 0},
1781 {CPT_MasterName_AIF_Grp5, eCPT_TCI6612_MID_AIF_Grp5, 0},
1782 {CPT_MasterName_AIF_Grp6, eCPT_TCI6612_MID_AIF_Grp6, 0},
1783 {CPT_MasterName_AIF_Grp7, eCPT_TCI6612_MID_AIF_Grp7, 0},
1784 {CPT_MasterName_QM_CDMA_Grp0, eCPT_TCI6612_MID_QM_CDMA_Grp0, 4},
1785 {CPT_MasterName_QM_CDMA_Grp1, eCPT_TCI6612_MID_QM_CDMA_Grp1, 0},
1786 {CPT_MasterName_QM_CDMA_Grp2, eCPT_TCI6612_MID_QM_CDMA_Grp2, 0},
1787 {CPT_MasterName_QM_CDMA_Grp3, eCPT_TCI6612_MID_QM_CDMA_Grp3, 0},
1788 {CPT_MasterName_NETCP_Grp0, eCPT_TCI6612_MID_NETCP_Grp0, 2},
1789 {CPT_MasterName_NETCP_Grp1, eCPT_TCI6612_MID_NETCP_Grp1, 0},
1790 {CPT_MasterName_TAC, eCPT_TCI6612_MID_TAC, 0},
1791 {CPT_MasterName_BCP_DIO1, eCPT_TCI6612_MID_BCP_DIO1, 0},
1792 {CPT_MasterName_BCP_CDMA, eCPT_TCI6612_MID_BCP_CDMA, 0},
1793 {CPT_MasterName_BCP_DIO0, eCPT_TCI6612_MID_BCP_DIO0, 0},
1794 {CPT_MasterName_ARM_128_Grp0, eCPT_TCI6612_MID_ARM_128_Grp0, 32}
1803 #ifdef RUNTIME_DEVICE_SELECT
1804 #define reg_rd32(addr) cTools_reg_rd32((uint32_t)addr)
1805 #define reg_wr32(addr, value) cTools_reg_wr32((uint32_t)addr, value)
1807 #define reg_rd32(addr) (*addr)
1808 #define reg_wr32(addr,value) (*addr = value)
1815 const uint32_t STM_BaseAddress = 0x20000000;
1816 const uint32_t STM_ChResolution = 0x1000;
1817 const uint32_t STM_Ch0MsgEnd = 0x20000800;
1820 #define PSC_BASE 0x02350000
1822 #define CPT_POWER_DOMAIN 1
1823 #define CPT_POWER_TRANSITION (1 << CPT_POWER_DOMAIN)
1824 #define CPT_LPCS_NUM 5
1825 #define CPT_TIMEOUT_CNT 0xFFFF
1826 #define CPT_PDSTAT_ON 0x1
1827 #define CPT_PDSTAT_POR_VALID 0x300
1828 #define CPT_MDSTAT_ENABLED 0x3
1831 #define PSC_PTCMD ((volatile uint32_t *) (PSC_BASE+ 0x120))
1832 #define PSC_PTSTAT ((volatile uint32_t *) (PSC_BASE+ 0x128))
1834 #define PSC_PDSTAT(n) ((volatile uint32_t *) (PSC_BASE+0x200+4*n))
1835 #define PSC_PDCTL(n) ((volatile uint32_t *) (PSC_BASE+0x300+4*n))
1836 #define PSC_PDCFG(n) ((volatile uint32_t *) (PSC_BASE+0x400+4*n))
1838 #define PSC_MDCFG(n) ((volatile uint32_t *) (PSC_BASE+0x600+4*n))
1839 #define PSC_MDSTAT(n) ((volatile uint32_t *) (PSC_BASE+0x800+4*n))
1840 #define PSC_MDCTL(n) ((volatile uint32_t *) (PSC_BASE+0xA00+4*n))
1843 #define CPT_REGOFF_Identification 0x00
1844 #define CPT_REGOFF_TransactionQualifier 0x04
1845 #define CPT_REGOFF_ModuleControlAndStatus 0x08
1846 #define CPT_REGOFF_SlidingTimeWindow 0x0C
1847 #define CPT_REGOFF_BusMasterSelect_TP0_A 0x10
1848 #define CPT_REGOFF_BusMasterSelect_TP0_B 0x14
1849 #define CPT_REGOFF_BusMasterSelect_TP0_C 0x18
1850 #define CPT_REGOFF_BusMasterSelect_TP0_D 0x1C
1851 #define CPT_REGOFF_BusMasterSelect_TP1_A 0x20
1852 #define CPT_REGOFF_BusMasterSelect_TP1_B 0x24
1853 #define CPT_REGOFF_BusMasterSelect_TP1_C 0x28
1854 #define CPT_REGOFF_BusMasterSelect_TP1_D 0x2C
1855 #define CPT_REGOFF_EndAddress 0x30
1856 #define CPT_REGOFF_StartAddress 0x34
1857 #define CPT_REGOFF_AccessStatus 0x38
1858 #define CPT_REGOFF_AccessStatusPacing 0x3C
1859 #define CPT_REGOFF_AddressMask 0x40
1860 #define CPT_REGOFF_DestinationAddress 0x44
1861 #define CPT_REGOFF_MessagePriority 0x48
1862 #define CPT_REGOFF_Ownership 0x4c
1863 #define CPT_REGOFF_ThroughPut0 0x50
1864 #define CPT_REGOFF_ThroughPut1 0x54
1865 #define CPT_REGOFF_AccumulatedWaitTime 0x58
1866 #define CPT_REGOFF_NumberOfGrants 0x5c
1867 #define CPT_REGOFF_InterruptRawStatus 0x60
1868 #define CPT_REGOFF_InterruptMaskStatus 0x64
1869 #define CPT_REGOFF_InterruptMaskSet 0x68
1870 #define CPT_REGOFF_InterruptMaskClear 0x6C
1871 #define CPT_REGOFF_InterruptEOI 0x70
1873 #define CPT_REGSPACE_BYTES 128
1878 #define CPT_ID_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_Identification ))
1879 #define CPT_QUAL_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_TransactionQualifier ))
1880 #define CPT_MODCTL_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_ModuleControlAndStatus ))
1881 #define CPT_STWINDOW_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_SlidingTimeWindow))
1882 #define CPT_MSTSELA_TP0_REGIndex(ba, r) ((volatile uint32_t *)((uint32_t)(ba) + ((r) * 4) + CPT_REGOFF_BusMasterSelect_TP0_A))
1883 #define CPT_MSTSELA_TP0_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP0_A))
1884 #define CPT_MSTSELB_TP0_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP0_B))
1885 #define CPT_MSTSELC_TP0_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP0_C))
1886 #define CPT_MSTSELD_TP0_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP0_D))
1887 #define CPT_MSTSELA_TP1_REGIndex(ba, r) ((volatile uint32_t *)((uint32_t)(ba) + ((r) * 4) + CPT_REGOFF_BusMasterSelect_TP1_A))
1888 #define CPT_MSTSELA_TP1_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP1_A))
1889 #define CPT_MSTSELB_TP1_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP1_B))
1890 #define CPT_MSTSELC_TP1_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP1_C))
1891 #define CPT_MSTSELD_TP1_REG(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_BusMasterSelect_TP1_D))
1892 #define CPT_ENDADDR(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_EndAddress ))
1893 #define CPT_STARTADDR(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_StartAddress ))
1894 #define CPT_ACCSTATUS(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_AccessStatus ))
1895 #define CPT_PACING(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_AccessStatusPacing ))
1896 #define CPT_ADDRMASK(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_AddressMask ))
1897 #define CPT_DSTADDR(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_DestinationAddress ))
1898 #define CPT_MSGPRI(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_MessagePriority ))
1899 #define CPT_OWNERSHIP(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_Ownership ))
1900 #define CPT_TP0(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_ThroughPut0 ))
1901 #define CPT_TP1(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_ThroughPut1 ))
1902 #define CPT_ACCUMWAIT(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_AccumulatedWaitTime ))
1903 #define CPT_GRANTCNT(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_NumberOfGrants ))
1904 #define CPT_INTRAW(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_InterruptRawStatus ))
1905 #define CPT_INTSTATUS(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_InterruptMaskStatus ))
1906 #define CPT_INTSET(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_InterruptMaskSet ))
1907 #define CPT_INTCLR(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_InterruptMaskClear ))
1908 #define CPT_INTEOI(ba) ((volatile uint32_t *)((uint32_t)(ba) + CPT_REGOFF_InterruptEOI ))
1932 #define CPT_GET_IDREG_MINOR(reg) ( reg & 0x1F )
1933 #define CPT_GET_IDREG_CUSTOM(reg) ( ( reg & 0xC0 ) >> 6 )
1934 #define CPT_GET_IDREG_MAJOR(reg) ( ( reg & 0xE00 ) >> 8 )
1935 #define CPT_GET_IDREG_RTL(reg) ( ( reg & 0xF800 ) >> 11 )
1936 #define CPT_GET_IDREG_FUNC(reg) ( ( reg & 0x0FFF0000 ) >> 16 )
1937 #define CPT_GET_IDREG_IDSCH(reg) ( ( reg & 0x80000000 ) >> 31 )
2001 #define CPT_GET_QUAL_TRIGOUT(reg) ( ( reg & 0xC0000000 ) >> 26 )
2002 #define CPT_GET_QUAL_TRIGSTAT(reg) ( ( reg & 0x02000000 ) >> 25 )
2003 #define CPT_GET_QUAL_TRIGIN(reg) ( ( reg & 0x01000000 ) >> 24 )
2004 #define CPT_GET_QUAL_TRIGOUTDTYPE(reg) ( ( reg & 0x00F00000 ) >> 20 )
2005 #define CPT_GET_QUAL_TH1DTYPE(reg) ( ( reg & 0x000F0000 ) >> 16 )
2006 #define CPT_GET_QUAL_TH0DTYPE(reg) ( ( reg & 0x0000F000 ) >> 12 )
2007 #define CPT_GET_QUAL_EVTBDTYPE(reg) ( ( reg & 0x00000F00 ) >> 8 )
2008 #define CPT_GET_QUAL_TRIGOUTRW(reg) ( ( reg & 0x000000C0 ) >> 6 )
2009 #define CPT_GET_QUAL_TH1RW(reg) ( ( reg & 0x00000030 ) >> 4 )
2010 #define CPT_GET_QUAL_TH0RW(reg) ( ( reg & 0x0000000C ) >> 2 )
2011 #define CPT_GET_QUAL_EVTBRW(reg) ( reg & 0x3 )
2013 #define CPT_SET_QUAL_TRIGOUT(qual) ( ( qual & 0x3 ) << 26 )
2014 #define CPT_SET_QUAL_TRIGIN(qual) ( ( qual & 1 ) << 24 )
2015 #define CPT_SET_QUAL_TRIGOUTDTYPE(qual) ( ( qual & 0xF ) << 20 )
2016 #define CPT_SET_QUAL_TH1DTYPE(qual) ( ( qual & 0xF ) << 16 )
2017 #define CPT_SET_QUAL_TH0DTYPE(qual) ( ( qual & 0xF ) << 12 )
2018 #define CPT_SET_QUAL_EVTBDTYPE(qual) ( ( qual & 0xF ) << 8 )
2019 #define CPT_SET_QUAL_TRIGOUTRW(qual) ( ( qual & 0x3 ) << 6 )
2020 #define CPT_SET_QUAL_TH1RW(qual) ( ( qual & 0x3 ) << 4 )
2021 #define CPT_SET_QUAL_TH0RW(qual) ( ( qual & 0x3 ) << 2 )
2022 #define CPT_SET_QUAL_EVTBRW(qual) ( qual & 0x3 )
2024 #define CPT_QUAL_TRIGOUT_MASK ( 0x3 << 26 )
2025 #define CPT_QUAL_TRIGIN_MASK ( 0x1 << 24 )
2026 #define CPT_QUAL_TRIGOUTDTYPE_MASK ( 0xF << 20 )
2027 #define CPT_QUAL_TH1DTYPE_MASK ( 0xF << 16 )
2028 #define CPT_QUAL_TH0DTYPE_MASK ( 0xF << 12 )
2029 #define CPT_QUAL_EVTBDTYPE_MASK ( 0xF << 8 )
2030 #define CPT_QUAL_TRIGOUTRW_MASK ( 0x3 << 6 )
2031 #define CPT_QUAL_TH1RW_MASK ( 0x3 << 4 )
2032 #define CPT_QUAL_TH0RW_MASK ( 0x3 << 2 )
2033 #define CPT_QUAL_EVTBRW_MASK ( 0x3 )
2035 #define CPT_SET_QUAL_ALLDISABLED 0x000000FF
2036 #define CPT_TRIG_QUAL_MASK 0x0DF000C0
2037 #define CPT_TH1_QUAL_MASK 0x000F0030
2038 #define CPT_TH0_QUAL_MASK 0x0000F00C
2039 #define CPT_EVTB_QUAL_MASK 0x00000F03
2073 #define CPT_GET_MODCTL_UPPERADDRBITS(reg) ( ( reg & 0xFFFF0000 ) >> 16 )
2074 #define CPT_GET_MODCTL_ADDRFLTEN(reg) ( ( reg & 0x00008000 ) >> 15 )
2075 #define CPT_GET_MODCTL_WAITCNTEN(reg) ( ( reg & 0x00004000 ) >> 14 )
2076 #define CPT_GET_MODCTL_GRANTCNTEN(reg) ( ( reg & 0x00002000 ) >> 13 )
2077 #define CPT_GET_MODCTL_EXPSEL(reg) ( ( reg & 0x00001F00 ) >> 8 )
2078 #define CPT_GET_MODCTL_ADDRMODE(reg) ( ( reg & 0x000000E0 ) >> 5 )
2079 #define CPT_GET_MODCTL_SID(reg) ( reg & 0x1F )
2081 #define CPT_SET_MODCTL_UPPERADDRBITS(cntl) ( ( cntl & 0xFFFF ) << 16 )
2082 #define CPT_SET_MODCTL_ADDRFLTEN(cntl) ( ( cntl & 0x1 ) << 15 )
2083 #define CPT_SET_MODCTL_WAITCNTEN(cntl) ( ( cntl & 0x1 ) << 14 )
2084 #define CPT_SET_MODCTL_GRANTCNTEN(cntl) ( ( cntl & 0x1 ) << 13 )
2085 #define CPT_SET_MODCTL_EXPSEL(cntl) ( ( cntl & 0x1F ) << 8 )
2087 #define CPT_SET_MODCTL_CNTEN(cntl) ( ( cntl & 0x3 ) << 13 )
2089 #define CPT_MODCTL_UPPERADDRBITS_MASK ( 0xFFFF << 16)
2090 #define CPT_MODCTL_ADDRFLTEN_MASK ( 0x1 << 15 )
2091 #define CPT_MODCTL_WAITCNTEN_MASK ( 0x1 << 14 )
2092 #define CPT_MODCTL_GRANTCNTEN_MASK ( 0x1 << 13 )
2093 #define CPT_MODCTL_EXPSEL_MASK ( 0x1F << 8 )
2095 #define CPT_MODCTL_ADDRMODE_32_TEST(value) ( 0xFFFFFFFF & value )
2096 #define CPT_MODCTL_ADDRMODE_36_TEST(value) ( 0xFFFFFFF0 & value )
2097 #define CPT_MODCTL_ADDRMODE_40_TEST(value) ( 0xFFFFFF00 & value )
2098 #define CPT_MODCTL_ADDRMODE_44_TEST(value) ( 0xFFFFF000 & value )
2099 #define CPT_MODCTL_ADDRMODE_48_TEST(value) ( 0xFFFF0000 & value )
2104 #define CPT_SET_MODCTL_ALLDISABLED 0x0
2127 #define CPT_SET_MASTER_SEL_NONE 0
2128 #define CPT_SET_MASTER_SEL_ALL 0xFFFFFFFF
2129 #define CPT_NUM_MASTER_SEL_REGS 4
2229 #define CPT_GET_PACING(reg) ( reg & 0x00FFFFFF )
2230 #define CPT_SET_PACING(reg) ( reg & 0x00FFFFFF )
2246 #define CPT_GET_ADDRESSMASK(reg) ( reg & 0x1F )
2247 #define CPT_SET_ADDRESSMASK(mask) ( mask & 0x1F )
2266 #define CPT_GET_MSGPRI_STAT(reg) ( ( reg & 0x00007000 ) >> 12 )
2267 #define CPT_GET_MSGPRI_EVTE(reg) ( ( reg & 0x00000E00 ) >> 9 )
2268 #define CPT_GET_MSGPRI_EVTB(reg) ( ( reg & 0x00000038 ) >> 3 )
2269 #define CPT_GET_MSGPRI_ACC(reg) ( reg & 0x7 )
2270 #define CPT_SET_MSGPRI_STAT(msgpri) ( ( msgpri & 0x7 ) << 12 )
2271 #define CPT_SET_MSGPRI_EVTE(msgpri) ( ( msgpri & 7 ) << 9 )
2272 #define CPT_SET_MSGPRI_EVTC(msgpri) ( ( msgpri & 7 ) << 6 )
2273 #define CPT_SET_MSGPRI_EVTB(msgpri) ( ( msgpri & 7 ) << 3 )
2274 #define CPT_SET_MSGPRI_ACC(msgpri) ( msgpri & 0x7 )
2286 #define CPT_GET_OWNERSHIP(reg) ( reg & 0x1 )
2287 #define CPT_SET_OWNERSHIP ( 0x1 )
2288 #define CPT_CLR_OWNERSHIP ( 0x0 )
2295 #define CPT_GET_THROUGHPUTCNT0(reg) ( reg & 0xFFFFFF )
2302 #define CPT_GET_THROUGHPUTCNT1(reg) ( reg & 0xFFFFFF )
2310 #define CPT_GET_WAITTIMECNT(reg) ( reg & 0xFFFFFF )
2318 #define CPT_GET_GRANTCNT(reg) ( reg & 0xFFFFFF )
2327 #define CPT_GET_RAWINTSTATE(reg) ( reg & 0x1 )
2328 #define CPT_SET_RAWINTSTATE ( 0x1 )
2339 #define CPT_GET_MASKINTSTATE(reg) ( reg & 0x1 )
2340 #define CPT_CLR_MASKINTSTATE ( 0x1 )
2348 #define CPT_GET_MASKINTENABLE(reg) ( reg & 0x1 )
2349 #define CPT_SET_MASKINTENABLE ( 0x1 )
2356 #define CPT_GET_MASKINTDISABLE(reg) ( reg & 0x1 )
2357 #define CPT_SET_MASKINTDISABLE ( 0x1 )
2359 #endif // _DOXYGEN_IGNORE
2360 #endif //__CPT_COMMON_H