Common Platform (CP) Tracer Library API Reference Guide (66AK2Exx Version)
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CPTLib_66AK2Exx.h File Reference
#include <stdlib.h>
#include <stdint.h>

Go to the source code of this file.

Enumerations

enum  eCPT_ModID {
  eCPT_MSMC_0, eCPT_MSMC_1, eCPT_MSMC_2, eCPT_MSMC_3,
  eCPT_QM_MST, eCPT_DDR, eCPT_SM, eCPT_QM_CFG1,
  eCPT_SCR3_CFG, eCPT_L2_0, eCPT_QM_CFG2, eCPT_TPCC_0_4,
  eCPT_TPCC_1_2_3, eCPT_INTC_CFG, eCPT_MSMC_4, eCPT_MSMC_5,
  eCPT_MSMC_6, eCPT_MSMC_7, eCPT_SPI_ROM_EMIF16, eCPT_NETCP_USB_CFG,
  eCPT_PCIE1_CFG, eCPT_ModID_Last
}
 
enum  eCPT_MasterID {
  eCPT_MID_GEM0, eCPT_MID_reserved1, eCPT_MID_reserved2, eCPT_MID_reserved3,
  eCPT_MID_reserved4, eCPT_MID_reserved5, eCPT_MID_reserved6, eCPT_MID_reserved7,
  eCPT_MID_A15_CPU0_0, eCPT_MID_A15_CPU1_0, eCPT_MID_A15_CPU2_0, eCPT_MID_A15_CPU3_0,
  eCPT_MID_reserved12, eCPT_MID_reserved13, eCPT_MID_reserved14, eCPT_MID_reserved15,
  eCPT_MID_GEM0_CFG, eCPT_MID_reserved17, eCPT_MID_reserved18, eCPT_MID_reserved19,
  eCPT_MID_reserved20, eCPT_MID_reserved21, eCPT_MID_reserved22, eCPT_MID_reserved23,
  eCPT_MID_reserved24, eCPT_MID_EDMA0_TC0_RD, eCPT_MID_EDMA0_TC0_WR, eCPT_MID_EDMA0_TC1_RD,
  eCPT_MID_VUSR0_MST, eCPT_MID_USB_1_MST, eCPT_MID_reseerved30, eCPT_MID_PCIe,
  eCPT_MID_EDMA0_TC1_WR, eCPT_MID_EDMA1_TC0_RD, eCPT_MID_EDMA1_TC0_WR, eCPT_MID_EDMA1_TC1_RD,
  eCPT_MID_EDMA1_TC1_WR, eCPT_MID_EDMA1_TC2_RD, eCPT_MID_EDMA1_TC2_WR, eCPT_MID_EDMA1_TC3_RD,
  eCPT_MID_EDMA1_TC3_WR, eCPT_MID_EDMA2_TC0_RD, eCPT_MID_EDMA2_TC0_WR, eCPT_MID_EDMA2_TC1_RD,
  eCPT_MID_EDMA2_TC1_WR, eCPT_MID_EDMA2_TC2_RD, eCPT_MID_EDMA2_TC2_WR, eCPT_MID_EDMA2_TC3_RD,
  eCPT_MID_EDMA2_TC3_WR, eCPT_MID_EDMA3_TC0_RD, eCPT_MID_EDMA3_TC0_WR, eCPT_MID_EDMA3_TC1_RD,
  eCPT_MID_MSMC, eCPT_MID_EDMA3_TC1_WR, eCPT_MID_reserved54, eCPT_MID_reserved55,
  eCPT_MID_USB_0_MST, eCPT_MID_reserved57, eCPT_MID_reserved58, eCPT_MID_reserved59,
  eCPT_MID_reserved60, eCPT_MID_reserved61, eCPT_MID_TPCC0, eCPT_MID_TPCC1,
  eCPT_MID_TPCC2, eCPT_MID_reserved65, eCPT_MID_reserved66, eCPT_MID_reserved67,
  eCPT_MID_QM_second_Grp0, eCPT_MID_QM_second_Grp1, eCPT_MID_QM_second_Grp2, eCPT_MID_QM_second_Grp3,
  eCPT_MID_NETCP_GLOBAL1_Grp0, eCPT_MID_NETCP_GLOBAL1_Grp1, eCPT_MID_NETCP_GLOBAL1_Grp2, eCPT_MID_NETCP_GLOBAL1_Grp3,
  eCPT_MID_reserved76, eCPT_MID_reserved77, eCPT_MID_reserved78, eCPT_MID_reserved79,
  eCPT_MID_TSIP1, eCPT_MID_reserved81, eCPT_MID_reserved82, eCPT_MID_TPCC3,
  eCPT_MID_XGE_Grp0, eCPT_MID_XGE_Grp1, eCPT_MID_XGE_Grp2, eCPT_MID_XGE_Grp3,
  eCPT_MID_reserved88, eCPT_MID_reserved89, eCPT_MID_reserved90, eCPT_MID_reserved91,
  eCPT_MID_reserved92, eCPT_MID_reserved93, eCPT_MID_reserved94, eCPT_MID_reserved95,
  eCPT_MID_QM1_CDMA_Grp0, eCPT_MID_QM1_CDMA_Grp1, eCPT_MID_QM1_CDMA_Grp2, eCPT_MID_QM1_CDMA_Grp3,
  eCPT_MID_reserved100, eCPT_MID_reserved101, eCPT_MID_PCIE_1_MST, eCPT_MID_reserved103,
  eCPT_MID_reserved104, eCPT_MID_reserved105, eCPT_MID_reserved106, eCPT_MID_DAP,
  eCPT_MID_reserved108, eCPT_MID_reserved109, eCPT_MID_reserved110, eCPT_MID_reserved111,
  eCPT_MID_NETCP_LOCAL_Grp0, eCPT_MID_NETCP_LOCAL_Grp1, eCPT_MID_NETCP_LOCAL_Grp2, eCPT_MID_NETCP_LOCAL_Grp3,
  eCPT_MID_NETCP_LOCAL_Grp4, eCPT_MID_NETCP_LOCAL_Grp5, eCPT_MID_NETCP_LOCAL_Grp6, eCPT_MID_NETCP_LOCAL_Grp7,
  eCPT_MID_EDMA4_TC0_RD = 169, eCPT_MID_EDMA4_TC0_WR, eCPT_MID_EDMA4_TC1_RD, eCPT_MID_EDMA4_TC1_WR,
  eCPT_MID_TPCC4, eCPT_MID_NETCP1_CFG_MST = 178, eCPT_MID_NETCP_Grp0 = 180, eCPT_MID_NETCP_Grp1,
  eCPT_MID_NETCP_Grp2, eCPT_MID_NETCP_Grp3, eCPT_MID_Cnt = 256
}
 

Detailed Description

66AK2Exx specific CP Tracer modules definitions

Enumeration Type Documentation

enum eCPT_ModID
eCPT_ModID
CP Tracer module ids
Enumerator
eCPT_MSMC_0 

CP Tracer MSMC 0 module

eCPT_MSMC_1 

CP Tracer MSMC 1 module

eCPT_MSMC_2 

CP Tracer MSMC 2 module

eCPT_MSMC_3 

CP Tracer MSMC 3 module

eCPT_QM_MST 

CP Tracer Queue Manager Master module

eCPT_DDR 

CP Tracer DDR3A module

eCPT_SM 

CP Tracer Semaphore module

eCPT_QM_CFG1 

CP Tracer Queue Manager 1 Priority module

eCPT_SCR3_CFG 

CP Tracer SCR3 Configuration module

eCPT_L2_0 

CP Tracer L2 0 Memory Controller module

eCPT_QM_CFG2 

CP Tracer Queue Manager 2 Priority module

eCPT_TPCC_0_4 

CP Tracer EDMA3 TPCC0 and EDMA3 TPCC4 module

eCPT_TPCC_1_2_3 

CP Tracer EDMA3 TPCC1, EDMA3 TPCC2 and EDMA3 TPCC3 module

eCPT_INTC_CFG 

CP Tracer Interrupt Controller (INTC) configuration module

eCPT_MSMC_4 

CP Tracer MSMC 4 module

eCPT_MSMC_5 

CP Tracer MSMC 5 module

eCPT_MSMC_6 

CP Tracer MSMC 6 module

eCPT_MSMC_7 

CP Tracer MSMC 7 module

eCPT_SPI_ROM_EMIF16 

CP Tracer SPI, ROM and EMIF16 modules

eCPT_NETCP_USB_CFG 

CP Tracer NETCP USB Config

eCPT_PCIE1_CFG 

CP Tracer PCIE1_CFG

eCPT_MasterID
CP Tracer master ids

The following table defines the list of masters that can be enabled for throughput counting and New Request events.

Note that some masters consist of a group of IDs designated with "_GrpN" suffix. For most situations enabling the entire group rather than a single group is the typical use case. See CPT_CfgMaster() for details.

Also note that master ids 140-167 and 174-178 correspond to the CP tracer masters. These CP tracer masters are connected to the STM module via a private interconnect. We intentionally did not define these master IDs, because the transactions from these masters have no significance from an application SW point of view. Also, the transactions from these masters cannot be traced at any available CP tracers.

Data Qualifier Restriction for certain Masters
The dtype qualifier for all non-MSMC CP Tracers is tied off to the DMA value. This means that for these CP Tracers, if you exclude DMA cycles (see eCPT_SrcQual) all data accesses are filtered.
Enumerator
eCPT_MID_GEM0 

GEM0

eCPT_MID_A15_CPU0_0 

ARM A15 CPU0

eCPT_MID_A15_CPU1_0 

ARM A15 CPU1

eCPT_MID_A15_CPU2_0 

ARM A15 CPU2

eCPT_MID_A15_CPU3_0 

ARM A15 CPU3

eCPT_MID_GEM0_CFG 

GEM0 CFG

eCPT_MID_EDMA0_TC0_RD 

EDMA0 TC0 Read

eCPT_MID_EDMA0_TC0_WR 

EDMA0 TC0 Write

eCPT_MID_EDMA0_TC1_RD 

EDMA0 TC1 Read

eCPT_MID_VUSR0_MST 

VSR0_MST

eCPT_MID_USB_1_MST 

USB_1_MST

eCPT_MID_PCIe 

PCIe Master

eCPT_MID_EDMA0_TC1_WR 

EDMA0 TC1 Write

eCPT_MID_EDMA1_TC0_RD 

EDMA1 TC0 Read

eCPT_MID_EDMA1_TC0_WR 

EDMA1 TC0 Write

eCPT_MID_EDMA1_TC1_RD 

EDMA1 TC1 Read

eCPT_MID_EDMA1_TC1_WR 

EDMA1 TC1 Write

eCPT_MID_EDMA1_TC2_RD 

EDMA1 TC2 Read

eCPT_MID_EDMA1_TC2_WR 

EDMA1 TC2 Write

eCPT_MID_EDMA1_TC3_RD 

EDMA1 TC3 Read

eCPT_MID_EDMA1_TC3_WR 

EDMA1 TC3 Write

eCPT_MID_EDMA2_TC0_RD 

EDMA2 TC0 Read

eCPT_MID_EDMA2_TC0_WR 

EDMA2 TC0 Write

eCPT_MID_EDMA2_TC1_RD 

EDMA2 TC1 Read

eCPT_MID_EDMA2_TC1_WR 

EDMA2 TC1 Write

eCPT_MID_EDMA2_TC2_RD 

EDMA2 TC2 Read

eCPT_MID_EDMA2_TC2_WR 

EDMA2 TC2 Write

eCPT_MID_EDMA2_TC3_RD 

EDMA2 TC3 Read

eCPT_MID_EDMA2_TC3_WR 

EDMA2 TC3 Write

eCPT_MID_EDMA3_TC0_RD 

EDMA3 TC0 Read

eCPT_MID_EDMA3_TC0_WR 

EDMA3 TC0 Write

eCPT_MID_EDMA3_TC1_RD 

EDMA3 TC1 Read

eCPT_MID_MSMC 

MSMC (note- for transactions initiated by MSMC internally and sent to the DDR)

eCPT_MID_EDMA3_TC1_WR 

EDMA3 TC1 Write

eCPT_MID_USB_0_MST 

USB_0_MST

eCPT_MID_TPCC0 

EDMA0 CC TR

eCPT_MID_TPCC1 

EDMA1 CC TR

eCPT_MID_TPCC2 

EDMA2 CC TR

eCPT_MID_QM_second_Grp0 

QM Secondary CDMA - master 0

eCPT_MID_QM_second_Grp1 

QM Secondary CDMA - master 1

eCPT_MID_QM_second_Grp2 

QM Secondary CDMA - master 2

eCPT_MID_QM_second_Grp3 

QM Secondary CDMA - master 3

eCPT_MID_NETCP_GLOBAL1_Grp0 

NETCP_GLOBAL1 - master 0

eCPT_MID_NETCP_GLOBAL1_Grp1 

NETCP_GLOBAL1 - master 1

eCPT_MID_NETCP_GLOBAL1_Grp2 

NETCP_GLOBAL1 - master 2*

eCPT_MID_NETCP_GLOBAL1_Grp3 

NETCP_GLOBAL1 - master 3*

eCPT_MID_TSIP1 

TSIP DMA 1

eCPT_MID_TPCC3 

EDMA3 CC TR

eCPT_MID_XGE_Grp0 

XGE (10 GIG Ethernet) master 0

eCPT_MID_XGE_Grp1 

XGE (10 GIG Ethernet) master 1

eCPT_MID_XGE_Grp2 

XGE (10 GIG Ethernet) master 2

eCPT_MID_XGE_Grp3 

XGE (10 GIG Ethernet) master 3

eCPT_MID_reserved88 

RAC_C_BE0

eCPT_MID_reserved89 

RAC_C_BE1

eCPT_MID_reserved90 

RAC_D_BE0

eCPT_MID_reserved91 

RAC_D_BE1

eCPT_MID_QM1_CDMA_Grp0 

QM1_CDMA - master 0

eCPT_MID_QM1_CDMA_Grp1 

QM1_CDMA - master 1

eCPT_MID_QM1_CDMA_Grp2 

QM1_CDMA - master 2

eCPT_MID_QM1_CDMA_Grp3 

QM1_CDMA - master 3

eCPT_MID_PCIE_1_MST 

PCIE 1 master

eCPT_MID_DAP 

DAP

eCPT_MID_NETCP_LOCAL_Grp0 

NETCP_LOCAL - master 0

eCPT_MID_NETCP_LOCAL_Grp1 

NETCP_LOCAL - master 1

eCPT_MID_NETCP_LOCAL_Grp2 

NETCP_LOCAL - master 2

eCPT_MID_NETCP_LOCAL_Grp3 

NETCP_LOCAL - master 3

eCPT_MID_NETCP_LOCAL_Grp4 

NETCP_LOCAL - master 4

eCPT_MID_NETCP_LOCAL_Grp5 

NETCP_LOCAL - master 5

eCPT_MID_NETCP_LOCAL_Grp6 

NETCP_LOCAL - master 6

eCPT_MID_NETCP_LOCAL_Grp7 

NETCP_LOCAL - master 7

eCPT_MID_EDMA4_TC0_RD 

EDMA4 TC0 Read

eCPT_MID_EDMA4_TC0_WR 

EDMA4 TC0 Write

eCPT_MID_EDMA4_TC1_RD 

EDMA4 TC1 Read

eCPT_MID_EDMA4_TC1_WR 

EDMA4 TC1 Write

eCPT_MID_TPCC4 

EDMA4 CC TR

eCPT_MID_NETCP1_CFG_MST 

NETCP1 CFG master

eCPT_MID_NETCP_Grp0 

NETCP GLOBAL0 - master 0

eCPT_MID_NETCP_Grp1 

NETCP GLOBAL0 - master 1

eCPT_MID_NETCP_Grp2 

NETCP GLOBAL0 - master 2

eCPT_MID_NETCP_Grp3 

NETCP GLOBAL0 - master 3