Common Platform (CP) Tracer Library API Reference Guide (TCI6612 Version)
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CPTLib_TCI6612.h File Reference
#include <stdlib.h>
#include <stdint.h>

Go to the source code of this file.

Enumerations

enum  eCPT_ModID {
  eCPT_MSMC_0, eCPT_MSMC_1, eCPT_MSMC_2, eCPT_MSMC_3,
  eCPT_QM_MST, eCPT_DDR, eCPT_SM, eCPT_QM_CFG,
  eCPT_SCR3_CFG, eCPT_L2_0, eCPT_L2_1, eCPT_RAC,
  eCPT_RAC_CFG, eCPT_TAC, eCPT_SCR_6P_A, eCPT_DDR_2,
  eCPT_ModID_Last
}
 
enum  eCPT_MasterID {
  eCPT_MID_GEM0, eCPT_MID_GEM1, eCPT_MID_reserved2, eCPT_MID_reserved3,
  eCPT_MID_ARM_64, eCPT_MID_reserved5, eCPT_MID_reserved6, eCPT_MID_reserved7,
  eCPT_MID_GEM0_CFG, eCPT_MID_GEM1_CFG, eCPT_MID_reserved10, eCPT_MID_reserved11,
  eCPT_MID_reserved12, eCPT_MID_reserved13, eCPT_MID_reserved14, eCPT_MID_reserved15,
  eCPT_MID_EDMA0_TC0_RD, eCPT_MID_EDMA0_TC0_WR, eCPT_MID_EDMA0_TC1_RD, eCPT_MID_EDMA0_TC1_WR,
  eCPT_MID_EDMA1_TC0_RD, eCPT_MID_EDMA1_TC0_WR, eCPT_MID_EDMA1_TC1_RD, eCPT_MID_EDMA1_TC1_WR,
  eCPT_MID_EDMA1_TC2_RD, eCPT_MID_EDMA1_TC2_WR, eCPT_MID_EDMA1_TC3_RD, eCPT_MID_EDMA1_TC3_WR,
  eCPT_MID_EDMA2_TC0_RD, eCPT_MID_EDMA2_TC0_WR, eCPT_MID_EDMA2_TC1_RD, eCPT_MID_EDMA2_TC1_WR,
  eCPT_MID_EDMA2_TC2_RD, eCPT_MID_EDMA2_TC2_WR, eCPT_MID_EDMA2_TC3_RD, eCPT_MID_EDMA2_TC3_WR,
  eCPT_MID_reserved36, eCPT_MID_reserved37, eCPT_MID_SRIO_PKTDMA_Grp0, eCPT_MID_SRIO_PKTDMA_Grp1,
  eCPT_MID_FFTC_A, eCPT_MID_reserved41, eCPT_MID_FFTC_B, eCPT_MID_reserved43,
  eCPT_MID_RAC_B_BE0, eCPT_MID_RAC_B_BE1, eCPT_MID_RAC_A_BE0, eCPT_MID_RAC_A_BE1,
  eCPT_MID_DAP, eCPT_MID_TPCC0, eCPT_MID_TPCC1, eCPT_MID_TPCC2,
  eCPT_MID_MSMC, eCPT_MID_PCIe, eCPT_MID_SRIO_M, eCPT_MID_HyperBridge,
  eCPT_MID_QM_SS_Grp0, eCPT_MID_QM_SS_Grp1, eCPT_MID_QM_SS_Grp2, eCPT_MID_QM_SS_Grp3,
  eCPT_MID_reserved60, eCPT_MID_reserved61, eCPT_MID_reserved62, eCPT_MID_reserved63,
  eCPT_MID_AIF_Grp0, eCPT_MID_AIF_Grp1, eCPT_MID_AIF_Grp2, eCPT_MID_AIF_Grp3,
  eCPT_MID_AIF_Grp4, eCPT_MID_AIF_Grp5, eCPT_MID_AIF_Grp6, eCPT_MID_AIF_Grp7,
  eCPT_MID_reserved72, eCPT_MID_reserved73, eCPT_MID_reserved74, eCPT_MID_reserved75,
  eCPT_MID_reserved76, eCPT_MID_reserved77, eCPT_MID_reserved78, eCPT_MID_reserved79,
  eCPT_MID_reserved80, eCPT_MID_reserved81, eCPT_MID_reserved82, eCPT_MID_reserved83,
  eCPT_MID_reserved84, eCPT_MID_reserved85, eCPT_MID_reserved86, eCPT_MID_reserved87,
  eCPT_MID_QM_CDMA_Grp0, eCPT_MID_QM_CDMA_Grp1, eCPT_MID_QM_CDMA_Grp2, eCPT_MID_QM_CDMA_Grp3,
  eCPT_MID_NETCP_Grp0, eCPT_MID_NETCP_Grp1, eCPT_MID_TAC, eCPT_MID_reserved95,
  eCPT_MID_BCP_DIO1, eCPT_MID_BCP_CDMA, eCPT_MID_BCP_DIO0, eCPT_MID_ARM_128_Grp0 = 224,
  eCPT_MID_ARM_128_Grp1, eCPT_MID_ARM_128_Grp2, eCPT_MID_ARM_128_Grp3, eCPT_MID_ARM_128_Grp4,
  eCPT_MID_ARM_128_Grp5, eCPT_MID_ARM_128_Grp6, eCPT_MID_ARM_128_Grp7, eCPT_MID_ARM_128_Grp8,
  eCPT_MID_ARM_128_Grp9, eCPT_MID_ARM_128_Grp10, eCPT_MID_ARM_128_Grp11, eCPT_MID_ARM_128_Grp12,
  eCPT_MID_ARM_128_Grp13, eCPT_MID_ARM_128_Grp14, eCPT_MID_ARM_128_Grp15, eCPT_MID_ARM_128_Grp16,
  eCPT_MID_ARM_128_Grp17, eCPT_MID_ARM_128_Grp18, eCPT_MID_ARM_128_Grp19, eCPT_MID_ARM_128_Grp20,
  eCPT_MID_ARM_128_Grp21, eCPT_MID_ARM_128_Grp22, eCPT_MID_ARM_128_Grp23, eCPT_MID_ARM_128_Grp24,
  eCPT_MID_ARM_128_Grp25, eCPT_MID_ARM_128_Grp26, eCPT_MID_ARM_128_Grp27, eCPT_MID_ARM_128_Grp28,
  eCPT_MID_ARM_128_Grp29, eCPT_MID_ARM_128_Grp30, eCPT_MID_ARM_128_Grp31, eCPT_MID_Cnt = 256
}
 

Detailed Description

TCI6612 specific CP Tracer modules definitions

Enumeration Type Documentation

enum eCPT_ModID
eCPT_ModID
CP Tracer module ids
Enumerator
eCPT_MSMC_0 

CP Tracer MSMC 0 module

eCPT_MSMC_1 

CP Tracer MSMC 1 module

eCPT_MSMC_2 

CP Tracer MSMC 2 module

eCPT_MSMC_3 

CP Tracer MSMC 3 module

eCPT_QM_MST 

CP Tracer Queue Manager Master module

eCPT_DDR 

CP Tracer DDR module

eCPT_SM 

CP Tracer Semaphore module

eCPT_QM_CFG 

CP Tracer Queue Manager Priority module

eCPT_SCR3_CFG 

CP Tracer SCR3 Configuration module

eCPT_L2_0 

CP Tracer L2 0 Memory Controller module

eCPT_L2_1 

CP Tracer L2 1 Memory Controller module

eCPT_RAC 

CP Tracer Receiver Accelerator Coprocessor module

eCPT_RAC_CFG 

CP Tracer Receiver Accelerator Coprocessor Configuration module

eCPT_TAC 

CP Tracer Transmit Accelerator Coprocessor module

eCPT_MasterID
CP Tracer master ids

The following table defines the list of masters that can be enabled for throughput counting and New Request events.

Note that some masters consist of a group of IDs designated with "_GrpN" suffix. For most situations enabling the entire group rather than a single group is the typical use case. See CPT_CfgMaster() for details.

Also note that master ids 128-131 and 136-149 correspond to the CP tracer masters. These CP tracer masters are connected to the STM module via a private interconnect. We intentionally did not define these master IDs, because the transactions from these masters have no significance from an application SW point of view. Also, the transactions from these masters cannot be traced at any available CP tracers.

Data Qualifier Restriction for certain Masters
The dtype qualifier for all non-MSMC CP Tracers is tied off to the DMA value. This means that for these CP Tracers, if you exclude DMA cycles (see eCPT_SrcQual) all data accesses are filtered.
Enumerator
eCPT_MID_GEM0 

GEM0

eCPT_MID_GEM1 

GEM1

eCPT_MID_ARM_64 

ARM A8

eCPT_MID_GEM0_CFG 

GEM0 CFG

eCPT_MID_GEM1_CFG 

GEM1 CFG

eCPT_MID_EDMA0_TC0_RD 

EDMA0 TC0 Read

eCPT_MID_EDMA0_TC0_WR 

EDMA0 TC0 Write

eCPT_MID_EDMA0_TC1_RD 

EDMA0 TC1 Read

eCPT_MID_EDMA0_TC1_WR 

EDMA0 TC1 Write

eCPT_MID_EDMA1_TC0_RD 

EDMA1 TC0 Read

eCPT_MID_EDMA1_TC0_WR 

EDMA1 TC0 Write

eCPT_MID_EDMA1_TC1_RD 

EDMA1 TC1 Read

eCPT_MID_EDMA1_TC1_WR 

EDMA1 TC1 Write

eCPT_MID_EDMA1_TC2_RD 

EDMA1 TC2 Read

eCPT_MID_EDMA1_TC2_WR 

EDMA1 TC2 Write

eCPT_MID_EDMA1_TC3_RD 

EDMA1 TC3 Read

eCPT_MID_EDMA1_TC3_WR 

EDMA1 TC3 Write

eCPT_MID_EDMA2_TC0_RD 

EDMA2 TC0 Read

eCPT_MID_EDMA2_TC0_WR 

EDMA2 TC0 Write

eCPT_MID_EDMA2_TC1_RD 

EDMA2 TC1 Read

eCPT_MID_EDMA2_TC1_WR 

EDMA2 TC1 Write

eCPT_MID_EDMA2_TC2_RD 

EDMA2 TC2 Read

eCPT_MID_EDMA2_TC2_WR 

EDMA2 TC2 Write

eCPT_MID_EDMA2_TC3_RD 

EDMA2 TC3 Read

eCPT_MID_EDMA2_TC3_WR 

EDMA2 TC3 Write

eCPT_MID_SRIO_PKTDMA_Grp0 

SRIO_PKTDMA - master 0

eCPT_MID_SRIO_PKTDMA_Grp1 

SRIO_PKTDMA - master 1

eCPT_MID_FFTC_A 

FFTC_A

eCPT_MID_FFTC_B 

FFTC_B

eCPT_MID_RAC_B_BE0 

RAC_B_BE0

eCPT_MID_RAC_B_BE1 

RAC_B_BE1

eCPT_MID_RAC_A_BE0 

RAC_A_BE0

eCPT_MID_RAC_A_BE1 

RAC_A_BE1

eCPT_MID_DAP 

DAP

eCPT_MID_TPCC0 

TPCC0

eCPT_MID_TPCC1 

TPCC1

eCPT_MID_TPCC2 

TPCC2

eCPT_MID_MSMC 

MSMC (note- for transactions initiated by MSMC internally and sent to the DDR)

eCPT_MID_PCIe 

PCIe

eCPT_MID_SRIO_M 

SRIO Master

eCPT_MID_HyperBridge 

Hyperbridge

eCPT_MID_QM_SS_Grp0 

Queue Manager master 0

eCPT_MID_QM_SS_Grp1 

Queue Manager master 1

eCPT_MID_QM_SS_Grp2 

Queue Manager master 2

eCPT_MID_QM_SS_Grp3 

Queue Manager master 3

eCPT_MID_AIF_Grp0 

AIF - master 0

eCPT_MID_AIF_Grp1 

AIF - master 1

eCPT_MID_AIF_Grp2 

AIF - master 2*

eCPT_MID_AIF_Grp3 

AIF - master 3*

eCPT_MID_AIF_Grp4 

AIF - master 4*

eCPT_MID_AIF_Grp5 

AIF - master 5*

eCPT_MID_AIF_Grp6 

AIF - master 6*

eCPT_MID_AIF_Grp7 

AIF - master 7*

eCPT_MID_QM_CDMA_Grp0 

QM_CDMA - master 0

eCPT_MID_QM_CDMA_Grp1 

QM_CDMA - master 1

eCPT_MID_QM_CDMA_Grp2 

QM_CDMA - master 2

eCPT_MID_QM_CDMA_Grp3 

QM_CDMA - master 3

eCPT_MID_NETCP_Grp0 

Network Co-processor master 0

eCPT_MID_NETCP_Grp1 

Network Co-processor master 1

eCPT_MID_TAC 

TAC

eCPT_MID_BCP_DIO1 

BCP_DIO1

eCPT_MID_BCP_CDMA 

BCP_CDMA

eCPT_MID_BCP_DIO0 

BCP_DIO0

eCPT_MID_ARM_128_Grp0 

ARM 128 bit master0

eCPT_MID_ARM_128_Grp1 

ARM 128 bit master1

eCPT_MID_ARM_128_Grp2 

ARM 128 bit master2

eCPT_MID_ARM_128_Grp3 

ARM 128 bit master3

eCPT_MID_ARM_128_Grp4 

ARM 128 bit master4

eCPT_MID_ARM_128_Grp5 

ARM 128 bit master5

eCPT_MID_ARM_128_Grp6 

ARM 128 bit master6

eCPT_MID_ARM_128_Grp7 

ARM 128 bit master7

eCPT_MID_ARM_128_Grp8 

ARM 128 bit master8

eCPT_MID_ARM_128_Grp9 

ARM 128 bit master9

eCPT_MID_ARM_128_Grp10 

ARM 128 bit master10

eCPT_MID_ARM_128_Grp11 

ARM 128 bit master11

eCPT_MID_ARM_128_Grp12 

ARM 128 bit master12

eCPT_MID_ARM_128_Grp13 

ARM 128 bit master13

eCPT_MID_ARM_128_Grp14 

ARM 128 bit master14

eCPT_MID_ARM_128_Grp15 

ARM 128 bit master15

eCPT_MID_ARM_128_Grp16 

ARM 128 bit master16

eCPT_MID_ARM_128_Grp17 

ARM 128 bit master17

eCPT_MID_ARM_128_Grp18 

ARM 128 bit master18

eCPT_MID_ARM_128_Grp19 

ARM 128 bit master19

eCPT_MID_ARM_128_Grp20 

ARM 128 bit master20

eCPT_MID_ARM_128_Grp21 

ARM 128 bit master21

eCPT_MID_ARM_128_Grp22 

ARM 128 bit master22

eCPT_MID_ARM_128_Grp23 

ARM 128 bit master23

eCPT_MID_ARM_128_Grp24 

ARM 128 bit master24

eCPT_MID_ARM_128_Grp25 

ARM 128 bit master25

eCPT_MID_ARM_128_Grp26 

ARM 128 bit master26

eCPT_MID_ARM_128_Grp27 

ARM 128 bit master27

eCPT_MID_ARM_128_Grp28 

ARM 128 bit master28

eCPT_MID_ARM_128_Grp29 

ARM 128 bit master29

eCPT_MID_ARM_128_Grp30 

ARM 128 bit master30

eCPT_MID_ARM_128_Grp31 

ARM 128 bit master31