40 #ifndef __DRIVERLIB_I2C_H__ 41 #define __DRIVERLIB_I2C_H__ 65 #define I2C_INT_MASTER 0x00000001 66 #define I2C_INT_SLAVE 0x00000002 73 #define I2C_MASTER_CMD_SINGLE_SEND \ 75 #define I2C_MASTER_CMD_SINGLE_RECEIVE \ 77 #define I2C_MASTER_CMD_BURST_SEND_START \ 79 #define I2C_MASTER_CMD_BURST_SEND_CONT \ 81 #define I2C_MASTER_CMD_BURST_SEND_FINISH \ 83 #define I2C_MASTER_CMD_BURST_SEND_STOP \ 85 #define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ 87 #define I2C_MASTER_CMD_BURST_RECEIVE_START \ 89 #define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ 91 #define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ 93 #define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ 95 #define I2C_MASTER_CMD_QUICK_COMMAND \ 97 #define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \ 99 #define I2C_MASTER_CMD_FIFO_SINGLE_SEND \ 101 #define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \ 103 #define I2C_MASTER_CMD_FIFO_BURST_SEND_START \ 105 #define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \ 107 #define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \ 109 #define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \ 111 #define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \ 113 #define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \ 115 #define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \ 117 #define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \ 125 #define I2C_MASTER_GLITCH_FILTER_DISABLED \ 127 #define I2C_MASTER_GLITCH_FILTER_1 \ 129 #define I2C_MASTER_GLITCH_FILTER_2 \ 131 #define I2C_MASTER_GLITCH_FILTER_3 \ 133 #define I2C_MASTER_GLITCH_FILTER_4 \ 135 #define I2C_MASTER_GLITCH_FILTER_8 \ 137 #define I2C_MASTER_GLITCH_FILTER_16 \ 139 #define I2C_MASTER_GLITCH_FILTER_32 \ 147 #define I2C_MASTER_ERR_NONE 0 148 #define I2C_MASTER_ERR_ADDR_ACK 0x00000004 149 #define I2C_MASTER_ERR_DATA_ACK 0x00000008 150 #define I2C_MASTER_ERR_ARB_LOST 0x00000010 151 #define I2C_MASTER_ERR_CLK_TOUT 0x00000080 158 #define I2C_SLAVE_ACT_NONE 0 159 #define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data 160 #define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data 161 #define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte 162 #define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave 163 #define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command 164 #define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value 171 #define I2C_MASTER_MAX_RETRIES 1000 // Number of retries 178 #define I2C_MASTER_INT_RX_FIFO_FULL \ 179 0x00000800 // RX FIFO Full Interrupt 180 #define I2C_MASTER_INT_TX_FIFO_EMPTY \ 181 0x00000400 // TX FIFO Empty Interrupt 182 #define I2C_MASTER_INT_RX_FIFO_REQ \ 183 0x00000200 // RX FIFO Request Interrupt 184 #define I2C_MASTER_INT_TX_FIFO_REQ \ 185 0x00000100 // TX FIFO Request Interrupt 186 #define I2C_MASTER_INT_ARB_LOST \ 187 0x00000080 // Arb Lost Interrupt 188 #define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt 189 #define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt 190 #define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt 191 #define I2C_MASTER_INT_TX_DMA_DONE \ 192 0x00000008 // TX DMA Complete Interrupt 193 #define I2C_MASTER_INT_RX_DMA_DONE \ 194 0x00000004 // RX DMA Complete Interrupt 195 #define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt 196 #define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt 203 #define I2C_SLAVE_INT_RX_FIFO_FULL \ 204 0x00000100 // RX FIFO Full Interrupt 205 #define I2C_SLAVE_INT_TX_FIFO_EMPTY \ 206 0x00000080 // TX FIFO Empty Interrupt 207 #define I2C_SLAVE_INT_RX_FIFO_REQ \ 208 0x00000040 // RX FIFO Request Interrupt 209 #define I2C_SLAVE_INT_TX_FIFO_REQ \ 210 0x00000020 // TX FIFO Request Interrupt 211 #define I2C_SLAVE_INT_TX_DMA_DONE \ 212 0x00000010 // TX DMA Complete Interrupt 213 #define I2C_SLAVE_INT_RX_DMA_DONE \ 214 0x00000008 // RX DMA Complete Interrupt 215 #define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt 216 #define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt 217 #define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt 224 #define I2C_SLAVE_TX_FIFO_ENABLE \ 226 #define I2C_SLAVE_RX_FIFO_ENABLE \ 234 #define I2C_FIFO_CFG_TX_MASTER 0x00000000 235 #define I2C_FIFO_CFG_TX_SLAVE 0x00008000 236 #define I2C_FIFO_CFG_RX_MASTER 0x00000000 237 #define I2C_FIFO_CFG_RX_SLAVE 0x80000000 238 #define I2C_FIFO_CFG_TX_MASTER_DMA \ 240 #define I2C_FIFO_CFG_TX_SLAVE_DMA \ 242 #define I2C_FIFO_CFG_RX_MASTER_DMA \ 244 #define I2C_FIFO_CFG_RX_SLAVE_DMA \ 246 #define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000 247 #define I2C_FIFO_CFG_TX_TRIG_1 0x00000001 248 #define I2C_FIFO_CFG_TX_TRIG_2 0x00000002 249 #define I2C_FIFO_CFG_TX_TRIG_3 0x00000003 250 #define I2C_FIFO_CFG_TX_TRIG_4 0x00000004 251 #define I2C_FIFO_CFG_TX_TRIG_5 0x00000005 252 #define I2C_FIFO_CFG_TX_TRIG_6 0x00000006 253 #define I2C_FIFO_CFG_TX_TRIG_7 0x00000007 254 #define I2C_FIFO_CFG_TX_TRIG_8 0x00000008 255 #define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000 256 #define I2C_FIFO_CFG_RX_TRIG_1 0x00010000 257 #define I2C_FIFO_CFG_RX_TRIG_2 0x00020000 258 #define I2C_FIFO_CFG_RX_TRIG_3 0x00030000 259 #define I2C_FIFO_CFG_RX_TRIG_4 0x00040000 260 #define I2C_FIFO_CFG_RX_TRIG_5 0x00050000 261 #define I2C_FIFO_CFG_RX_TRIG_6 0x00060000 262 #define I2C_FIFO_CFG_RX_TRIG_7 0x00070000 263 #define I2C_FIFO_CFG_RX_TRIG_8 0x00080000 270 #define I2C_FIFO_RX_BELOW_TRIG_LEVEL \ 272 #define I2C_FIFO_RX_FULL 0x00020000 273 #define I2C_FIFO_RX_EMPTY 0x00010000 274 #define I2C_FIFO_TX_BELOW_TRIG_LEVEL \ 276 #define I2C_FIFO_TX_FULL 0x00000002 277 #define I2C_FIFO_TX_EMPTY 0x00000001 284 extern void I2CIntRegister(uint32_t ui32Base,
void(pfnHandler)(
void));
301 uint32_t ui32Config);
319 uint32_t ui32IntFlags);
321 uint32_t ui32IntFlags);
325 uint32_t ui32IntFlags);
331 uint8_t ui8SlaveAddr,
337 extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr);
339 uint8_t ui8SlaveAddr);
345 uint32_t ui32IntFlags);
361 #endif // __DRIVERLIB_I2C_H__ void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd)
Definition: i2c.c:1239
uint32_t I2CMasterBurstCountGet(uint32_t ui32Base)
Definition: i2c.c:1933
uint32_t I2CFIFODataGet(uint32_t ui32Base)
Definition: i2c.c:1831
void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable)
Definition: i2c.c:1423
void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr)
Definition: i2c.c:237
void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)
Definition: i2c.c:170
void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:632
void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:1057
bool I2CMasterBusBusy(uint32_t ui32Base)
Definition: i2c.c:1180
void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr)
Definition: i2c.c:273
void I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:566
void I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:981
void I2CMasterIntClear(uint32_t ui32Base)
Definition: i2c.c:934
bool I2CMasterBusy(uint32_t ui32Base)
Definition: i2c.c:1145
void I2CSlaveEnable(uint32_t ui32Base)
Definition: i2c.c:344
uint32_t I2CMasterDataGet(uint32_t ui32Base)
Definition: i2c.c:1364
void I2CMasterEnable(uint32_t ui32Base)
Definition: i2c.c:319
void I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length)
Definition: i2c.c:1905
void I2CSlaveDisable(uint32_t ui32Base)
Definition: i2c.c:399
void I2CIntUnregister(uint32_t ui32Base)
Definition: i2c.c:483
uint32_t I2CFIFOStatus(uint32_t ui32Base)
Definition: i2c.c:1734
bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked)
Definition: i2c.c:776
uint32_t I2CMasterLineStateGet(uint32_t ui32Base)
Definition: i2c.c:1118
void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value)
Definition: i2c.c:1395
void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data)
Definition: i2c.c:1538
void I2CSlaveIntEnable(uint32_t ui32Base)
Definition: i2c.c:591
bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked)
Definition: i2c.c:852
void I2CRxFIFOFlush(uint32_t ui32Base)
Definition: i2c.c:1704
void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config)
Definition: i2c.c:2011
uint32_t I2CMasterErr(uint32_t ui32Base)
Definition: i2c.c:1289
uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked)
Definition: i2c.c:890
uint32_t I2CSlaveStatus(uint32_t ui32Base)
Definition: i2c.c:1512
uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data)
Definition: i2c.c:1866
void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data)
Definition: i2c.c:1338
void I2CMasterIntEnable(uint32_t ui32Base)
Definition: i2c.c:522
void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config)
Definition: i2c.c:1674
void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config)
Definition: i2c.c:1604
void I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:746
void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK)
Definition: i2c.c:1458
void I2CSlaveIntDisable(uint32_t ui32Base)
Definition: i2c.c:714
void I2CTxFIFOFlush(uint32_t ui32Base)
Definition: i2c.c:1635
void I2CMasterDisable(uint32_t ui32Base)
Definition: i2c.c:374
void I2CIntRegister(uint32_t ui32Base, void(*pfnHandler)(void))
Definition: i2c.c:439
uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data)
Definition: i2c.c:1796
void I2CSlaveFIFODisable(uint32_t ui32Base)
Definition: i2c.c:2037
void I2CMasterIntDisable(uint32_t ui32Base)
Definition: i2c.c:657
void I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
Definition: i2c.c:689
void I2CSlaveIntClear(uint32_t ui32Base)
Definition: i2c.c:1017
uint32_t I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked)
Definition: i2c.c:814
void I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, bool bReceive)
Definition: i2c.c:1088
void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data)
Definition: i2c.c:1762
void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config)
Definition: i2c.c:1974
uint32_t I2CSlaveDataGet(uint32_t ui32Base)
Definition: i2c.c:1564