IAR Cortex-M4 with hard FP Timing Benchmarks
Target Platform: ti.platforms.simplelink:CC2642:1
Tool Chain Version: 8.50.1.245
BIOS Version: bios_6_81_00_03_eng
XDCTools Version: xdctools_3_61_00_16_core
Benchmark | Cycles |
---|---|
Interrupt Latency | 153 |
Hwi_restore() | 16 |
Hwi_disable() | 16 |
Hwi dispatcher prolog | 152 |
Hwi dispatcher epilog | 239 |
Hwi dispatcher | 380 |
Hardware Interrupt to Blocked Task | 652 |
Hardware Interrupt to Software Interrupt | 456 |
Swi_enable() | 82 |
Swi_disable() | 20 |
Post Software Interrupt Again | 36 |
Post Software Interrupt without Context Switch | 113 |
Post Software Interrupt with Context Switch | 241 |
Create a New Task without Context Switch | 2552 |
Set a Task Priority without a Context Switch | 217 |
Task_yield() | 290 |
Post Semaphore No Waiting Task | 60 |
Post Semaphore No Task Switch | 227 |
Post Semaphore with Task Switch | 338 |
Pend on Semaphore No Context Switch | 75 |
Pend on Semaphore with Task Switch | 377 |
Clock_getTicks() | 289 |
POSIX Create a New Task without Context Switch | 5266 |
POSIX Set a Task Priority without a Context Switch | 303 |
POSIX Post Semaphore No Waiting Task | 73 |
POSIX Post Semaphore No Task Switch | 240 |
POSIX Post Semaphore with Task Switch | 349 |
POSIX Pend on Semaphore No Context Switch | 89 |
POSIX Pend on Semaphore with Task Switch | 390 |
The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.
See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.