![](tilogo.gif) |
![](titagline.gif) |
Go to the documentation of this file. 34 #ifndef __HW_CPU_TPIU_H__ 35 #define __HW_CPU_TPIU_H__ 44 #define CPU_TPIU_O_SSPSR 0x00000000 47 #define CPU_TPIU_O_CSPSR 0x00000004 50 #define CPU_TPIU_O_ACPR 0x00000010 53 #define CPU_TPIU_O_SPPR 0x000000F0 56 #define CPU_TPIU_O_FFSR 0x00000300 59 #define CPU_TPIU_O_FFCR 0x00000304 62 #define CPU_TPIU_O_FSCR 0x00000308 65 #define CPU_TPIU_O_CLAIMMASK 0x00000FA0 68 #define CPU_TPIU_O_CLAIMSET 0x00000FA0 71 #define CPU_TPIU_O_CLAIMTAG 0x00000FA4 74 #define CPU_TPIU_O_CLAIMCLR 0x00000FA4 77 #define CPU_TPIU_O_LAR 0x00000FB0 80 #define CPU_TPIU_O_DEVID 0x00000FC8 93 #define CPU_TPIU_SSPSR_FOUR 0x00000008 94 #define CPU_TPIU_SSPSR_FOUR_BITN 3 95 #define CPU_TPIU_SSPSR_FOUR_M 0x00000008 96 #define CPU_TPIU_SSPSR_FOUR_S 3 104 #define CPU_TPIU_SSPSR_THREE 0x00000004 105 #define CPU_TPIU_SSPSR_THREE_BITN 2 106 #define CPU_TPIU_SSPSR_THREE_M 0x00000004 107 #define CPU_TPIU_SSPSR_THREE_S 2 115 #define CPU_TPIU_SSPSR_TWO 0x00000002 116 #define CPU_TPIU_SSPSR_TWO_BITN 1 117 #define CPU_TPIU_SSPSR_TWO_M 0x00000002 118 #define CPU_TPIU_SSPSR_TWO_S 1 126 #define CPU_TPIU_SSPSR_ONE 0x00000001 127 #define CPU_TPIU_SSPSR_ONE_BITN 0 128 #define CPU_TPIU_SSPSR_ONE_M 0x00000001 129 #define CPU_TPIU_SSPSR_ONE_S 0 141 #define CPU_TPIU_CSPSR_FOUR 0x00000008 142 #define CPU_TPIU_CSPSR_FOUR_BITN 3 143 #define CPU_TPIU_CSPSR_FOUR_M 0x00000008 144 #define CPU_TPIU_CSPSR_FOUR_S 3 151 #define CPU_TPIU_CSPSR_THREE 0x00000004 152 #define CPU_TPIU_CSPSR_THREE_BITN 2 153 #define CPU_TPIU_CSPSR_THREE_M 0x00000004 154 #define CPU_TPIU_CSPSR_THREE_S 2 161 #define CPU_TPIU_CSPSR_TWO 0x00000002 162 #define CPU_TPIU_CSPSR_TWO_BITN 1 163 #define CPU_TPIU_CSPSR_TWO_M 0x00000002 164 #define CPU_TPIU_CSPSR_TWO_S 1 171 #define CPU_TPIU_CSPSR_ONE 0x00000001 172 #define CPU_TPIU_CSPSR_ONE_BITN 0 173 #define CPU_TPIU_CSPSR_ONE_M 0x00000001 174 #define CPU_TPIU_CSPSR_ONE_S 0 184 #define CPU_TPIU_ACPR_PRESCALER_W 13 185 #define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF 186 #define CPU_TPIU_ACPR_PRESCALER_S 0 201 #define CPU_TPIU_SPPR_PROTOCOL_W 2 202 #define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 203 #define CPU_TPIU_SPPR_PROTOCOL_S 0 204 #define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 205 #define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 206 #define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 217 #define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 218 #define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 219 #define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 220 #define CPU_TPIU_FFSR_FTNONSTOP_S 3 230 #define CPU_TPIU_FFCR_TRIGIN 0x00000100 231 #define CPU_TPIU_FFCR_TRIGIN_BITN 8 232 #define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 233 #define CPU_TPIU_FFCR_TRIGIN_S 8 241 #define CPU_TPIU_FFCR_ENFCONT 0x00000002 242 #define CPU_TPIU_FFCR_ENFCONT_BITN 1 243 #define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 244 #define CPU_TPIU_FFCR_ENFCONT_S 1 256 #define CPU_TPIU_FSCR_FSCR_W 32 257 #define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF 258 #define CPU_TPIU_FSCR_FSCR_S 0 275 #define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 276 #define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF 277 #define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 294 #define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 295 #define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF 296 #define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 310 #define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 311 #define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF 312 #define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 329 #define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 330 #define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF 331 #define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 343 #define CPU_TPIU_DEVID_NRZ_SWO 0x00000400 344 #define CPU_TPIU_DEVID_NRZ_SWO_BITN 11 345 #define CPU_TPIU_DEVID_NRZ_SWO_M 0x00000400 346 #define CPU_TPIU_DEVID_NRZ_SWO_S 11 351 #define CPU_TPIU_DEVID_MANCHESTER_SWO 0x00000200 352 #define CPU_TPIU_DEVID_MANCHESTER_SWO_BITN 10 353 #define CPU_TPIU_DEVID_MANCHESTER_SWO_M 0x00000200 354 #define CPU_TPIU_DEVID_MANCHESTER_SWO_S 10 360 #define CPU_TPIU_DEVID_PARALLEL_TRACE 0x00000100 361 #define CPU_TPIU_DEVID_PARALLEL_TRACE_BITN 9 362 #define CPU_TPIU_DEVID_PARALLEL_TRACE_M 0x00000100 363 #define CPU_TPIU_DEVID_PARALLEL_TRACE_S 9 368 #define CPU_TPIU_DEVID_FIFO_SIZE_W 2 369 #define CPU_TPIU_DEVID_FIFO_SIZE_M 0x000001C0 370 #define CPU_TPIU_DEVID_FIFO_SIZE_S 6 376 #define CPU_TPIU_DEVID_ASYNC_TRACECLKIN 0x00000020 377 #define CPU_TPIU_DEVID_ASYNC_TRACECLKIN_BITN 5 378 #define CPU_TPIU_DEVID_ASYNC_TRACECLKIN_M 0x00000020 379 #define CPU_TPIU_DEVID_ASYNC_TRACECLKIN_S 5 388 #define CPU_TPIU_DEVID_NUM_INPUTS_W 5 389 #define CPU_TPIU_DEVID_NUM_INPUTS_M 0x0000001F 390 #define CPU_TPIU_DEVID_NUM_INPUTS_S 0 391 #define CPU_TPIU_DEVID_NUM_INPUTS_ONE 0x00000000 392 #define CPU_TPIU_DEVID_NUM_INPUTS_TWO 0x00000001 395 #endif // __CPU_TPIU__
© Copyright 1995-2021, Texas Instruments Incorporated. All rights reserved.
Trademarks | Privacy policy | Terms of use | Terms of sale