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Go to the documentation of this file. 34 #ifndef __HW_CPU_SCS_H__ 35 #define __HW_CPU_SCS_H__ 44 #define CPU_SCS_O_ICTR 0x00000004 47 #define CPU_SCS_O_ACTLR 0x00000008 50 #define CPU_SCS_O_STCSR 0x00000010 53 #define CPU_SCS_O_STRVR 0x00000014 56 #define CPU_SCS_O_STCVR 0x00000018 59 #define CPU_SCS_O_STCR 0x0000001C 62 #define CPU_SCS_O_NVIC_ISER0 0x00000100 65 #define CPU_SCS_O_NVIC_ISER1 0x00000104 68 #define CPU_SCS_O_NVIC_ICER0 0x00000180 71 #define CPU_SCS_O_NVIC_ICER1 0x00000184 74 #define CPU_SCS_O_NVIC_ISPR0 0x00000200 77 #define CPU_SCS_O_NVIC_ISPR1 0x00000204 80 #define CPU_SCS_O_NVIC_ICPR0 0x00000280 83 #define CPU_SCS_O_NVIC_ICPR1 0x00000284 86 #define CPU_SCS_O_NVIC_IABR0 0x00000300 89 #define CPU_SCS_O_NVIC_IABR1 0x00000304 92 #define CPU_SCS_O_NVIC_IPR0 0x00000400 95 #define CPU_SCS_O_NVIC_IPR1 0x00000404 98 #define CPU_SCS_O_NVIC_IPR2 0x00000408 101 #define CPU_SCS_O_NVIC_IPR3 0x0000040C 104 #define CPU_SCS_O_NVIC_IPR4 0x00000410 107 #define CPU_SCS_O_NVIC_IPR5 0x00000414 110 #define CPU_SCS_O_NVIC_IPR6 0x00000418 113 #define CPU_SCS_O_NVIC_IPR7 0x0000041C 116 #define CPU_SCS_O_NVIC_IPR8 0x00000420 119 #define CPU_SCS_O_NVIC_IPR9 0x00000424 122 #define CPU_SCS_O_CPUID 0x00000D00 125 #define CPU_SCS_O_ICSR 0x00000D04 128 #define CPU_SCS_O_VTOR 0x00000D08 131 #define CPU_SCS_O_AIRCR 0x00000D0C 134 #define CPU_SCS_O_SCR 0x00000D10 137 #define CPU_SCS_O_CCR 0x00000D14 140 #define CPU_SCS_O_SHPR1 0x00000D18 143 #define CPU_SCS_O_SHPR2 0x00000D1C 146 #define CPU_SCS_O_SHPR3 0x00000D20 149 #define CPU_SCS_O_SHCSR 0x00000D24 152 #define CPU_SCS_O_CFSR 0x00000D28 155 #define CPU_SCS_O_HFSR 0x00000D2C 158 #define CPU_SCS_O_DFSR 0x00000D30 161 #define CPU_SCS_O_MMFAR 0x00000D34 164 #define CPU_SCS_O_BFAR 0x00000D38 167 #define CPU_SCS_O_AFSR 0x00000D3C 170 #define CPU_SCS_O_ID_PFR0 0x00000D40 173 #define CPU_SCS_O_ID_PFR1 0x00000D44 176 #define CPU_SCS_O_ID_DFR0 0x00000D48 179 #define CPU_SCS_O_ID_AFR0 0x00000D4C 182 #define CPU_SCS_O_ID_MMFR0 0x00000D50 185 #define CPU_SCS_O_ID_MMFR1 0x00000D54 188 #define CPU_SCS_O_ID_MMFR2 0x00000D58 191 #define CPU_SCS_O_ID_MMFR3 0x00000D5C 194 #define CPU_SCS_O_ID_ISAR0 0x00000D60 197 #define CPU_SCS_O_ID_ISAR1 0x00000D64 200 #define CPU_SCS_O_ID_ISAR2 0x00000D68 203 #define CPU_SCS_O_ID_ISAR3 0x00000D6C 206 #define CPU_SCS_O_ID_ISAR4 0x00000D70 209 #define CPU_SCS_O_CPACR 0x00000D88 212 #define CPU_SCS_O_MPU_TYPE 0x00000D90 215 #define CPU_SCS_O_MPU_CTRL 0x00000D94 218 #define CPU_SCS_O_MPU_RNR 0x00000D98 221 #define CPU_SCS_O_MPU_RBAR 0x00000D9C 224 #define CPU_SCS_O_MPU_RASR 0x00000DA0 227 #define CPU_SCS_O_MPU_RBAR_A1 0x00000DA4 230 #define CPU_SCS_O_MPU_RASR_A1 0x00000DA8 233 #define CPU_SCS_O_MPU_RBAR_A2 0x00000DAC 236 #define CPU_SCS_O_MPU_RASR_A2 0x00000DB0 239 #define CPU_SCS_O_MPU_RBAR_A3 0x00000DB4 242 #define CPU_SCS_O_MPU_RASR_A3 0x00000DB8 245 #define CPU_SCS_O_DHCSR 0x00000DF0 248 #define CPU_SCS_O_DCRSR 0x00000DF4 251 #define CPU_SCS_O_DCRDR 0x00000DF8 254 #define CPU_SCS_O_DEMCR 0x00000DFC 257 #define CPU_SCS_O_STIR 0x00000F00 260 #define CPU_SCS_O_FPCCR 0x00000F34 263 #define CPU_SCS_O_FPCAR 0x00000F38 266 #define CPU_SCS_O_FPDSCR 0x00000F3C 269 #define CPU_SCS_O_MVFR0 0x00000F40 272 #define CPU_SCS_O_MVFR1 0x00000F44 291 #define CPU_SCS_ICTR_INTLINESNUM_W 3 292 #define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 293 #define CPU_SCS_ICTR_INTLINESNUM_S 0 304 #define CPU_SCS_ACTLR_DISOOFP 0x00000200 305 #define CPU_SCS_ACTLR_DISOOFP_BITN 9 306 #define CPU_SCS_ACTLR_DISOOFP_M 0x00000200 307 #define CPU_SCS_ACTLR_DISOOFP_S 9 312 #define CPU_SCS_ACTLR_DISFPCA 0x00000100 313 #define CPU_SCS_ACTLR_DISFPCA_BITN 8 314 #define CPU_SCS_ACTLR_DISFPCA_M 0x00000100 315 #define CPU_SCS_ACTLR_DISFPCA_S 8 320 #define CPU_SCS_ACTLR_DISFOLD 0x00000004 321 #define CPU_SCS_ACTLR_DISFOLD_BITN 2 322 #define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 323 #define CPU_SCS_ACTLR_DISFOLD_S 2 331 #define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 332 #define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 333 #define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 334 #define CPU_SCS_ACTLR_DISDEFWBUF_S 1 341 #define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 342 #define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 343 #define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 344 #define CPU_SCS_ACTLR_DISMCYCINT_S 0 358 #define CPU_SCS_STCSR_COUNTFLAG 0x00010000 359 #define CPU_SCS_STCSR_COUNTFLAG_BITN 16 360 #define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 361 #define CPU_SCS_STCSR_COUNTFLAG_S 16 372 #define CPU_SCS_STCSR_CLKSOURCE 0x00000004 373 #define CPU_SCS_STCSR_CLKSOURCE_BITN 2 374 #define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 375 #define CPU_SCS_STCSR_CLKSOURCE_S 2 382 #define CPU_SCS_STCSR_TICKINT 0x00000002 383 #define CPU_SCS_STCSR_TICKINT_BITN 1 384 #define CPU_SCS_STCSR_TICKINT_M 0x00000002 385 #define CPU_SCS_STCSR_TICKINT_S 1 396 #define CPU_SCS_STCSR_ENABLE 0x00000001 397 #define CPU_SCS_STCSR_ENABLE_BITN 0 398 #define CPU_SCS_STCSR_ENABLE_M 0x00000001 399 #define CPU_SCS_STCSR_ENABLE_S 0 410 #define CPU_SCS_STRVR_RELOAD_W 24 411 #define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF 412 #define CPU_SCS_STRVR_RELOAD_S 0 425 #define CPU_SCS_STCVR_CURRENT_W 24 426 #define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF 427 #define CPU_SCS_STCVR_CURRENT_S 0 437 #define CPU_SCS_STCR_NOREF 0x80000000 438 #define CPU_SCS_STCR_NOREF_BITN 31 439 #define CPU_SCS_STCR_NOREF_M 0x80000000 440 #define CPU_SCS_STCR_NOREF_S 31 446 #define CPU_SCS_STCR_SKEW 0x40000000 447 #define CPU_SCS_STCR_SKEW_BITN 30 448 #define CPU_SCS_STCR_SKEW_M 0x40000000 449 #define CPU_SCS_STCR_SKEW_S 30 456 #define CPU_SCS_STCR_TENMS_W 24 457 #define CPU_SCS_STCR_TENMS_M 0x00FFFFFF 458 #define CPU_SCS_STCR_TENMS_S 0 470 #define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 471 #define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 472 #define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 473 #define CPU_SCS_NVIC_ISER0_SETENA31_S 31 480 #define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 481 #define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 482 #define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 483 #define CPU_SCS_NVIC_ISER0_SETENA30_S 30 490 #define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 491 #define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 492 #define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 493 #define CPU_SCS_NVIC_ISER0_SETENA29_S 29 500 #define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 501 #define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 502 #define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 503 #define CPU_SCS_NVIC_ISER0_SETENA28_S 28 510 #define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 511 #define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 512 #define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 513 #define CPU_SCS_NVIC_ISER0_SETENA27_S 27 520 #define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 521 #define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 522 #define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 523 #define CPU_SCS_NVIC_ISER0_SETENA26_S 26 530 #define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 531 #define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 532 #define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 533 #define CPU_SCS_NVIC_ISER0_SETENA25_S 25 540 #define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 541 #define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 542 #define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 543 #define CPU_SCS_NVIC_ISER0_SETENA24_S 24 550 #define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 551 #define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 552 #define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 553 #define CPU_SCS_NVIC_ISER0_SETENA23_S 23 560 #define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 561 #define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 562 #define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 563 #define CPU_SCS_NVIC_ISER0_SETENA22_S 22 570 #define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 571 #define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 572 #define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 573 #define CPU_SCS_NVIC_ISER0_SETENA21_S 21 580 #define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 581 #define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 582 #define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 583 #define CPU_SCS_NVIC_ISER0_SETENA20_S 20 590 #define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 591 #define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 592 #define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 593 #define CPU_SCS_NVIC_ISER0_SETENA19_S 19 600 #define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 601 #define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 602 #define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 603 #define CPU_SCS_NVIC_ISER0_SETENA18_S 18 610 #define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 611 #define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 612 #define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 613 #define CPU_SCS_NVIC_ISER0_SETENA17_S 17 620 #define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 621 #define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 622 #define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 623 #define CPU_SCS_NVIC_ISER0_SETENA16_S 16 630 #define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 631 #define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 632 #define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 633 #define CPU_SCS_NVIC_ISER0_SETENA15_S 15 640 #define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 641 #define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 642 #define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 643 #define CPU_SCS_NVIC_ISER0_SETENA14_S 14 650 #define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 651 #define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 652 #define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 653 #define CPU_SCS_NVIC_ISER0_SETENA13_S 13 660 #define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 661 #define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 662 #define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 663 #define CPU_SCS_NVIC_ISER0_SETENA12_S 12 670 #define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 671 #define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 672 #define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 673 #define CPU_SCS_NVIC_ISER0_SETENA11_S 11 680 #define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 681 #define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 682 #define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 683 #define CPU_SCS_NVIC_ISER0_SETENA10_S 10 690 #define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 691 #define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 692 #define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 693 #define CPU_SCS_NVIC_ISER0_SETENA9_S 9 700 #define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 701 #define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 702 #define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 703 #define CPU_SCS_NVIC_ISER0_SETENA8_S 8 710 #define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 711 #define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 712 #define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 713 #define CPU_SCS_NVIC_ISER0_SETENA7_S 7 720 #define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 721 #define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 722 #define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 723 #define CPU_SCS_NVIC_ISER0_SETENA6_S 6 730 #define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 731 #define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 732 #define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 733 #define CPU_SCS_NVIC_ISER0_SETENA5_S 5 740 #define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 741 #define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 742 #define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 743 #define CPU_SCS_NVIC_ISER0_SETENA4_S 4 750 #define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 751 #define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 752 #define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 753 #define CPU_SCS_NVIC_ISER0_SETENA3_S 3 760 #define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 761 #define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 762 #define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 763 #define CPU_SCS_NVIC_ISER0_SETENA2_S 2 770 #define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 771 #define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 772 #define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 773 #define CPU_SCS_NVIC_ISER0_SETENA1_S 1 780 #define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 781 #define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 782 #define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 783 #define CPU_SCS_NVIC_ISER0_SETENA0_S 0 795 #define CPU_SCS_NVIC_ISER1_SETENA37 0x00000020 796 #define CPU_SCS_NVIC_ISER1_SETENA37_BITN 5 797 #define CPU_SCS_NVIC_ISER1_SETENA37_M 0x00000020 798 #define CPU_SCS_NVIC_ISER1_SETENA37_S 5 805 #define CPU_SCS_NVIC_ISER1_SETENA36 0x00000010 806 #define CPU_SCS_NVIC_ISER1_SETENA36_BITN 4 807 #define CPU_SCS_NVIC_ISER1_SETENA36_M 0x00000010 808 #define CPU_SCS_NVIC_ISER1_SETENA36_S 4 815 #define CPU_SCS_NVIC_ISER1_SETENA35 0x00000008 816 #define CPU_SCS_NVIC_ISER1_SETENA35_BITN 3 817 #define CPU_SCS_NVIC_ISER1_SETENA35_M 0x00000008 818 #define CPU_SCS_NVIC_ISER1_SETENA35_S 3 825 #define CPU_SCS_NVIC_ISER1_SETENA34 0x00000004 826 #define CPU_SCS_NVIC_ISER1_SETENA34_BITN 2 827 #define CPU_SCS_NVIC_ISER1_SETENA34_M 0x00000004 828 #define CPU_SCS_NVIC_ISER1_SETENA34_S 2 835 #define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 836 #define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 837 #define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 838 #define CPU_SCS_NVIC_ISER1_SETENA33_S 1 845 #define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 846 #define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 847 #define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 848 #define CPU_SCS_NVIC_ISER1_SETENA32_S 0 860 #define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 861 #define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 862 #define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 863 #define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 870 #define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 871 #define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 872 #define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 873 #define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 880 #define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 881 #define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 882 #define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 883 #define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 890 #define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 891 #define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 892 #define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 893 #define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 900 #define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 901 #define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 902 #define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 903 #define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 910 #define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 911 #define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 912 #define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 913 #define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 920 #define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 921 #define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 922 #define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 923 #define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 930 #define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 931 #define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 932 #define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 933 #define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 940 #define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 941 #define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 942 #define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 943 #define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 950 #define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 951 #define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 952 #define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 953 #define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 960 #define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 961 #define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 962 #define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 963 #define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 970 #define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 971 #define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 972 #define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 973 #define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 980 #define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 981 #define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 982 #define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 983 #define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 990 #define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 991 #define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 992 #define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 993 #define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 1000 #define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 1001 #define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 1002 #define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 1003 #define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 1010 #define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 1011 #define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 1012 #define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 1013 #define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 1020 #define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 1021 #define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 1022 #define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 1023 #define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 1030 #define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 1031 #define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 1032 #define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 1033 #define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 1040 #define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 1041 #define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 1042 #define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 1043 #define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 1050 #define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 1051 #define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 1052 #define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 1053 #define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 1060 #define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 1061 #define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 1062 #define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 1063 #define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 1070 #define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 1071 #define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 1072 #define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 1073 #define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 1080 #define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 1081 #define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 1082 #define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 1083 #define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 1090 #define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 1091 #define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 1092 #define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 1093 #define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 1100 #define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 1101 #define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 1102 #define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 1103 #define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 1110 #define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 1111 #define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 1112 #define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 1113 #define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 1120 #define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 1121 #define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 1122 #define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 1123 #define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 1130 #define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 1131 #define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 1132 #define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 1133 #define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 1140 #define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 1141 #define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 1142 #define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 1143 #define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 1150 #define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 1151 #define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 1152 #define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 1153 #define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 1160 #define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 1161 #define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 1162 #define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 1163 #define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 1170 #define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 1171 #define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 1172 #define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 1173 #define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 1185 #define CPU_SCS_NVIC_ICER1_CLRENA37 0x00000020 1186 #define CPU_SCS_NVIC_ICER1_CLRENA37_BITN 5 1187 #define CPU_SCS_NVIC_ICER1_CLRENA37_M 0x00000020 1188 #define CPU_SCS_NVIC_ICER1_CLRENA37_S 5 1195 #define CPU_SCS_NVIC_ICER1_CLRENA36 0x00000010 1196 #define CPU_SCS_NVIC_ICER1_CLRENA36_BITN 4 1197 #define CPU_SCS_NVIC_ICER1_CLRENA36_M 0x00000010 1198 #define CPU_SCS_NVIC_ICER1_CLRENA36_S 4 1205 #define CPU_SCS_NVIC_ICER1_CLRENA35 0x00000008 1206 #define CPU_SCS_NVIC_ICER1_CLRENA35_BITN 3 1207 #define CPU_SCS_NVIC_ICER1_CLRENA35_M 0x00000008 1208 #define CPU_SCS_NVIC_ICER1_CLRENA35_S 3 1215 #define CPU_SCS_NVIC_ICER1_CLRENA34 0x00000004 1216 #define CPU_SCS_NVIC_ICER1_CLRENA34_BITN 2 1217 #define CPU_SCS_NVIC_ICER1_CLRENA34_M 0x00000004 1218 #define CPU_SCS_NVIC_ICER1_CLRENA34_S 2 1225 #define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 1226 #define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 1227 #define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 1228 #define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 1235 #define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 1236 #define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 1237 #define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 1238 #define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 1250 #define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 1251 #define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 1252 #define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 1253 #define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 1260 #define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 1261 #define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 1262 #define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 1263 #define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 1270 #define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 1271 #define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 1272 #define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 1273 #define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 1280 #define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 1281 #define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 1282 #define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 1283 #define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 1290 #define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 1291 #define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 1292 #define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 1293 #define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 1300 #define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 1301 #define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 1302 #define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 1303 #define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 1310 #define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 1311 #define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 1312 #define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 1313 #define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 1320 #define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 1321 #define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 1322 #define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 1323 #define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 1330 #define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 1331 #define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 1332 #define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 1333 #define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 1340 #define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 1341 #define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 1342 #define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 1343 #define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 1350 #define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 1351 #define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 1352 #define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 1353 #define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 1360 #define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 1361 #define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 1362 #define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 1363 #define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 1370 #define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 1371 #define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 1372 #define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 1373 #define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 1380 #define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 1381 #define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 1382 #define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 1383 #define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 1390 #define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 1391 #define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 1392 #define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 1393 #define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 1400 #define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 1401 #define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 1402 #define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 1403 #define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 1410 #define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 1411 #define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 1412 #define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 1413 #define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 1420 #define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 1421 #define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 1422 #define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 1423 #define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 1430 #define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 1431 #define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 1432 #define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 1433 #define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 1440 #define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 1441 #define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 1442 #define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 1443 #define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 1450 #define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 1451 #define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 1452 #define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 1453 #define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 1460 #define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 1461 #define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 1462 #define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 1463 #define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 1470 #define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 1471 #define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 1472 #define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 1473 #define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 1480 #define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 1481 #define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 1482 #define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 1483 #define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 1490 #define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 1491 #define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 1492 #define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 1493 #define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 1500 #define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 1501 #define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 1502 #define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 1503 #define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 1510 #define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 1511 #define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 1512 #define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 1513 #define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 1520 #define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 1521 #define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 1522 #define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 1523 #define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 1530 #define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 1531 #define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 1532 #define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 1533 #define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 1540 #define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 1541 #define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 1542 #define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 1543 #define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 1550 #define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 1551 #define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 1552 #define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 1553 #define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 1560 #define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 1561 #define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 1562 #define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 1563 #define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 1575 #define CPU_SCS_NVIC_ISPR1_SETPEND37 0x00000020 1576 #define CPU_SCS_NVIC_ISPR1_SETPEND37_BITN 5 1577 #define CPU_SCS_NVIC_ISPR1_SETPEND37_M 0x00000020 1578 #define CPU_SCS_NVIC_ISPR1_SETPEND37_S 5 1585 #define CPU_SCS_NVIC_ISPR1_SETPEND36 0x00000010 1586 #define CPU_SCS_NVIC_ISPR1_SETPEND36_BITN 4 1587 #define CPU_SCS_NVIC_ISPR1_SETPEND36_M 0x00000010 1588 #define CPU_SCS_NVIC_ISPR1_SETPEND36_S 4 1595 #define CPU_SCS_NVIC_ISPR1_SETPEND35 0x00000008 1596 #define CPU_SCS_NVIC_ISPR1_SETPEND35_BITN 3 1597 #define CPU_SCS_NVIC_ISPR1_SETPEND35_M 0x00000008 1598 #define CPU_SCS_NVIC_ISPR1_SETPEND35_S 3 1605 #define CPU_SCS_NVIC_ISPR1_SETPEND34 0x00000004 1606 #define CPU_SCS_NVIC_ISPR1_SETPEND34_BITN 2 1607 #define CPU_SCS_NVIC_ISPR1_SETPEND34_M 0x00000004 1608 #define CPU_SCS_NVIC_ISPR1_SETPEND34_S 2 1615 #define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 1616 #define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 1617 #define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 1618 #define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 1625 #define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 1626 #define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 1627 #define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 1628 #define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 1640 #define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 1641 #define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 1642 #define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 1643 #define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 1650 #define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 1651 #define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 1652 #define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 1653 #define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 1660 #define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 1661 #define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 1662 #define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 1663 #define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 1670 #define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 1671 #define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 1672 #define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 1673 #define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 1680 #define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 1681 #define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 1682 #define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 1683 #define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 1690 #define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 1691 #define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 1692 #define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 1693 #define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 1700 #define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 1701 #define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 1702 #define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 1703 #define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 1710 #define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 1711 #define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 1712 #define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 1713 #define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 1720 #define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 1721 #define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 1722 #define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 1723 #define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 1730 #define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 1731 #define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 1732 #define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 1733 #define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 1740 #define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 1741 #define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 1742 #define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 1743 #define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 1750 #define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 1751 #define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 1752 #define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 1753 #define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 1760 #define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 1761 #define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 1762 #define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 1763 #define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 1770 #define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 1771 #define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 1772 #define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 1773 #define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 1780 #define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 1781 #define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 1782 #define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 1783 #define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 1790 #define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 1791 #define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 1792 #define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 1793 #define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 1800 #define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 1801 #define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 1802 #define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 1803 #define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 1810 #define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 1811 #define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 1812 #define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 1813 #define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 1820 #define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 1821 #define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 1822 #define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 1823 #define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 1830 #define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 1831 #define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 1832 #define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 1833 #define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 1840 #define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 1841 #define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 1842 #define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 1843 #define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 1850 #define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 1851 #define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 1852 #define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 1853 #define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 1860 #define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 1861 #define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 1862 #define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 1863 #define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 1870 #define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 1871 #define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 1872 #define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 1873 #define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 1880 #define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 1881 #define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 1882 #define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 1883 #define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 1890 #define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 1891 #define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 1892 #define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 1893 #define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 1900 #define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 1901 #define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 1902 #define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 1903 #define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 1910 #define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 1911 #define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 1912 #define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 1913 #define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 1920 #define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 1921 #define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 1922 #define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 1923 #define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 1930 #define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 1931 #define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 1932 #define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 1933 #define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 1940 #define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 1941 #define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 1942 #define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 1943 #define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 1950 #define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 1951 #define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 1952 #define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 1953 #define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 1965 #define CPU_SCS_NVIC_ICPR1_CLRPEND37 0x00000020 1966 #define CPU_SCS_NVIC_ICPR1_CLRPEND37_BITN 5 1967 #define CPU_SCS_NVIC_ICPR1_CLRPEND37_M 0x00000020 1968 #define CPU_SCS_NVIC_ICPR1_CLRPEND37_S 5 1975 #define CPU_SCS_NVIC_ICPR1_CLRPEND36 0x00000010 1976 #define CPU_SCS_NVIC_ICPR1_CLRPEND36_BITN 4 1977 #define CPU_SCS_NVIC_ICPR1_CLRPEND36_M 0x00000010 1978 #define CPU_SCS_NVIC_ICPR1_CLRPEND36_S 4 1985 #define CPU_SCS_NVIC_ICPR1_CLRPEND35 0x00000008 1986 #define CPU_SCS_NVIC_ICPR1_CLRPEND35_BITN 3 1987 #define CPU_SCS_NVIC_ICPR1_CLRPEND35_M 0x00000008 1988 #define CPU_SCS_NVIC_ICPR1_CLRPEND35_S 3 1995 #define CPU_SCS_NVIC_ICPR1_CLRPEND34 0x00000004 1996 #define CPU_SCS_NVIC_ICPR1_CLRPEND34_BITN 2 1997 #define CPU_SCS_NVIC_ICPR1_CLRPEND34_M 0x00000004 1998 #define CPU_SCS_NVIC_ICPR1_CLRPEND34_S 2 2005 #define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 2006 #define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 2007 #define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 2008 #define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 2015 #define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 2016 #define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 2017 #define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 2018 #define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 2030 #define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 2031 #define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 2032 #define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 2033 #define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 2040 #define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 2041 #define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 2042 #define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 2043 #define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 2050 #define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 2051 #define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 2052 #define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 2053 #define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 2060 #define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 2061 #define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 2062 #define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 2063 #define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 2070 #define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 2071 #define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 2072 #define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 2073 #define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 2080 #define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 2081 #define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 2082 #define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 2083 #define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 2090 #define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 2091 #define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 2092 #define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 2093 #define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 2100 #define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 2101 #define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 2102 #define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 2103 #define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 2110 #define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 2111 #define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 2112 #define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 2113 #define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 2120 #define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 2121 #define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 2122 #define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 2123 #define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 2130 #define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 2131 #define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 2132 #define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 2133 #define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 2140 #define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 2141 #define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 2142 #define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 2143 #define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 2150 #define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 2151 #define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 2152 #define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 2153 #define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 2160 #define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 2161 #define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 2162 #define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 2163 #define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 2170 #define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 2171 #define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 2172 #define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 2173 #define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 2180 #define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 2181 #define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 2182 #define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 2183 #define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 2190 #define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 2191 #define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 2192 #define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 2193 #define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 2200 #define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 2201 #define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 2202 #define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 2203 #define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 2210 #define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 2211 #define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 2212 #define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 2213 #define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 2220 #define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 2221 #define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 2222 #define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 2223 #define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 2230 #define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 2231 #define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 2232 #define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 2233 #define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 2240 #define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 2241 #define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 2242 #define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 2243 #define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 2250 #define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 2251 #define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 2252 #define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 2253 #define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 2260 #define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 2261 #define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 2262 #define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 2263 #define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 2270 #define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 2271 #define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 2272 #define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 2273 #define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 2280 #define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 2281 #define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 2282 #define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 2283 #define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 2290 #define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 2291 #define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 2292 #define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 2293 #define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 2300 #define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 2301 #define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 2302 #define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 2303 #define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 2310 #define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 2311 #define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 2312 #define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 2313 #define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 2320 #define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 2321 #define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 2322 #define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 2323 #define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 2330 #define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 2331 #define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 2332 #define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 2333 #define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 2340 #define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 2341 #define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 2342 #define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 2343 #define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 2355 #define CPU_SCS_NVIC_IABR1_ACTIVE37 0x00000020 2356 #define CPU_SCS_NVIC_IABR1_ACTIVE37_BITN 5 2357 #define CPU_SCS_NVIC_IABR1_ACTIVE37_M 0x00000020 2358 #define CPU_SCS_NVIC_IABR1_ACTIVE37_S 5 2365 #define CPU_SCS_NVIC_IABR1_ACTIVE36 0x00000010 2366 #define CPU_SCS_NVIC_IABR1_ACTIVE36_BITN 4 2367 #define CPU_SCS_NVIC_IABR1_ACTIVE36_M 0x00000010 2368 #define CPU_SCS_NVIC_IABR1_ACTIVE36_S 4 2375 #define CPU_SCS_NVIC_IABR1_ACTIVE35 0x00000008 2376 #define CPU_SCS_NVIC_IABR1_ACTIVE35_BITN 3 2377 #define CPU_SCS_NVIC_IABR1_ACTIVE35_M 0x00000008 2378 #define CPU_SCS_NVIC_IABR1_ACTIVE35_S 3 2385 #define CPU_SCS_NVIC_IABR1_ACTIVE34 0x00000004 2386 #define CPU_SCS_NVIC_IABR1_ACTIVE34_BITN 2 2387 #define CPU_SCS_NVIC_IABR1_ACTIVE34_M 0x00000004 2388 #define CPU_SCS_NVIC_IABR1_ACTIVE34_S 2 2395 #define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 2396 #define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 2397 #define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 2398 #define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 2405 #define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 2406 #define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 2407 #define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 2408 #define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 2418 #define CPU_SCS_NVIC_IPR0_PRI_3_W 8 2419 #define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 2420 #define CPU_SCS_NVIC_IPR0_PRI_3_S 24 2425 #define CPU_SCS_NVIC_IPR0_PRI_2_W 8 2426 #define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 2427 #define CPU_SCS_NVIC_IPR0_PRI_2_S 16 2432 #define CPU_SCS_NVIC_IPR0_PRI_1_W 8 2433 #define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 2434 #define CPU_SCS_NVIC_IPR0_PRI_1_S 8 2439 #define CPU_SCS_NVIC_IPR0_PRI_0_W 8 2440 #define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF 2441 #define CPU_SCS_NVIC_IPR0_PRI_0_S 0 2451 #define CPU_SCS_NVIC_IPR1_PRI_7_W 8 2452 #define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 2453 #define CPU_SCS_NVIC_IPR1_PRI_7_S 24 2458 #define CPU_SCS_NVIC_IPR1_PRI_6_W 8 2459 #define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 2460 #define CPU_SCS_NVIC_IPR1_PRI_6_S 16 2465 #define CPU_SCS_NVIC_IPR1_PRI_5_W 8 2466 #define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 2467 #define CPU_SCS_NVIC_IPR1_PRI_5_S 8 2472 #define CPU_SCS_NVIC_IPR1_PRI_4_W 8 2473 #define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF 2474 #define CPU_SCS_NVIC_IPR1_PRI_4_S 0 2484 #define CPU_SCS_NVIC_IPR2_PRI_11_W 8 2485 #define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 2486 #define CPU_SCS_NVIC_IPR2_PRI_11_S 24 2491 #define CPU_SCS_NVIC_IPR2_PRI_10_W 8 2492 #define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 2493 #define CPU_SCS_NVIC_IPR2_PRI_10_S 16 2498 #define CPU_SCS_NVIC_IPR2_PRI_9_W 8 2499 #define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 2500 #define CPU_SCS_NVIC_IPR2_PRI_9_S 8 2505 #define CPU_SCS_NVIC_IPR2_PRI_8_W 8 2506 #define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF 2507 #define CPU_SCS_NVIC_IPR2_PRI_8_S 0 2517 #define CPU_SCS_NVIC_IPR3_PRI_15_W 8 2518 #define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 2519 #define CPU_SCS_NVIC_IPR3_PRI_15_S 24 2524 #define CPU_SCS_NVIC_IPR3_PRI_14_W 8 2525 #define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 2526 #define CPU_SCS_NVIC_IPR3_PRI_14_S 16 2531 #define CPU_SCS_NVIC_IPR3_PRI_13_W 8 2532 #define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 2533 #define CPU_SCS_NVIC_IPR3_PRI_13_S 8 2538 #define CPU_SCS_NVIC_IPR3_PRI_12_W 8 2539 #define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF 2540 #define CPU_SCS_NVIC_IPR3_PRI_12_S 0 2550 #define CPU_SCS_NVIC_IPR4_PRI_19_W 8 2551 #define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 2552 #define CPU_SCS_NVIC_IPR4_PRI_19_S 24 2557 #define CPU_SCS_NVIC_IPR4_PRI_18_W 8 2558 #define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 2559 #define CPU_SCS_NVIC_IPR4_PRI_18_S 16 2564 #define CPU_SCS_NVIC_IPR4_PRI_17_W 8 2565 #define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 2566 #define CPU_SCS_NVIC_IPR4_PRI_17_S 8 2571 #define CPU_SCS_NVIC_IPR4_PRI_16_W 8 2572 #define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF 2573 #define CPU_SCS_NVIC_IPR4_PRI_16_S 0 2583 #define CPU_SCS_NVIC_IPR5_PRI_23_W 8 2584 #define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 2585 #define CPU_SCS_NVIC_IPR5_PRI_23_S 24 2590 #define CPU_SCS_NVIC_IPR5_PRI_22_W 8 2591 #define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 2592 #define CPU_SCS_NVIC_IPR5_PRI_22_S 16 2597 #define CPU_SCS_NVIC_IPR5_PRI_21_W 8 2598 #define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 2599 #define CPU_SCS_NVIC_IPR5_PRI_21_S 8 2604 #define CPU_SCS_NVIC_IPR5_PRI_20_W 8 2605 #define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF 2606 #define CPU_SCS_NVIC_IPR5_PRI_20_S 0 2616 #define CPU_SCS_NVIC_IPR6_PRI_27_W 8 2617 #define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 2618 #define CPU_SCS_NVIC_IPR6_PRI_27_S 24 2623 #define CPU_SCS_NVIC_IPR6_PRI_26_W 8 2624 #define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 2625 #define CPU_SCS_NVIC_IPR6_PRI_26_S 16 2630 #define CPU_SCS_NVIC_IPR6_PRI_25_W 8 2631 #define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 2632 #define CPU_SCS_NVIC_IPR6_PRI_25_S 8 2637 #define CPU_SCS_NVIC_IPR6_PRI_24_W 8 2638 #define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF 2639 #define CPU_SCS_NVIC_IPR6_PRI_24_S 0 2649 #define CPU_SCS_NVIC_IPR7_PRI_31_W 8 2650 #define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 2651 #define CPU_SCS_NVIC_IPR7_PRI_31_S 24 2656 #define CPU_SCS_NVIC_IPR7_PRI_30_W 8 2657 #define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 2658 #define CPU_SCS_NVIC_IPR7_PRI_30_S 16 2663 #define CPU_SCS_NVIC_IPR7_PRI_29_W 8 2664 #define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 2665 #define CPU_SCS_NVIC_IPR7_PRI_29_S 8 2670 #define CPU_SCS_NVIC_IPR7_PRI_28_W 8 2671 #define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF 2672 #define CPU_SCS_NVIC_IPR7_PRI_28_S 0 2682 #define CPU_SCS_NVIC_IPR8_PRI_35_W 8 2683 #define CPU_SCS_NVIC_IPR8_PRI_35_M 0xFF000000 2684 #define CPU_SCS_NVIC_IPR8_PRI_35_S 24 2689 #define CPU_SCS_NVIC_IPR8_PRI_34_W 8 2690 #define CPU_SCS_NVIC_IPR8_PRI_34_M 0x00FF0000 2691 #define CPU_SCS_NVIC_IPR8_PRI_34_S 16 2696 #define CPU_SCS_NVIC_IPR8_PRI_33_W 8 2697 #define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 2698 #define CPU_SCS_NVIC_IPR8_PRI_33_S 8 2703 #define CPU_SCS_NVIC_IPR8_PRI_32_W 8 2704 #define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF 2705 #define CPU_SCS_NVIC_IPR8_PRI_32_S 0 2715 #define CPU_SCS_NVIC_IPR9_PRI_37_W 8 2716 #define CPU_SCS_NVIC_IPR9_PRI_37_M 0x0000FF00 2717 #define CPU_SCS_NVIC_IPR9_PRI_37_S 8 2722 #define CPU_SCS_NVIC_IPR9_PRI_36_W 8 2723 #define CPU_SCS_NVIC_IPR9_PRI_36_M 0x000000FF 2724 #define CPU_SCS_NVIC_IPR9_PRI_36_S 0 2734 #define CPU_SCS_CPUID_IMPLEMENTER_W 8 2735 #define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 2736 #define CPU_SCS_CPUID_IMPLEMENTER_S 24 2741 #define CPU_SCS_CPUID_VARIANT_W 4 2742 #define CPU_SCS_CPUID_VARIANT_M 0x00F00000 2743 #define CPU_SCS_CPUID_VARIANT_S 20 2748 #define CPU_SCS_CPUID_CONSTANT_W 4 2749 #define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 2750 #define CPU_SCS_CPUID_CONSTANT_S 16 2755 #define CPU_SCS_CPUID_PARTNO_W 12 2756 #define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 2757 #define CPU_SCS_CPUID_PARTNO_S 4 2762 #define CPU_SCS_CPUID_REVISION_W 4 2763 #define CPU_SCS_CPUID_REVISION_M 0x0000000F 2764 #define CPU_SCS_CPUID_REVISION_S 0 2779 #define CPU_SCS_ICSR_NMIPENDSET 0x80000000 2780 #define CPU_SCS_ICSR_NMIPENDSET_BITN 31 2781 #define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 2782 #define CPU_SCS_ICSR_NMIPENDSET_S 31 2790 #define CPU_SCS_ICSR_PENDSVSET 0x10000000 2791 #define CPU_SCS_ICSR_PENDSVSET_BITN 28 2792 #define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 2793 #define CPU_SCS_ICSR_PENDSVSET_S 28 2801 #define CPU_SCS_ICSR_PENDSVCLR 0x08000000 2802 #define CPU_SCS_ICSR_PENDSVCLR_BITN 27 2803 #define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 2804 #define CPU_SCS_ICSR_PENDSVCLR_S 27 2812 #define CPU_SCS_ICSR_PENDSTSET 0x04000000 2813 #define CPU_SCS_ICSR_PENDSTSET_BITN 26 2814 #define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 2815 #define CPU_SCS_ICSR_PENDSTSET_S 26 2823 #define CPU_SCS_ICSR_PENDSTCLR 0x02000000 2824 #define CPU_SCS_ICSR_PENDSTCLR_BITN 25 2825 #define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 2826 #define CPU_SCS_ICSR_PENDSTCLR_S 25 2836 #define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 2837 #define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 2838 #define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 2839 #define CPU_SCS_ICSR_ISRPREEMPT_S 23 2847 #define CPU_SCS_ICSR_ISRPENDING 0x00400000 2848 #define CPU_SCS_ICSR_ISRPENDING_BITN 22 2849 #define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 2850 #define CPU_SCS_ICSR_ISRPENDING_S 22 2856 #define CPU_SCS_ICSR_VECTPENDING_W 6 2857 #define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 2858 #define CPU_SCS_ICSR_VECTPENDING_S 12 2867 #define CPU_SCS_ICSR_RETTOBASE 0x00000800 2868 #define CPU_SCS_ICSR_RETTOBASE_BITN 11 2869 #define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 2870 #define CPU_SCS_ICSR_RETTOBASE_S 11 2875 #define CPU_SCS_ICSR_VECTACTIVE_W 9 2876 #define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF 2877 #define CPU_SCS_ICSR_VECTACTIVE_S 0 2887 #define CPU_SCS_VTOR_TBLOFF_W 23 2888 #define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 2889 #define CPU_SCS_VTOR_TBLOFF_S 7 2900 #define CPU_SCS_AIRCR_VECTKEY_W 16 2901 #define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 2902 #define CPU_SCS_AIRCR_VECTKEY_S 16 2910 #define CPU_SCS_AIRCR_ENDIANESS 0x00008000 2911 #define CPU_SCS_AIRCR_ENDIANESS_BITN 15 2912 #define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 2913 #define CPU_SCS_AIRCR_ENDIANESS_S 15 2914 #define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 2915 #define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 2927 #define CPU_SCS_AIRCR_PRIGROUP_W 3 2928 #define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 2929 #define CPU_SCS_AIRCR_PRIGROUP_S 8 2935 #define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 2936 #define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 2937 #define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 2938 #define CPU_SCS_AIRCR_SYSRESETREQ_S 2 2948 #define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 2949 #define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 2950 #define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 2951 #define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 2959 #define CPU_SCS_AIRCR_VECTRESET 0x00000001 2960 #define CPU_SCS_AIRCR_VECTRESET_BITN 0 2961 #define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 2962 #define CPU_SCS_AIRCR_VECTRESET_S 0 2983 #define CPU_SCS_SCR_SEVONPEND 0x00000010 2984 #define CPU_SCS_SCR_SEVONPEND_BITN 4 2985 #define CPU_SCS_SCR_SEVONPEND_M 0x00000010 2986 #define CPU_SCS_SCR_SEVONPEND_S 4 2995 #define CPU_SCS_SCR_SLEEPDEEP 0x00000004 2996 #define CPU_SCS_SCR_SLEEPDEEP_BITN 2 2997 #define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 2998 #define CPU_SCS_SCR_SLEEPDEEP_S 2 2999 #define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 3000 #define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 3009 #define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 3010 #define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 3011 #define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 3012 #define CPU_SCS_SCR_SLEEPONEXIT_S 1 3028 #define CPU_SCS_CCR_STKALIGN 0x00000200 3029 #define CPU_SCS_CCR_STKALIGN_BITN 9 3030 #define CPU_SCS_CCR_STKALIGN_M 0x00000200 3031 #define CPU_SCS_CCR_STKALIGN_S 9 3045 #define CPU_SCS_CCR_BFHFNMIGN 0x00000100 3046 #define CPU_SCS_CCR_BFHFNMIGN_BITN 8 3047 #define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 3048 #define CPU_SCS_CCR_BFHFNMIGN_S 8 3059 #define CPU_SCS_CCR_DIV_0_TRP 0x00000010 3060 #define CPU_SCS_CCR_DIV_0_TRP_BITN 4 3061 #define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 3062 #define CPU_SCS_CCR_DIV_0_TRP_S 4 3075 #define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 3076 #define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 3077 #define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 3078 #define CPU_SCS_CCR_UNALIGN_TRP_S 3 3089 #define CPU_SCS_CCR_USERSETMPEND 0x00000002 3090 #define CPU_SCS_CCR_USERSETMPEND_BITN 1 3091 #define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 3092 #define CPU_SCS_CCR_USERSETMPEND_S 1 3109 #define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 3110 #define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 3111 #define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 3112 #define CPU_SCS_CCR_NONBASETHREDENA_S 0 3122 #define CPU_SCS_SHPR1_PRI_6_W 8 3123 #define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 3124 #define CPU_SCS_SHPR1_PRI_6_S 16 3129 #define CPU_SCS_SHPR1_PRI_5_W 8 3130 #define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 3131 #define CPU_SCS_SHPR1_PRI_5_S 8 3136 #define CPU_SCS_SHPR1_PRI_4_W 8 3137 #define CPU_SCS_SHPR1_PRI_4_M 0x000000FF 3138 #define CPU_SCS_SHPR1_PRI_4_S 0 3148 #define CPU_SCS_SHPR2_PRI_11_W 8 3149 #define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 3150 #define CPU_SCS_SHPR2_PRI_11_S 24 3160 #define CPU_SCS_SHPR3_PRI_15_W 8 3161 #define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 3162 #define CPU_SCS_SHPR3_PRI_15_S 24 3167 #define CPU_SCS_SHPR3_PRI_14_W 8 3168 #define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 3169 #define CPU_SCS_SHPR3_PRI_14_S 16 3174 #define CPU_SCS_SHPR3_PRI_12_W 8 3175 #define CPU_SCS_SHPR3_PRI_12_M 0x000000FF 3176 #define CPU_SCS_SHPR3_PRI_12_S 0 3189 #define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 3190 #define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 3191 #define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 3192 #define CPU_SCS_SHCSR_USGFAULTENA_S 18 3193 #define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 3194 #define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 3202 #define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 3203 #define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 3204 #define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 3205 #define CPU_SCS_SHCSR_BUSFAULTENA_S 17 3206 #define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 3207 #define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 3215 #define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 3216 #define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 3217 #define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 3218 #define CPU_SCS_SHCSR_MEMFAULTENA_S 16 3219 #define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 3220 #define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 3228 #define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 3229 #define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 3230 #define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 3231 #define CPU_SCS_SHCSR_SVCALLPENDED_S 15 3232 #define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 3233 #define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 3241 #define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 3242 #define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 3243 #define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 3244 #define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 3245 #define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 3246 #define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 3254 #define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 3255 #define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 3256 #define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 3257 #define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 3258 #define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 3259 #define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 3267 #define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 3268 #define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 3269 #define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 3270 #define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 3271 #define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 3272 #define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 3283 #define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 3284 #define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 3285 #define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 3286 #define CPU_SCS_SHCSR_SYSTICKACT_S 11 3287 #define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 3288 #define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 3296 #define CPU_SCS_SHCSR_PENDSVACT 0x00000400 3297 #define CPU_SCS_SHCSR_PENDSVACT_BITN 10 3298 #define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 3299 #define CPU_SCS_SHCSR_PENDSVACT_S 10 3307 #define CPU_SCS_SHCSR_MONITORACT 0x00000100 3308 #define CPU_SCS_SHCSR_MONITORACT_BITN 8 3309 #define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 3310 #define CPU_SCS_SHCSR_MONITORACT_S 8 3311 #define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 3312 #define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 3320 #define CPU_SCS_SHCSR_SVCALLACT 0x00000080 3321 #define CPU_SCS_SHCSR_SVCALLACT_BITN 7 3322 #define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 3323 #define CPU_SCS_SHCSR_SVCALLACT_S 7 3324 #define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 3325 #define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 3333 #define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 3334 #define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 3335 #define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 3336 #define CPU_SCS_SHCSR_USGFAULTACT_S 3 3337 #define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 3338 #define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 3346 #define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 3347 #define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 3348 #define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 3349 #define CPU_SCS_SHCSR_BUSFAULTACT_S 1 3350 #define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 3351 #define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 3359 #define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 3360 #define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 3361 #define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 3362 #define CPU_SCS_SHCSR_MEMFAULTACT_S 0 3363 #define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 3364 #define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 3377 #define CPU_SCS_CFSR_DIVBYZERO 0x02000000 3378 #define CPU_SCS_CFSR_DIVBYZERO_BITN 25 3379 #define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 3380 #define CPU_SCS_CFSR_DIVBYZERO_S 25 3387 #define CPU_SCS_CFSR_UNALIGNED 0x01000000 3388 #define CPU_SCS_CFSR_UNALIGNED_BITN 24 3389 #define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 3390 #define CPU_SCS_CFSR_UNALIGNED_S 24 3396 #define CPU_SCS_CFSR_NOCP 0x00080000 3397 #define CPU_SCS_CFSR_NOCP_BITN 19 3398 #define CPU_SCS_CFSR_NOCP_M 0x00080000 3399 #define CPU_SCS_CFSR_NOCP_S 19 3406 #define CPU_SCS_CFSR_INVPC 0x00040000 3407 #define CPU_SCS_CFSR_INVPC_BITN 18 3408 #define CPU_SCS_CFSR_INVPC_M 0x00040000 3409 #define CPU_SCS_CFSR_INVPC_S 18 3417 #define CPU_SCS_CFSR_INVSTATE 0x00020000 3418 #define CPU_SCS_CFSR_INVSTATE_BITN 17 3419 #define CPU_SCS_CFSR_INVSTATE_M 0x00020000 3420 #define CPU_SCS_CFSR_INVSTATE_S 17 3427 #define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 3428 #define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 3429 #define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 3430 #define CPU_SCS_CFSR_UNDEFINSTR_S 16 3440 #define CPU_SCS_CFSR_BFARVALID 0x00008000 3441 #define CPU_SCS_CFSR_BFARVALID_BITN 15 3442 #define CPU_SCS_CFSR_BFARVALID_M 0x00008000 3443 #define CPU_SCS_CFSR_BFARVALID_S 15 3450 #define CPU_SCS_CFSR_STKERR 0x00001000 3451 #define CPU_SCS_CFSR_STKERR_BITN 12 3452 #define CPU_SCS_CFSR_STKERR_M 0x00001000 3453 #define CPU_SCS_CFSR_STKERR_S 12 3461 #define CPU_SCS_CFSR_UNSTKERR 0x00000800 3462 #define CPU_SCS_CFSR_UNSTKERR_BITN 11 3463 #define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 3464 #define CPU_SCS_CFSR_UNSTKERR_S 11 3475 #define CPU_SCS_CFSR_IMPRECISERR 0x00000400 3476 #define CPU_SCS_CFSR_IMPRECISERR_BITN 10 3477 #define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 3478 #define CPU_SCS_CFSR_IMPRECISERR_S 10 3483 #define CPU_SCS_CFSR_PRECISERR 0x00000200 3484 #define CPU_SCS_CFSR_PRECISERR_BITN 9 3485 #define CPU_SCS_CFSR_PRECISERR_M 0x00000200 3486 #define CPU_SCS_CFSR_PRECISERR_S 9 3493 #define CPU_SCS_CFSR_IBUSERR 0x00000100 3494 #define CPU_SCS_CFSR_IBUSERR_BITN 8 3495 #define CPU_SCS_CFSR_IBUSERR_M 0x00000100 3496 #define CPU_SCS_CFSR_IBUSERR_S 8 3505 #define CPU_SCS_CFSR_MMARVALID 0x00000080 3506 #define CPU_SCS_CFSR_MMARVALID_BITN 7 3507 #define CPU_SCS_CFSR_MMARVALID_M 0x00000080 3508 #define CPU_SCS_CFSR_MMARVALID_S 7 3515 #define CPU_SCS_CFSR_MSTKERR 0x00000010 3516 #define CPU_SCS_CFSR_MSTKERR_BITN 4 3517 #define CPU_SCS_CFSR_MSTKERR_M 0x00000010 3518 #define CPU_SCS_CFSR_MSTKERR_S 4 3526 #define CPU_SCS_CFSR_MUNSTKERR 0x00000008 3527 #define CPU_SCS_CFSR_MUNSTKERR_BITN 3 3528 #define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 3529 #define CPU_SCS_CFSR_MUNSTKERR_S 3 3537 #define CPU_SCS_CFSR_DACCVIOL 0x00000002 3538 #define CPU_SCS_CFSR_DACCVIOL_BITN 1 3539 #define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 3540 #define CPU_SCS_CFSR_DACCVIOL_S 1 3548 #define CPU_SCS_CFSR_IACCVIOL 0x00000001 3549 #define CPU_SCS_CFSR_IACCVIOL_BITN 0 3550 #define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 3551 #define CPU_SCS_CFSR_IACCVIOL_S 0 3566 #define CPU_SCS_HFSR_DEBUGEVT 0x80000000 3567 #define CPU_SCS_HFSR_DEBUGEVT_BITN 31 3568 #define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 3569 #define CPU_SCS_HFSR_DEBUGEVT_S 31 3577 #define CPU_SCS_HFSR_FORCED 0x40000000 3578 #define CPU_SCS_HFSR_FORCED_BITN 30 3579 #define CPU_SCS_HFSR_FORCED_M 0x40000000 3580 #define CPU_SCS_HFSR_FORCED_S 30 3587 #define CPU_SCS_HFSR_VECTTBL 0x00000002 3588 #define CPU_SCS_HFSR_VECTTBL_BITN 1 3589 #define CPU_SCS_HFSR_VECTTBL_M 0x00000002 3590 #define CPU_SCS_HFSR_VECTTBL_S 1 3604 #define CPU_SCS_DFSR_EXTERNAL 0x00000010 3605 #define CPU_SCS_DFSR_EXTERNAL_BITN 4 3606 #define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 3607 #define CPU_SCS_DFSR_EXTERNAL_S 4 3616 #define CPU_SCS_DFSR_VCATCH 0x00000008 3617 #define CPU_SCS_DFSR_VCATCH_BITN 3 3618 #define CPU_SCS_DFSR_VCATCH_M 0x00000008 3619 #define CPU_SCS_DFSR_VCATCH_S 3 3628 #define CPU_SCS_DFSR_DWTTRAP 0x00000004 3629 #define CPU_SCS_DFSR_DWTTRAP_BITN 2 3630 #define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 3631 #define CPU_SCS_DFSR_DWTTRAP_S 2 3641 #define CPU_SCS_DFSR_BKPT 0x00000002 3642 #define CPU_SCS_DFSR_BKPT_BITN 1 3643 #define CPU_SCS_DFSR_BKPT_M 0x00000002 3644 #define CPU_SCS_DFSR_BKPT_S 1 3652 #define CPU_SCS_DFSR_HALTED 0x00000001 3653 #define CPU_SCS_DFSR_HALTED_BITN 0 3654 #define CPU_SCS_DFSR_HALTED_M 0x00000001 3655 #define CPU_SCS_DFSR_HALTED_S 0 3671 #define CPU_SCS_MMFAR_ADDRESS_W 32 3672 #define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF 3673 #define CPU_SCS_MMFAR_ADDRESS_S 0 3688 #define CPU_SCS_BFAR_ADDRESS_W 32 3689 #define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF 3690 #define CPU_SCS_BFAR_ADDRESS_S 0 3701 #define CPU_SCS_AFSR_IMPDEF_W 32 3702 #define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF 3703 #define CPU_SCS_AFSR_IMPDEF_S 0 3721 #define CPU_SCS_ID_PFR0_STATE1_W 4 3722 #define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 3723 #define CPU_SCS_ID_PFR0_STATE1_S 4 3731 #define CPU_SCS_ID_PFR0_STATE0_W 4 3732 #define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F 3733 #define CPU_SCS_ID_PFR0_STATE0_S 0 3746 #define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 3747 #define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 3748 #define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 3761 #define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 3762 #define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 3763 #define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 3791 #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 3792 #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 3793 #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 3794 #define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 3839 #define CPU_SCS_MPU_TYPE_IREGION_W 8 3840 #define CPU_SCS_MPU_TYPE_IREGION_M 0x00FF0000 3841 #define CPU_SCS_MPU_TYPE_IREGION_S 16 3847 #define CPU_SCS_MPU_TYPE_DREGION_W 8 3848 #define CPU_SCS_MPU_TYPE_DREGION_M 0x0000FF00 3849 #define CPU_SCS_MPU_TYPE_DREGION_S 8 3854 #define CPU_SCS_MPU_TYPE_SEPARATE 0x00000001 3855 #define CPU_SCS_MPU_TYPE_SEPARATE_BITN 0 3856 #define CPU_SCS_MPU_TYPE_SEPARATE_M 0x00000001 3857 #define CPU_SCS_MPU_TYPE_SEPARATE_S 0 3877 #define CPU_SCS_MPU_CTRL_PRIVDEFENA 0x00000004 3878 #define CPU_SCS_MPU_CTRL_PRIVDEFENA_BITN 2 3879 #define CPU_SCS_MPU_CTRL_PRIVDEFENA_M 0x00000004 3880 #define CPU_SCS_MPU_CTRL_PRIVDEFENA_S 2 3889 #define CPU_SCS_MPU_CTRL_HFNMIENA 0x00000002 3890 #define CPU_SCS_MPU_CTRL_HFNMIENA_BITN 1 3891 #define CPU_SCS_MPU_CTRL_HFNMIENA_M 0x00000002 3892 #define CPU_SCS_MPU_CTRL_HFNMIENA_S 1 3900 #define CPU_SCS_MPU_CTRL_ENABLE 0x00000001 3901 #define CPU_SCS_MPU_CTRL_ENABLE_BITN 0 3902 #define CPU_SCS_MPU_CTRL_ENABLE_M 0x00000001 3903 #define CPU_SCS_MPU_CTRL_ENABLE_S 0 3916 #define CPU_SCS_MPU_RNR_REGION_W 8 3917 #define CPU_SCS_MPU_RNR_REGION_M 0x000000FF 3918 #define CPU_SCS_MPU_RNR_REGION_S 0 3932 #define CPU_SCS_MPU_RBAR_ADDR_W 27 3933 #define CPU_SCS_MPU_RBAR_ADDR_M 0xFFFFFFE0 3934 #define CPU_SCS_MPU_RBAR_ADDR_S 5 3941 #define CPU_SCS_MPU_RBAR_VALID 0x00000010 3942 #define CPU_SCS_MPU_RBAR_VALID_BITN 4 3943 #define CPU_SCS_MPU_RBAR_VALID_M 0x00000010 3944 #define CPU_SCS_MPU_RBAR_VALID_S 4 3949 #define CPU_SCS_MPU_RBAR_REGION_W 4 3950 #define CPU_SCS_MPU_RBAR_REGION_M 0x0000000F 3951 #define CPU_SCS_MPU_RBAR_REGION_S 0 3963 #define CPU_SCS_MPU_RASR_XN 0x10000000 3964 #define CPU_SCS_MPU_RASR_XN_BITN 28 3965 #define CPU_SCS_MPU_RASR_XN_M 0x10000000 3966 #define CPU_SCS_MPU_RASR_XN_S 28 3979 #define CPU_SCS_MPU_RASR_AP_W 3 3980 #define CPU_SCS_MPU_RASR_AP_M 0x07000000 3981 #define CPU_SCS_MPU_RASR_AP_S 24 3986 #define CPU_SCS_MPU_RASR_TEX_W 3 3987 #define CPU_SCS_MPU_RASR_TEX_M 0x00380000 3988 #define CPU_SCS_MPU_RASR_TEX_S 19 3995 #define CPU_SCS_MPU_RASR_S 0x00040000 3996 #define CPU_SCS_MPU_RASR_S_BITN 18 3997 #define CPU_SCS_MPU_RASR_S_M 0x00040000 3998 #define CPU_SCS_MPU_RASR_S_S 18 4005 #define CPU_SCS_MPU_RASR_C 0x00020000 4006 #define CPU_SCS_MPU_RASR_C_BITN 17 4007 #define CPU_SCS_MPU_RASR_C_M 0x00020000 4008 #define CPU_SCS_MPU_RASR_C_S 17 4015 #define CPU_SCS_MPU_RASR_B 0x00010000 4016 #define CPU_SCS_MPU_RASR_B_BITN 16 4017 #define CPU_SCS_MPU_RASR_B_M 0x00010000 4018 #define CPU_SCS_MPU_RASR_B_S 16 4026 #define CPU_SCS_MPU_RASR_SRD_W 8 4027 #define CPU_SCS_MPU_RASR_SRD_M 0x0000FF00 4028 #define CPU_SCS_MPU_RASR_SRD_S 8 4061 #define CPU_SCS_MPU_RASR_SIZE_W 5 4062 #define CPU_SCS_MPU_RASR_SIZE_M 0x0000003E 4063 #define CPU_SCS_MPU_RASR_SIZE_S 1 4070 #define CPU_SCS_MPU_RASR_ENABLE 0x00000001 4071 #define CPU_SCS_MPU_RASR_ENABLE_BITN 0 4072 #define CPU_SCS_MPU_RASR_ENABLE_M 0x00000001 4073 #define CPU_SCS_MPU_RASR_ENABLE_S 0 4083 #define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_W 32 4084 #define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_M 0xFFFFFFFF 4085 #define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_S 0 4095 #define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_W 32 4096 #define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_M 0xFFFFFFFF 4097 #define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_S 0 4107 #define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_W 32 4108 #define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_M 0xFFFFFFFF 4109 #define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_S 0 4119 #define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_W 32 4120 #define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_M 0xFFFFFFFF 4121 #define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_S 0 4131 #define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_W 32 4132 #define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_M 0xFFFFFFFF 4133 #define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_S 0 4143 #define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_W 32 4144 #define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_M 0xFFFFFFFF 4145 #define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_S 0 4161 #define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 4162 #define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 4163 #define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 4164 #define CPU_SCS_DHCSR_S_RESET_ST_S 25 4173 #define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 4174 #define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 4175 #define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 4176 #define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 4184 #define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 4185 #define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 4186 #define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 4187 #define CPU_SCS_DHCSR_S_LOCKUP_S 19 4195 #define CPU_SCS_DHCSR_S_SLEEP 0x00040000 4196 #define CPU_SCS_DHCSR_S_SLEEP_BITN 18 4197 #define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 4198 #define CPU_SCS_DHCSR_S_SLEEP_S 18 4205 #define CPU_SCS_DHCSR_S_HALT 0x00020000 4206 #define CPU_SCS_DHCSR_S_HALT_BITN 17 4207 #define CPU_SCS_DHCSR_S_HALT_M 0x00020000 4208 #define CPU_SCS_DHCSR_S_HALT_S 17 4216 #define CPU_SCS_DHCSR_S_REGRDY 0x00010000 4217 #define CPU_SCS_DHCSR_S_REGRDY_BITN 16 4218 #define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 4219 #define CPU_SCS_DHCSR_S_REGRDY_S 16 4229 #define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 4230 #define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 4231 #define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 4232 #define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 4244 #define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 4245 #define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 4246 #define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 4247 #define CPU_SCS_DHCSR_C_MASKINTS_S 3 4255 #define CPU_SCS_DHCSR_C_STEP 0x00000004 4256 #define CPU_SCS_DHCSR_C_STEP_BITN 2 4257 #define CPU_SCS_DHCSR_C_STEP_M 0x00000004 4258 #define CPU_SCS_DHCSR_C_STEP_S 2 4264 #define CPU_SCS_DHCSR_C_HALT 0x00000002 4265 #define CPU_SCS_DHCSR_C_HALT_BITN 1 4266 #define CPU_SCS_DHCSR_C_HALT_M 0x00000002 4267 #define CPU_SCS_DHCSR_C_HALT_S 1 4277 #define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 4278 #define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 4279 #define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 4280 #define CPU_SCS_DHCSR_C_DEBUGEN_S 0 4291 #define CPU_SCS_DCRSR_REGWNR 0x00010000 4292 #define CPU_SCS_DCRSR_REGWNR_BITN 16 4293 #define CPU_SCS_DCRSR_REGWNR_M 0x00010000 4294 #define CPU_SCS_DCRSR_REGWNR_S 16 4320 #define CPU_SCS_DCRSR_REGSEL_W 5 4321 #define CPU_SCS_DCRSR_REGSEL_M 0x0000001F 4322 #define CPU_SCS_DCRSR_REGSEL_S 0 4339 #define CPU_SCS_DCRDR_DCRDR_W 32 4340 #define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF 4341 #define CPU_SCS_DCRDR_DCRDR_S 0 4354 #define CPU_SCS_DEMCR_TRCENA 0x01000000 4355 #define CPU_SCS_DEMCR_TRCENA_BITN 24 4356 #define CPU_SCS_DEMCR_TRCENA_M 0x01000000 4357 #define CPU_SCS_DEMCR_TRCENA_S 24 4366 #define CPU_SCS_DEMCR_MON_REQ 0x00080000 4367 #define CPU_SCS_DEMCR_MON_REQ_BITN 19 4368 #define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 4369 #define CPU_SCS_DEMCR_MON_REQ_S 19 4377 #define CPU_SCS_DEMCR_MON_STEP 0x00040000 4378 #define CPU_SCS_DEMCR_MON_STEP_BITN 18 4379 #define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 4380 #define CPU_SCS_DEMCR_MON_STEP_S 18 4389 #define CPU_SCS_DEMCR_MON_PEND 0x00020000 4390 #define CPU_SCS_DEMCR_MON_PEND_BITN 17 4391 #define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 4392 #define CPU_SCS_DEMCR_MON_PEND_S 17 4409 #define CPU_SCS_DEMCR_MON_EN 0x00010000 4410 #define CPU_SCS_DEMCR_MON_EN_BITN 16 4411 #define CPU_SCS_DEMCR_MON_EN_M 0x00010000 4412 #define CPU_SCS_DEMCR_MON_EN_S 16 4417 #define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 4418 #define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 4419 #define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 4420 #define CPU_SCS_DEMCR_VC_HARDERR_S 10 4426 #define CPU_SCS_DEMCR_VC_INTERR 0x00000200 4427 #define CPU_SCS_DEMCR_VC_INTERR_BITN 9 4428 #define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 4429 #define CPU_SCS_DEMCR_VC_INTERR_S 9 4434 #define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 4435 #define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 4436 #define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 4437 #define CPU_SCS_DEMCR_VC_BUSERR_S 8 4443 #define CPU_SCS_DEMCR_VC_STATERR 0x00000080 4444 #define CPU_SCS_DEMCR_VC_STATERR_BITN 7 4445 #define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 4446 #define CPU_SCS_DEMCR_VC_STATERR_S 7 4452 #define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 4453 #define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 4454 #define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 4455 #define CPU_SCS_DEMCR_VC_CHKERR_S 6 4461 #define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 4462 #define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 4463 #define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 4464 #define CPU_SCS_DEMCR_VC_NOCPERR_S 5 4470 #define CPU_SCS_DEMCR_VC_MMERR 0x00000010 4471 #define CPU_SCS_DEMCR_VC_MMERR_BITN 4 4472 #define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 4473 #define CPU_SCS_DEMCR_VC_MMERR_S 4 4479 #define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 4480 #define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 4481 #define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 4482 #define CPU_SCS_DEMCR_VC_CORERESET_S 0 4494 #define CPU_SCS_STIR_INTID_W 9 4495 #define CPU_SCS_STIR_INTID_M 0x000001FF 4496 #define CPU_SCS_STIR_INTID_S 0 4510 #define CPU_SCS_FPCCR_ASPEN 0x80000000 4511 #define CPU_SCS_FPCCR_ASPEN_BITN 31 4512 #define CPU_SCS_FPCCR_ASPEN_M 0x80000000 4513 #define CPU_SCS_FPCCR_ASPEN_S 31 4523 #define CPU_SCS_FPCCR_LSPEN 0x40000000 4524 #define CPU_SCS_FPCCR_LSPEN_BITN 30 4525 #define CPU_SCS_FPCCR_LSPEN_M 0x40000000 4526 #define CPU_SCS_FPCCR_LSPEN_S 30 4536 #define CPU_SCS_FPCCR_MONRDY 0x00000100 4537 #define CPU_SCS_FPCCR_MONRDY_BITN 8 4538 #define CPU_SCS_FPCCR_MONRDY_M 0x00000100 4539 #define CPU_SCS_FPCCR_MONRDY_S 8 4550 #define CPU_SCS_FPCCR_BFRDY 0x00000040 4551 #define CPU_SCS_FPCCR_BFRDY_BITN 6 4552 #define CPU_SCS_FPCCR_BFRDY_M 0x00000040 4553 #define CPU_SCS_FPCCR_BFRDY_S 6 4564 #define CPU_SCS_FPCCR_MMRDY 0x00000020 4565 #define CPU_SCS_FPCCR_MMRDY_BITN 5 4566 #define CPU_SCS_FPCCR_MMRDY_M 0x00000020 4567 #define CPU_SCS_FPCCR_MMRDY_S 5 4577 #define CPU_SCS_FPCCR_HFRDY 0x00000010 4578 #define CPU_SCS_FPCCR_HFRDY_BITN 4 4579 #define CPU_SCS_FPCCR_HFRDY_M 0x00000010 4580 #define CPU_SCS_FPCCR_HFRDY_S 4 4589 #define CPU_SCS_FPCCR_THREAD 0x00000008 4590 #define CPU_SCS_FPCCR_THREAD_BITN 3 4591 #define CPU_SCS_FPCCR_THREAD_M 0x00000008 4592 #define CPU_SCS_FPCCR_THREAD_S 3 4602 #define CPU_SCS_FPCCR_USER 0x00000002 4603 #define CPU_SCS_FPCCR_USER_BITN 1 4604 #define CPU_SCS_FPCCR_USER_M 0x00000002 4605 #define CPU_SCS_FPCCR_USER_S 1 4613 #define CPU_SCS_FPCCR_LSPACT 0x00000001 4614 #define CPU_SCS_FPCCR_LSPACT_BITN 0 4615 #define CPU_SCS_FPCCR_LSPACT_M 0x00000001 4616 #define CPU_SCS_FPCCR_LSPACT_S 0 4627 #define CPU_SCS_FPCAR_ADDRESS_W 30 4628 #define CPU_SCS_FPCAR_ADDRESS_M 0xFFFFFFFC 4629 #define CPU_SCS_FPCAR_ADDRESS_S 2 4640 #define CPU_SCS_FPDSCR_AHP 0x04000000 4641 #define CPU_SCS_FPDSCR_AHP_BITN 26 4642 #define CPU_SCS_FPDSCR_AHP_M 0x04000000 4643 #define CPU_SCS_FPDSCR_AHP_S 26 4649 #define CPU_SCS_FPDSCR_DN 0x02000000 4650 #define CPU_SCS_FPDSCR_DN_BITN 25 4651 #define CPU_SCS_FPDSCR_DN_M 0x02000000 4652 #define CPU_SCS_FPDSCR_DN_S 25 4658 #define CPU_SCS_FPDSCR_FZ 0x01000000 4659 #define CPU_SCS_FPDSCR_FZ_BITN 24 4660 #define CPU_SCS_FPDSCR_FZ_M 0x01000000 4661 #define CPU_SCS_FPDSCR_FZ_S 24 4673 #define CPU_SCS_FPDSCR_RMODE_W 2 4674 #define CPU_SCS_FPDSCR_RMODE_M 0x00C00000 4675 #define CPU_SCS_FPDSCR_RMODE_S 22 4686 #define CPU_SCS_MVFR0_FP_ROUNDING_MODES_W 4 4687 #define CPU_SCS_MVFR0_FP_ROUNDING_MODES_M 0xF0000000 4688 #define CPU_SCS_MVFR0_FP_ROUNDING_MODES_S 28 4694 #define CPU_SCS_MVFR0_SHORT_VECTORS_W 4 4695 #define CPU_SCS_MVFR0_SHORT_VECTORS_M 0x0F000000 4696 #define CPU_SCS_MVFR0_SHORT_VECTORS_S 24 4702 #define CPU_SCS_MVFR0_SQUARE_ROOT_W 4 4703 #define CPU_SCS_MVFR0_SQUARE_ROOT_M 0x00F00000 4704 #define CPU_SCS_MVFR0_SQUARE_ROOT_S 20 4710 #define CPU_SCS_MVFR0_DIVIDE_W 4 4711 #define CPU_SCS_MVFR0_DIVIDE_M 0x000F0000 4712 #define CPU_SCS_MVFR0_DIVIDE_S 16 4718 #define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_W 4 4719 #define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_M 0x0000F000 4720 #define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_S 12 4726 #define CPU_SCS_MVFR0_DOUBLE_PRECISION_W 4 4727 #define CPU_SCS_MVFR0_DOUBLE_PRECISION_M 0x00000F00 4728 #define CPU_SCS_MVFR0_DOUBLE_PRECISION_S 8 4734 #define CPU_SCS_MVFR0_SINGLE_PRECISION_W 4 4735 #define CPU_SCS_MVFR0_SINGLE_PRECISION_M 0x000000F0 4736 #define CPU_SCS_MVFR0_SINGLE_PRECISION_S 4 4742 #define CPU_SCS_MVFR0_A_SIMD_W 4 4743 #define CPU_SCS_MVFR0_A_SIMD_M 0x0000000F 4744 #define CPU_SCS_MVFR0_A_SIMD_S 0 4755 #define CPU_SCS_MVFR1_FP_FUSED_MAC_W 4 4756 #define CPU_SCS_MVFR1_FP_FUSED_MAC_M 0xF0000000 4757 #define CPU_SCS_MVFR1_FP_FUSED_MAC_S 28 4763 #define CPU_SCS_MVFR1_FP_HPFP_W 4 4764 #define CPU_SCS_MVFR1_FP_HPFP_M 0x0F000000 4765 #define CPU_SCS_MVFR1_FP_HPFP_S 24 4772 #define CPU_SCS_MVFR1_D_NAN_MODE_W 4 4773 #define CPU_SCS_MVFR1_D_NAN_MODE_M 0x000000F0 4774 #define CPU_SCS_MVFR1_D_NAN_MODE_S 4 4781 #define CPU_SCS_MVFR1_FTZ_MODE_W 4 4782 #define CPU_SCS_MVFR1_FTZ_MODE_M 0x0000000F 4783 #define CPU_SCS_MVFR1_FTZ_MODE_S 0 4786 #endif // __CPU_SCS__
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