TI Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3200:1

Tool Chain Version: 18.12.3

BIOS Version: bios_6_80_00_08_eng

XDCTools Version: xdctools_3_60_00_24_core

Benchmark	Cycles
Interrupt Latency	127
Hwi_restore()	10
Hwi_disable()	14
Hwi dispatcher prolog	118
Hwi dispatcher epilog	235
Hwi dispatcher	346
Hardware Interrupt to Blocked Task	566
Hardware Interrupt to Software Interrupt	398
Swi_enable()	81
Swi_disable()	16
Post Software Interrupt Again	40
Post Software Interrupt without Context Switch	109
Post Software Interrupt with Context Switch	224
Create a New Task without Context Switch	2791
Set a Task Priority without a Context Switch	186
Task_yield()	222
Post Semaphore No Waiting Task	103
Post Semaphore No Task Switch	204
Post Semaphore with Task Switch	274
Pend on Semaphore No Context Switch	85
Pend on Semaphore with Task Switch	309
Clock_getTicks()	12
POSIX Create a New Task without Context Switch	5125
POSIX Set a Task Priority without a Context Switch	253
POSIX Post Semaphore No Waiting Task	119
POSIX Post Semaphore No Task Switch	224
POSIX Post Semaphore with Task Switch	294
POSIX Pend on Semaphore No Context Switch	99
POSIX Pend on Semaphore with Task Switch	326

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.