IAR Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 8.32.2.178

BIOS Version: bios_6_80_00_08_eng

XDCTools Version: xdctools_3_60_00_24_core

Benchmark	Cycles
Interrupt Latency	141
Hwi_restore()	7
Hwi_disable()	9
Hwi dispatcher prolog	119
Hwi dispatcher epilog	219
Hwi dispatcher	328
Hardware Interrupt to Blocked Task	512
Hardware Interrupt to Software Interrupt	331
Swi_enable()	58
Swi_disable()	12
Post Software Interrupt Again	20
Post Software Interrupt without Context Switch	81
Post Software Interrupt with Context Switch	162
Create a New Task without Context Switch	1921
Set a Task Priority without a Context Switch	145
Task_yield()	218
Post Semaphore No Waiting Task	65
Post Semaphore No Task Switch	160
Post Semaphore with Task Switch	250
Pend on Semaphore No Context Switch	58
Pend on Semaphore with Task Switch	277
Clock_getTicks()	9
POSIX Create a New Task without Context Switch	3438
POSIX Set a Task Priority without a Context Switch	186
POSIX Post Semaphore No Waiting Task	78
POSIX Post Semaphore No Task Switch	172
POSIX Post Semaphore with Task Switch	256
POSIX Pend on Semaphore No Context Switch	48
POSIX Pend on Semaphore with Task Switch	283

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.