TI Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 18.12.2

BIOS Version: bios_6_77_00_10_eng

XDCTools Version: xdctools_3_60_00_19_core_eng

Benchmark	Cycles
Interrupt Latency	102
Hwi_restore()	6
Hwi_disable()	8
Hwi dispatcher prolog	87
Hwi dispatcher epilog	194
Hwi dispatcher	271
Hardware Interrupt to Blocked Task	447
Hardware Interrupt to Software Interrupt	305
Swi_enable()	63
Swi_disable()	9
Post Software Interrupt Again	31
Post Software Interrupt without Context Switch	84
Post Software Interrupt with Context Switch	162
Create a New Task without Context Switch	2113
Set a Task Priority without a Context Switch	136
Task_yield()	170
Post Semaphore No Waiting Task	78
Post Semaphore No Task Switch	160
Post Semaphore with Task Switch	216
Pend on Semaphore No Context Switch	61
Pend on Semaphore with Task Switch	232
Clock_getTicks()	8
POSIX Create a New Task without Context Switch	3800
POSIX Set a Task Priority without a Context Switch	183
POSIX Post Semaphore No Waiting Task	87
POSIX Post Semaphore No Task Switch	172
POSIX Post Semaphore with Task Switch	229
POSIX Pend on Semaphore No Context Switch	73
POSIX Pend on Semaphore with Task Switch	247

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.