GCC Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC2642:1

Tool Chain Version: 7.2.1

BIOS Version: bios_6_80_00_08_eng

XDCTools Version: xdctools_3_60_00_24_core

Benchmark	Cycles
Interrupt Latency	174
Hwi_restore()	17
Hwi_disable()	16
Hwi dispatcher prolog	151
Hwi dispatcher epilog	238
Hwi dispatcher	380
Hardware Interrupt to Blocked Task	651
Hardware Interrupt to Software Interrupt	454
Swi_enable()	90
Swi_disable()	20
Post Software Interrupt Again	37
Post Software Interrupt without Context Switch	117
Post Software Interrupt with Context Switch	240
Create a New Task without Context Switch	4601
Set a Task Priority without a Context Switch	199
Task_yield()	290
Post Semaphore No Waiting Task	61
Post Semaphore No Task Switch	227
Post Semaphore with Task Switch	338
Pend on Semaphore No Context Switch	75
Pend on Semaphore with Task Switch	379
Clock_getTicks()	221
POSIX Create a New Task without Context Switch	7557
POSIX Set a Task Priority without a Context Switch	283
POSIX Post Semaphore No Waiting Task	73
POSIX Post Semaphore No Task Switch	241
POSIX Post Semaphore with Task Switch	352
POSIX Pend on Semaphore No Context Switch	90
POSIX Pend on Semaphore with Task Switch	392

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings:

“-mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -Dti_sysbios_Build_useHwiMacros -Dfar= -D__DYNAMIC_REENT__”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.