EDMA3 Resource Manager: Module Index

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Modules

Here is a list of all modules:
  • EDMA3 Resource Manager
    • EDMA3 Resource Manager Symbols
      • EDMA3 Resource Manager Defines
      • EDMA3 Resource Manager Enums
      • EDMA3 Resource Manager Typedefs
    • EDMA3 Resource Manager Data Structures
    • EDMA3 Resource Manager APIs
      • EDMA3 Resource Manager Initialization APIs
      • EDMA3 Resource Manager Basic APIs
      • EDMA3 Resource Manager Advanced APIs
Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by doxygen 1.6.1


EDMA3 Resource Manager: EDMA3 Resource Manager

EDMA3 Resource Manager

Modules

EDMA3 Resource Manager Symbols
EDMA3 Resource Manager Data Structures
EDMA3 Resource Manager APIs

Detailed Description

Introduction

Overview

EDMA3 Resource Manager is a TI mandated library for all EDMA3 peripheral users to acquire and configure EDMA3 hardware resources (DMA/QDMA channels, PaRAM Sets, TCCs etc.) and DMA Interrupt Service Routines.

Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by doxygen 1.6.1


EDMA3 Resource Manager: EDMA3 Resource Manager Symbols

EDMA3 Resource Manager Symbols
[EDMA3 Resource Manager]

Modules

EDMA3 Resource Manager Defines
EDMA3 Resource Manager Enums
EDMA3 Resource Manager Typedefs

Detailed Description

Include common header file

Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by doxygen 1.6.1


EDMA3 Resource Manager: EDMA3 Resource Manager Defines

EDMA3 Resource Manager Defines
[EDMA3 Resource Manager Symbols]

Defines

#define | EDMA3_RM_RES_ANY (1010u)
Used to specify any available Resource Id (EDMA3_RM_ResDesc.resId).
#define | EDMA3_RM_E_BASE (-155)
#define | EDMA3_RM_E_OBJ_NOT_DELETED (EDMA3_RM_E_BASE)
#define | EDMA3_RM_E_OBJ_NOT_CLOSED (EDMA3_RM_E_BASE-1)
#define | EDMA3_RM_E_OBJ_NOT_OPENED (EDMA3_RM_E_BASE-2)
#define | EDMA3_RM_E_INVALID_PARAM (EDMA3_RM_E_BASE-3)
#define | EDMA3_RM_E_RES_ALREADY_FREE (EDMA3_RM_E_BASE-4)
#define | EDMA3_RM_E_RES_NOT_OWNED (EDMA3_RM_E_BASE-5)
#define | EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE (EDMA3_RM_E_BASE-6)
#define | EDMA3_RM_E_ALL_RES_NOT_AVAILABLE (EDMA3_RM_E_BASE-7)
#define | EDMA3_RM_E_INVALID_STATE (EDMA3_RM_E_BASE-8)
#define | EDMA3_RM_E_MAX_RM_INST_OPENED (EDMA3_RM_E_BASE-9)
#define | EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS (EDMA3_RM_E_BASE-10)
#define | EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED (EDMA3_RM_E_BASE-11)
#define | EDMA3_RM_E_SEMAPHORE (EDMA3_RM_E_BASE-12)
#define | EDMA3_RM_E_FEATURE_UNSUPPORTED (EDMA3_RM_E_BASE-13)
#define | EDMA3_RM_E_RES_NOT_ALLOCATED (EDMA3_RM_E_BASE-14)
#define | EDMA3_RM_DMA_CHANNEL_ANY (1011u)
#define | EDMA3_RM_QDMA_CHANNEL_ANY (1012u)
#define | EDMA3_RM_TCC_ANY (1013u)
#define | EDMA3_RM_PARAM_ANY (1014u)
#define | EDMA3_RM_CH_NO_PARAM_MAP (1015u)
#define | EDMA3_RM_CH_NO_TCC_MAP (1016u)

Define Documentation

#define EDMA3_RM_E_BASE (-155)

Resource Manager Error Codes base define

#define EDMA3_RM_E_OBJ_NOT_DELETED (EDMA3_RM_E_BASE)

Resource Manager Object Not Deleted yet. So the object cannot be created.

#define EDMA3_RM_E_OBJ_NOT_CLOSED (EDMA3_RM_E_BASE-1)

Resource Manager Object Not Closed yet. So the object cannot be deleted.

#define EDMA3_RM_E_OBJ_NOT_OPENED (EDMA3_RM_E_BASE-2)

Resource Manager Object Not Opened yet So the object cannot be closed.

#define EDMA3_RM_E_INVALID_PARAM (EDMA3_RM_E_BASE-3)

Invalid Parameter passed to API

#define EDMA3_RM_E_RES_ALREADY_FREE (EDMA3_RM_E_BASE-4)

Resource requested for freeing is already free

#define EDMA3_RM_E_RES_NOT_OWNED (EDMA3_RM_E_BASE-5)

Resource requested for allocation/freeing is not owned

#define EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE (EDMA3_RM_E_BASE-6)

Resource is not available

#define EDMA3_RM_E_ALL_RES_NOT_AVAILABLE (EDMA3_RM_E_BASE-7)

No Resource of specified type is available

#define EDMA3_RM_E_INVALID_STATE (EDMA3_RM_E_BASE-8)

Invalid State of EDMA3 RM Obj

#define EDMA3_RM_E_MAX_RM_INST_OPENED (EDMA3_RM_E_BASE-9)

Maximum no of Res Mgr Instances already Opened

#define EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS (EDMA3_RM_E_BASE-10)

More than one Res Mgr Master Instance NOT supported. Only 1 master can exist.

#define EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED (EDMA3_RM_E_BASE-11)

Callback function already registered.

#define EDMA3_RM_E_SEMAPHORE (EDMA3_RM_E_BASE-12)

Semaphore related error

#define EDMA3_RM_E_FEATURE_UNSUPPORTED (EDMA3_RM_E_BASE-13)

Hardware feature NOT supported

#define EDMA3_RM_E_RES_NOT_ALLOCATED (EDMA3_RM_E_BASE-14)

EDMA3 Resource NOT allocated

#define EDMA3_RM_DMA_CHANNEL_ANY (1011u)

Used to specify any available DMA Channel while requesting one. Used in the API EDMA3_RM_allocLogicalChannel (). DMA channel from the pool of (owned && non_reserved && available_right_now) DMA channels will be chosen and returned.

#define EDMA3_RM_QDMA_CHANNEL_ANY (1012u)

Used to specify any available QDMA Channel while requesting one. Used in the API EDMA3_RM_allocLogicalChannel(). QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned.

#define EDMA3_RM_TCC_ANY (1013u)

Used to specify any available TCC while requesting one. Used in the API EDMA3_RM_allocLogicalChannel(), for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned.

#define EDMA3_RM_PARAM_ANY (1014u)

Used to specify any available PaRAM Set while requesting one. Used in the API EDMA3_RM_allocLogicalChannel(), for both DMA/QDMA and Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned.

#define EDMA3_RM_CH_NO_PARAM_MAP (1015u)

This define is used to specify that a DMA channel is NOT tied to any PaRAM Set and hence any available PaRAM Set could be used for that DMA channel. It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.

This value should mandatorily be used to mark DMA channels with no initial mapping to specific PaRAM Sets.

#define EDMA3_RM_CH_NO_TCC_MAP (1016u)

This define is used to specify that the DMA/QDMA channel is not tied to any TCC and hence any available TCC could be used for that DMA/QDMA channel. It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.

This value should mandatorily be used to mark DMA channels with no initial mapping to specific TCCs.

Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by doxygen 1.6.1


EDMA3 Resource Manager: EDMA3 Resource Manager Enums

EDMA3 Resource Manager Enums
[EDMA3 Resource Manager Symbols]

Enumerations

enum EDMA3_RM_TccStatus {
EDMA3_RM_XFER_COMPLETE = 1,
EDMA3_RM_E_CC_DMA_EVT_MISS = 2,
EDMA3_RM_E_CC_QDMA_EVT_MISS = 3
}

This enum defines the channel specific status codes of an EDMA3 transfer. It is returned while calling the channel specific callback function to tell the status.

More...
enum EDMA3_RM_GlobalError {
EDMA3_RM_E_CC_QUE_THRES_EXCEED = 1,
EDMA3_RM_E_CC_TCC = 2,
EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR = 3,
EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR = 4,
EDMA3_RM_E_TC_INVALID_ADDR = 5,
EDMA3_RM_E_TC_TR_ERROR = 6
}

This enum defines the global (not specific to any channel) error codes of completion of an EDMA3 transfer.

More...
enum EDMA3_RM_ResType {
EDMA3_RM_RES_DMA_CHANNEL = 1,
EDMA3_RM_RES_QDMA_CHANNEL = 2,
EDMA3_RM_RES_TCC = 3,
EDMA3_RM_RES_PARAM_SET = 4
}

EDMA3 Resource Type.

More...
enum EDMA3_RM_HW_CHANNEL_EVENT {
EDMA3_RM_HW_CHANNEL_EVENT_0 = 0,
EDMA3_RM_HW_CHANNEL_EVENT_1,
EDMA3_RM_HW_CHANNEL_EVENT_2,
EDMA3_RM_HW_CHANNEL_EVENT_3,
EDMA3_RM_HW_CHANNEL_EVENT_4,
EDMA3_RM_HW_CHANNEL_EVENT_5,
EDMA3_RM_HW_CHANNEL_EVENT_6,
EDMA3_RM_HW_CHANNEL_EVENT_7,
EDMA3_RM_HW_CHANNEL_EVENT_8,
EDMA3_RM_HW_CHANNEL_EVENT_9,
EDMA3_RM_HW_CHANNEL_EVENT_10,
EDMA3_RM_HW_CHANNEL_EVENT_11,
EDMA3_RM_HW_CHANNEL_EVENT_12,
EDMA3_RM_HW_CHANNEL_EVENT_13,
EDMA3_RM_HW_CHANNEL_EVENT_14,
EDMA3_RM_HW_CHANNEL_EVENT_15,
EDMA3_RM_HW_CHANNEL_EVENT_16,
EDMA3_RM_HW_CHANNEL_EVENT_17,
EDMA3_RM_HW_CHANNEL_EVENT_18,
EDMA3_RM_HW_CHANNEL_EVENT_19,
EDMA3_RM_HW_CHANNEL_EVENT_20,
EDMA3_RM_HW_CHANNEL_EVENT_21,
EDMA3_RM_HW_CHANNEL_EVENT_22,
EDMA3_RM_HW_CHANNEL_EVENT_23,
EDMA3_RM_HW_CHANNEL_EVENT_24,
EDMA3_RM_HW_CHANNEL_EVENT_25,
EDMA3_RM_HW_CHANNEL_EVENT_26,
EDMA3_RM_HW_CHANNEL_EVENT_27,
EDMA3_RM_HW_CHANNEL_EVENT_28,
EDMA3_RM_HW_CHANNEL_EVENT_29,
EDMA3_RM_HW_CHANNEL_EVENT_30,
EDMA3_RM_HW_CHANNEL_EVENT_31,
EDMA3_RM_HW_CHANNEL_EVENT_32,
EDMA3_RM_HW_CHANNEL_EVENT_33,
EDMA3_RM_HW_CHANNEL_EVENT_34,
EDMA3_RM_HW_CHANNEL_EVENT_35,
EDMA3_RM_HW_CHANNEL_EVENT_36,
EDMA3_RM_HW_CHANNEL_EVENT_37,
EDMA3_RM_HW_CHANNEL_EVENT_38,
EDMA3_RM_HW_CHANNEL_EVENT_39,
EDMA3_RM_HW_CHANNEL_EVENT_40,
EDMA3_RM_HW_CHANNEL_EVENT_41,
EDMA3_RM_HW_CHANNEL_EVENT_42,
EDMA3_RM_HW_CHANNEL_EVENT_43,
EDMA3_RM_HW_CHANNEL_EVENT_44,
EDMA3_RM_HW_CHANNEL_EVENT_45,
EDMA3_RM_HW_CHANNEL_EVENT_46,
EDMA3_RM_HW_CHANNEL_EVENT_47,
EDMA3_RM_HW_CHANNEL_EVENT_48,
EDMA3_RM_HW_CHANNEL_EVENT_49,
EDMA3_RM_HW_CHANNEL_EVENT_50,
EDMA3_RM_HW_CHANNEL_EVENT_51,
EDMA3_RM_HW_CHANNEL_EVENT_52,
EDMA3_RM_HW_CHANNEL_EVENT_53,
EDMA3_RM_HW_CHANNEL_EVENT_54,
EDMA3_RM_HW_CHANNEL_EVENT_55,
EDMA3_RM_HW_CHANNEL_EVENT_56,
EDMA3_RM_HW_CHANNEL_EVENT_57,
EDMA3_RM_HW_CHANNEL_EVENT_58,
EDMA3_RM_HW_CHANNEL_EVENT_59,
EDMA3_RM_HW_CHANNEL_EVENT_60,
EDMA3_RM_HW_CHANNEL_EVENT_61,
EDMA3_RM_HW_CHANNEL_EVENT_62,
EDMA3_RM_HW_CHANNEL_EVENT_63
}

DMA Channels assigned to different Hardware Events.

More...
enum EDMA3_RM_QdmaTrigWord {
EDMA3_RM_QDMA_TRIG_OPT = 0,
EDMA3_RM_QDMA_TRIG_SRC = 1,
EDMA3_RM_QDMA_TRIG_ACNT_BCNT = 2,
EDMA3_RM_QDMA_TRIG_DST = 3,
EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX = 4,
EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD = 5,
EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX = 6,
EDMA3_RM_QDMA_TRIG_CCNT = 7,
EDMA3_RM_QDMA_TRIG_DEFAULT = 7
}

QDMA Trigger Word.

More...
enum EDMA3_RM_Cntrlr_PhyAddr {
EDMA3_RM_CC_PHY_ADDR = 0,
EDMA3_RM_TC0_PHY_ADDR,
EDMA3_RM_TC1_PHY_ADDR,
EDMA3_RM_TC2_PHY_ADDR,
EDMA3_RM_TC3_PHY_ADDR,
EDMA3_RM_TC4_PHY_ADDR,
EDMA3_RM_TC5_PHY_ADDR,
EDMA3_RM_TC6_PHY_ADDR,
EDMA3_RM_TC7_PHY_ADDR
}

CC/TC Physical Address.

More...
enum EDMA3_RM_IoctlCmd { ,
EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION,
EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION,
EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION,
EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION
}

EDMA3 Resource Manager IOCTL commands.

More...

Enumeration Type Documentation

enum EDMA3_RM_TccStatus

This enum defines the channel specific status codes of an EDMA3 transfer. It is returned while calling the channel specific callback function to tell the status.

Enumerator:
EDMA3_RM_XFER_COMPLETE

DMA Transfer successfully completed (true completion mode) or submitted to the TC (early completion mode).

EDMA3_RM_E_CC_DMA_EVT_MISS

Channel Controller has reported an error DMA missed events:- for all 64 DMA channels. These get latched in the event missed registers (EMR/EMRH).

EDMA3_RM_E_CC_QDMA_EVT_MISS

QDMA missed events:- for all QDMA channels. These get latched in the QDMA event missed register (QEMR).

enum EDMA3_RM_GlobalError

This enum defines the global (not specific to any channel) error codes of completion of an EDMA3 transfer.

Enumerator:
EDMA3_RM_E_CC_QUE_THRES_EXCEED

Threshold exceed:- for all event queues. These get latched in EDMA3CC error register (CCERR). This error has a direct relation with the setting of EDMA3_RM_GblConfigParams.evtQueueWaterMarkLvl

EDMA3_RM_E_CC_TCC

TCC error:- for outstanding transfer requests expected to return completion code (TCCHEN or TCINTEN bit in OPT is set to 1) exceeding the maximum limit of 63. This also gets latched in the CCERR.

EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR

Transfer Controller has reported an error Detection of a Read error signaled by the source or destination address

EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR

Detection of a Write error signaled by the source or destination address

EDMA3_RM_E_TC_INVALID_ADDR

Attempt to read or write to an invalid address in the configuration memory map.

EDMA3_RM_E_TC_TR_ERROR

Detection of a FIFO mode TR violating the FIFO mode transfer rules (the source/destination addresses and source/destination indexes must be aligned to 32 bytes).

enum EDMA3_RM_ResType

EDMA3 Resource Type.

Enumerator:
EDMA3_RM_RES_DMA_CHANNEL

DMA Channel resource

EDMA3_RM_RES_QDMA_CHANNEL

QDMA Channel resource

EDMA3_RM_RES_TCC

TCC resource

EDMA3_RM_RES_PARAM_SET

Parameter RAM Set resource

enum EDMA3_RM_HW_CHANNEL_EVENT

DMA Channels assigned to different Hardware Events.

They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. for eg, the sample SoC specific file "soc.h" can have these defines:

define EDMA3_RM_HW_CHANNEL_MCBSP_TX EDMA3_RM_HW_CHANNEL_EVENT_2 define EDMA3_RM_HW_CHANNEL_MCBSP_RX EDMA3_RM_HW_CHANNEL_EVENT_3

These defines will be used by the MCBSP driver. The same event EDMA3_RM_HW_CHANNEL_EVENT_2/3 could be mapped to some other peripheral also.

Enumerator:
EDMA3_RM_HW_CHANNEL_EVENT_0

Channel assigned to EDMA3 Event 0

EDMA3_RM_HW_CHANNEL_EVENT_1

Channel assigned to EDMA3 Event 1

EDMA3_RM_HW_CHANNEL_EVENT_2

Channel assigned to EDMA3 Event 2

EDMA3_RM_HW_CHANNEL_EVENT_3

Channel assigned to EDMA3 Event 3

EDMA3_RM_HW_CHANNEL_EVENT_4

Channel assigned to EDMA3 Event 4

EDMA3_RM_HW_CHANNEL_EVENT_5

Channel assigned to EDMA3 Event 5

EDMA3_RM_HW_CHANNEL_EVENT_6

Channel assigned to EDMA3 Event 6

EDMA3_RM_HW_CHANNEL_EVENT_7

Channel assigned to EDMA3 Event 7

EDMA3_RM_HW_CHANNEL_EVENT_8

Channel assigned to EDMA3 Event 8

EDMA3_RM_HW_CHANNEL_EVENT_9

Channel assigned to EDMA3 Event 9

EDMA3_RM_HW_CHANNEL_EVENT_10

Channel assigned to EDMA3 Event 10

EDMA3_RM_HW_CHANNEL_EVENT_11

Channel assigned to EDMA3 Event 11

EDMA3_RM_HW_CHANNEL_EVENT_12

Channel assigned to EDMA3 Event 12

EDMA3_RM_HW_CHANNEL_EVENT_13

Channel assigned to EDMA3 Event 13

EDMA3_RM_HW_CHANNEL_EVENT_14

Channel assigned to EDMA3 Event 14

EDMA3_RM_HW_CHANNEL_EVENT_15

Channel assigned to EDMA3 Event 15

EDMA3_RM_HW_CHANNEL_EVENT_16

Channel assigned to EDMA3 Event 16

EDMA3_RM_HW_CHANNEL_EVENT_17

Channel assigned to EDMA3 Event 17

EDMA3_RM_HW_CHANNEL_EVENT_18

Channel assigned to EDMA3 Event 18

EDMA3_RM_HW_CHANNEL_EVENT_19

Channel assigned to EDMA3 Event 19

EDMA3_RM_HW_CHANNEL_EVENT_20

Channel assigned to EDMA3 Event 20

EDMA3_RM_HW_CHANNEL_EVENT_21

Channel assigned to EDMA3 Event 21

EDMA3_RM_HW_CHANNEL_EVENT_22

Channel assigned to EDMA3 Event 22

EDMA3_RM_HW_CHANNEL_EVENT_23

Channel assigned to EDMA3 Event 23

EDMA3_RM_HW_CHANNEL_EVENT_24

Channel assigned to EDMA3 Event 24

EDMA3_RM_HW_CHANNEL_EVENT_25

Channel assigned to EDMA3 Event 25

EDMA3_RM_HW_CHANNEL_EVENT_26

Channel assigned to EDMA3 Event 26

EDMA3_RM_HW_CHANNEL_EVENT_27

Channel assigned to EDMA3 Event 27

EDMA3_RM_HW_CHANNEL_EVENT_28

Channel assigned to EDMA3 Event 28

EDMA3_RM_HW_CHANNEL_EVENT_29

Channel assigned to EDMA3 Event 29

EDMA3_RM_HW_CHANNEL_EVENT_30

Channel assigned to EDMA3 Event 30

EDMA3_RM_HW_CHANNEL_EVENT_31

Channel assigned to EDMA3 Event 31

EDMA3_RM_HW_CHANNEL_EVENT_32

Channel assigned to EDMA3 Event 32

EDMA3_RM_HW_CHANNEL_EVENT_33

Channel assigned to EDMA3 Event 33

EDMA3_RM_HW_CHANNEL_EVENT_34

Channel assigned to EDMA3 Event 34

EDMA3_RM_HW_CHANNEL_EVENT_35

Channel assigned to EDMA3 Event 35

EDMA3_RM_HW_CHANNEL_EVENT_36

Channel assigned to EDMA3 Event 36

EDMA3_RM_HW_CHANNEL_EVENT_37

Channel assigned to EDMA3 Event 37

EDMA3_RM_HW_CHANNEL_EVENT_38

Channel assigned to EDMA3 Event 38

EDMA3_RM_HW_CHANNEL_EVENT_39

Channel assigned to EDMA3 Event 39

EDMA3_RM_HW_CHANNEL_EVENT_40

Channel assigned to EDMA3 Event 40

EDMA3_RM_HW_CHANNEL_EVENT_41

Channel assigned to EDMA3 Event 41

EDMA3_RM_HW_CHANNEL_EVENT_42

Channel assigned to EDMA3 Event 42

EDMA3_RM_HW_CHANNEL_EVENT_43

Channel assigned to EDMA3 Event 43

EDMA3_RM_HW_CHANNEL_EVENT_44

Channel assigned to EDMA3 Event 44

EDMA3_RM_HW_CHANNEL_EVENT_45

Channel assigned to EDMA3 Event 45

EDMA3_RM_HW_CHANNEL_EVENT_46

Channel assigned to EDMA3 Event 46

EDMA3_RM_HW_CHANNEL_EVENT_47

Channel assigned to EDMA3 Event 47

EDMA3_RM_HW_CHANNEL_EVENT_48

Channel assigned to EDMA3 Event 48

EDMA3_RM_HW_CHANNEL_EVENT_49

Channel assigned to EDMA3 Event 49

EDMA3_RM_HW_CHANNEL_EVENT_50

Channel assigned to EDMA3 Event 50

EDMA3_RM_HW_CHANNEL_EVENT_51

Channel assigned to EDMA3 Event 51

EDMA3_RM_HW_CHANNEL_EVENT_52

Channel assigned to EDMA3 Event 52

EDMA3_RM_HW_CHANNEL_EVENT_53

Channel assigned to EDMA3 Event 53

EDMA3_RM_HW_CHANNEL_EVENT_54

Channel assigned to EDMA3 Event 54

EDMA3_RM_HW_CHANNEL_EVENT_55

Channel assigned to EDMA3 Event 55

EDMA3_RM_HW_CHANNEL_EVENT_56

Channel assigned to EDMA3 Event 56

EDMA3_RM_HW_CHANNEL_EVENT_57

Channel assigned to EDMA3 Event 57

EDMA3_RM_HW_CHANNEL_EVENT_58

Channel assigned to EDMA3 Event 58

EDMA3_RM_HW_CHANNEL_EVENT_59

Channel assigned to EDMA3 Event 59

EDMA3_RM_HW_CHANNEL_EVENT_60

Channel assigned to EDMA3 Event 60

EDMA3_RM_HW_CHANNEL_EVENT_61

Channel assigned to EDMA3 Event 61

EDMA3_RM_HW_CHANNEL_EVENT_62

Channel assigned to EDMA3 Event 62

EDMA3_RM_HW_CHANNEL_EVENT_63

Channel assigned to EDMA3 Event 63

enum EDMA3_RM_QdmaTrigWord

QDMA Trigger Word.

Use this enum to set the QDMA trigger word to any of the 8 DWords(uint32_t) within a Parameter RAM set

Enumerator:
EDMA3_RM_QDMA_TRIG_OPT

Set the OPT field (Offset Address 0h Bytes) as the QDMA trigger word

EDMA3_RM_QDMA_TRIG_SRC

Set the SRC field (Offset Address 4h Bytes) as the QDMA trigger word

EDMA3_RM_QDMA_TRIG_ACNT_BCNT

Set the (ACNT + BCNT) field (Offset Address 8h Bytes) as the QDMA trigger word

EDMA3_RM_QDMA_TRIG_DST

Set the DST field (Offset Address Ch Bytes) as the QDMA trigger word

EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX

Set the (SRCBIDX + DSTBIDX) field (Offset Address 10h Bytes) as the QDMA trigger word

EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD

Set the (LINK + BCNTRLD) field (Offset Address 14h Bytes) as the QDMA trigger word

EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX

Set the (SRCCIDX + DSTCIDX) field (Offset Address 18h Bytes) as the QDMA trigger word

EDMA3_RM_QDMA_TRIG_CCNT

Set the (CCNT + RSVD) field (Offset Address 1Ch Bytes) as the QDMA trigger word

EDMA3_RM_QDMA_TRIG_DEFAULT

Default Trigger Word

enum EDMA3_RM_Cntrlr_PhyAddr

CC/TC Physical Address.

Use this enum to get the physical address of the Channel Controller or the Transfer Controller. The address returned could be used by the advanced users to set/get some specific registers direclty.

Enumerator:
EDMA3_RM_CC_PHY_ADDR

Channel Controller Physical Address

EDMA3_RM_TC0_PHY_ADDR

Transfer Controller 0 Physical Address

EDMA3_RM_TC1_PHY_ADDR

Transfer Controller 1 Physical Address

EDMA3_RM_TC2_PHY_ADDR

Transfer Controller 2 Physical Address

EDMA3_RM_TC3_PHY_ADDR

Transfer Controller 3 Physical Address

EDMA3_RM_TC4_PHY_ADDR

Transfer Controller 4 Physical Address

EDMA3_RM_TC5_PHY_ADDR

Transfer Controller 5 Physical Address

EDMA3_RM_TC6_PHY_ADDR

Transfer Controller 6 Physical Address

EDMA3_RM_TC7_PHY_ADDR

Transfer Controller 7 Physical Address

enum EDMA3_RM_IoctlCmd

EDMA3 Resource Manager IOCTL commands.

Enumerator:
EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION

PaRAM Sets will be cleared OR will not be cleared during allocation, depending upon this option.

For e.g., To clear the PaRAM Sets during allocation, cmdArg = (void *)1;

To NOT clear the PaRAM Sets during allocation, cmdArg = (void *)0;

For all other values, it will return error.

By default, PaRAM Sets will be cleared during allocation.

Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources.

EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION

To check whether PaRAM Sets will be cleared or not during allocation. If the value read is '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation.

For e.g., uint32_t *isParamClearingDone = (uint32_t *)cmdArg; (*isParamClearingDone) = paramClearingRequired;

EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION

Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be modified OR will not be modified during EDMA3_RM_allocLogicalChannel (), depending upon this option.

For e.g., To modify the Registers or PaRAM Sets during allocation, cmdArg = (void *)1;

To NOT modify the Registers or PaRAM Sets during allocation, cmdArg = (void *)0;

For all other values, it will return error.

By default, Registers or PaRAM Sets will be programmed during allocation.

Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources.

EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION

To check whether Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be programmed or not during allocation (EDMA3_RM_allocLogicalChannel ()). If the value read is '1', it means that the registers/PaRAMs are getting programmed during allocation. If the value read is '0', it means that the registers/PaRAMs are NOT getting programmed during allocation.

For e.g., uint32_t *isParamClearingDone = (uint32_t *)cmdArg; (*isParamClearingDone) = paramClearingRequired;

Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by doxygen 1.6.1


EDMA3 Resource Manager: EDMA3 Resource Manager Typedefs

EDMA3 Resource Manager Typedefs
[EDMA3 Resource Manager Symbols]

Typedefs

typedef void(* | EDMA3_RM_GblErrCallback )(EDMA3_RM_GlobalError deviceStatus, uint32_t instanceId, void *gblerrData)
Global Error callback - caters to module events like bus error etc which are not channel specific. Runs in ISR context.
typedef void(* | EDMA3_RM_TccCallback )(uint32_t tcc, EDMA3_RM_TccStatus status, void *appData)
TCC callback - caters to channel-specific events like "Event Miss Error" or "Transfer Complete". Runs in ISR context.
typedef uint32_t | EDMA3_RM_RegionId
EDMA3 Region Id.
typedef uint32_t | EDMA3_RM_EventQueue
EDMA3 Event Queue assignment.

Typedef Documentation

typedef void(* EDMA3_RM_GblErrCallback)(EDMA3_RM_GlobalError deviceStatus, uint32_t instanceId, void *gblerrData)

Global Error callback - caters to module events like bus error etc which are not channel specific. Runs in ISR context.

gblerrData is application provided data when open'ing the Resource Manager.

typedef void(* EDMA3_RM_TccCallback)(uint32_t tcc, EDMA3_RM_TccStatus status, void *appData)

TCC callback - caters to channel-specific events like "Event Miss Error" or "Transfer Complete". Runs in ISR context.

appData is passed by the application during Register'ing of TCC Callback function.

EDMA3_RM_RegionId

EDMA3 Region Id.

Use this to assign channels/PaRAM sets/TCCs to a particular Region.

EDMA3_RM_EventQueue

EDMA3 Event Queue assignment.

There can be 8 Event Queues. Either of them can be assigned to a DMA/QDMA channel using this.

Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by doxygen 1.6.1


EDMA3 Resource Manager: EDMA3 Resource Manager Data Structures

EDMA3 Resource Manager Data Structures
[EDMA3 Resource Manager]

Data Structures

struct | EDMA3_RM_GblErrCallbackParams
Global Error Callback parameters. More...
struct | EDMA3_RM_ResDesc
Handle to a Resource. More...
struct | EDMA3_RM_GblConfigParams
Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...
struct | EDMA3_RM_InstanceInitConfig
Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information. More...
struct | EDMA3_RM_Param
Used to Initialize the Resource Manager Instance. More...
struct | EDMA3_RM_MiscParam
Used to specify the miscellaneous options during Resource Manager Initialization. More...
struct | EDMA3_RM_ParamentryRegs
EDMA3 PaRAM Set. More...
struct | EDMA3_RM_PaRAMRegs
EDMA3 PaRAM Set in User Configurable format. More...
Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by doxygen 1.6.1


EDMA3 Resource Manager: EDMA3 Resource Manager APIs

EDMA3 Resource Manager APIs
[EDMA3 Resource Manager]

Modules

EDMA3 Resource Manager Initialization APIs
EDMA3 Resource Manager Basic APIs
EDMA3 Resource Manager Advanced APIs
Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by doxygen 1.6.1


EDMA3 Resource Manager: EDMA3 Resource Manager Initialization APIs

EDMA3 Resource Manager Initialization APIs
[EDMA3 Resource Manager APIs]

Functions

EDMA3_RM_Result | EDMA3_RM_create (uint32_t phyCtrllerInstId, const EDMA3_RM_GblConfigParams *gblCfgParams, const void *miscParam)
Create EDMA3 Resource Manager Object.
EDMA3_RM_Result | EDMA3_RM_delete (uint32_t phyCtrllerInstId, const void *param)
Delete EDMA3 Resource Manager Object.
EDMA3_RM_Handle | EDMA3_RM_open (uint32_t phyCtrllerInstId, const EDMA3_RM_Param *initParam, EDMA3_RM_Result *errorCode)
Open EDMA3 Resource Manager Instance.
EDMA3_RM_Result | EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr, const void *param)
Close EDMA3 Resource Manager Instance.

Function Documentation

EDMA3_RM_Result EDMA3_RM_create | ( | uint32_t | phyCtrllerInstId,
 |  | const EDMA3_RM_GblConfigParams * | gblCfgParams,
 |  | const void * | miscParam
 | ) |  |

Create EDMA3 Resource Manager Object.

This API is used to create the EDMA3 Resource Manager Object. It should be called only ONCE for each EDMA3 hardware instance.

Init-time Configuration structure for EDMA3 hardware is provided to pass the SoC specific information. This configuration information could be provided by the user at init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam' argument is NULL. User can avoid these registers' programming (in some specific use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration structure and passing this structure as the third argument (miscParam).

After successful completion of this API, Resource Manager Object's state changes to EDMA3_RM_CREATED from EDMA3_RM_DELETED.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
gblCfgParams | [IN] SoC specific configuration structure for the EDMA3 Hardware.
miscParam | [IN] Misc configuration options provided in the structure 'EDMA3_RM_MiscParam'. For default options, user can pass NULL in this argument.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
EDMA3_RM_Result EDMA3_RM_delete | ( | uint32_t | phyCtrllerInstId,
 |  | const void * | param
 | ) |  |

Delete EDMA3 Resource Manager Object.

This API is used to delete the EDMA3 RM Object. It should be called once for each EDMA3 hardware instance, ONLY after closing all the previously opened EDMA3 RM Instances.

After successful completion of this API, Resource Manager Object's state changes to EDMA3_RM_DELETED.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Phy Controller Instance Id (Hardware instance id, starting from 0).
param | [IN] For possible future use.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
EDMA3_RM_Handle EDMA3_RM_open | ( | uint32_t | phyCtrllerInstId,
 |  | const EDMA3_RM_Param * | initParam,
 |  | EDMA3_RM_Result * | errorCode
 | ) |  |

Open EDMA3 Resource Manager Instance.

This API is used to open an EDMA3 Resource Manager Instance. It could be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_RM_INSTANCES instances are allowed for each EDMA3 hardware instance.

Also, only ONE Master Resource Manager Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled.

User could pass the instance specific configuration structure (initParam->rmInstInitConfig) as a part of the 'initParam' structure, during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

By default, this Resource Manager instance will clear the PaRAM Sets while allocating them. To change the default behavior, user should use the IOCTL interface appropriately.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
initParam | [IN] Used to Initialize the Resource Manager Instance (Master or Slave).
errorCode | [OUT] Error code while opening RM instance.
Returns:
Handle to the opened Resource Manager instance Or NULL in case of error.
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data structures, to make it re-entrant.
EDMA3_RM_Result EDMA3_RM_close | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | const void * | param
 | ) |  |

Close EDMA3 Resource Manager Instance.

This API is used to close a previously opened EDMA3 RM Instance.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
param | [IN] For possible future use.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data structures, to make it re-entrant.
Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by doxygen 1.6.1


EDMA3 Resource Manager: EDMA3 Resource Manager Basic APIs

EDMA3 Resource Manager Basic APIs
[EDMA3 Resource Manager APIs]

Functions

EDMA3_RM_Result | EDMA3_RM_registerTccCb (EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj, uint32_t tcc, EDMA3_RM_TccCallback tccCb, void *cbData)
Registers a transfer completion handler for a specific DMA/QDMA channel.
EDMA3_RM_Result | EDMA3_RM_unregisterTccCb (EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *channelObj)
Unregister the previously registered callback function against a DMA/QDMA channel.
EDMA3_RM_Result | EDMA3_RM_allocResource (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *resObj)
This API is used to allocate specified EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC.
EDMA3_RM_Result | EDMA3_RM_freeResource (EDMA3_RM_Handle hEdmaResMgr, const EDMA3_RM_ResDesc *resObj)
This API is used to free previously allocated EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC.
EDMA3_RM_Result | EDMA3_RM_allocContiguousResource (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, uint32_t numResources)
Allocate a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC.
EDMA3_RM_Result | EDMA3_RM_freeContiguousResource (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *firstResIdObj, uint32_t numResources)
Free a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated.

Function Documentation

EDMA3_RM_Result EDMA3_RM_registerTccCb | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | const EDMA3_RM_ResDesc * | channelObj,
 |  | uint32_t | tcc,
 |  | EDMA3_RM_TccCallback | tccCb,
 |  | void * | cbData
 | ) |  |

Registers a transfer completion handler for a specific DMA/QDMA channel.

This function registers a non-NULL callback function for a specific DMA or QDMA channel and enables the completion interrupt for the TCC associated with the underlying channel in the IER/IERH register. It also sets the DRAE/DRAEH register for the TCC associated with the specified DMA/QDMA channel. If user enables the transfer completion interrupts (intermediate or final) in the OPT field of the associated PaRAM Set, the registered callback function will be called by the EDMA3 Resource Manager.

If a call-back function is already registered for the channel, the API fails with the error code EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened EDMA3 Resource Manager Instance
channelObj | [IN] Channel ID and type (DMA or QDMA Channel), allocated earlier, and corresponding to which a callback function needs to be registered against the associated TCC.
tcc | [IN] TCC against which the handler needs to be registered.
tccCb | [IN] The Callback function to be registered against the TCC.
cbData | [IN] Callback data to be passed while calling the callback function.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is re-entrant for unique tcc values. It is non- re-entrant for same tcc value.
EDMA3_RM_Result EDMA3_RM_unregisterTccCb | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | const EDMA3_RM_ResDesc * | channelObj
 | ) |  |

Unregister the previously registered callback function against a DMA/QDMA channel.

This function un-registers the previously registered callback function for the DMA/QDMA channel by removing any stored callback function. Moreover, it clears the: Interrupt Enable Register (IER/IERH) by writing to the IECR/IECRH register, for the TCC associated with that particular channel, DRA/DRAEH register for the TCC associated with the specified DMA/QDMA channel

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened EDMA3 Resource Manager Instance
channelObj | [IN] Channel ID and type, allocated earlier (DMA or QDMA Channel ONLY), and corresponding to which a TCC is there. Against that TCC, the callback needs to be un-registered.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code.
Note:
This function is re-entrant for unique (channelObj->type + channelObj->resId) combination. It is non-re-entrant for same channelObj Resource.
EDMA3_RM_Result EDMA3_RM_allocResource | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | EDMA3_RM_ResDesc * | resObj
 | ) |  |

This API is used to allocate specified EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC.

Note: To free the resources allocated by this API, user should call EDMA3_RM_freeResource () ONLY to de-allocate all the allocated resources.

User can either request a specific resource by passing the resource id in 'resObj->resId' OR request ANY available resource of the type 'resObj->type'.

ANY types of resources are those resources when user doesn't care about the actual resource allocated; user just wants a resource of the type specified. One use-case is to perform memory-to-memory data transfer operation. This operation can be performed using any available DMA or QDMA channel. User doesn't need any specific channel for the same.

To allocate a specific resource, first this API checks whether that resource is OWNED by the Resource Manager instance. Then it checks the current availability of that resource.

To allocate ANY available resource, this API tries to allocate a resource from the pool of (owned && non_reserved && available_right_now) resources.

After allocating a DMA/QDMA channel, the same resource is enabled in the shadow region specific register (DRAE/DRAEH/QRAE). DRAE/DRAEH register for a TCC is updated only when user registers a callback function against that TCC using EDMA3_RM_registerTccCb().

Allocated PaRAM Set is initialized to NULL before this API returns if user has requested for one.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
resObj | [IN/OUT] Handle to the resource descriptor object, which needs to be allocated. In case user passes a specific resource Id, resObj value is left unchanged. In case user requests ANY available resource, the allocated resource id is returned in resObj.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It is re-entrant, but should not be called from the user callback function (ISR context).
EDMA3_RM_Result EDMA3_RM_freeResource | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | const EDMA3_RM_ResDesc * | resObj
 | ) |  |

This API is used to free previously allocated EDMA3 Resources like DMA/QDMA channel, PaRAM Set or TCC.

To free a specific resource, first this API checks whether that resource is OWNED by the Resource Manager Instance. Then it checks whether that resource has been allocated by the Resource Manager instance or not.

After freeing a DMA/QDMA channel, the same resource is disabled in the shadow region specific register (DRAE/DRAEH/QRAE). This operation is performed for TCC while unregistering the callback function.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
resObj | [IN] Handle to the resource descriptor object, which needs to be freed.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function disables the global interrupts to prevent simultaneous access to the global pool of resources. It is re-entrant.
EDMA3_RM_Result EDMA3_RM_allocContiguousResource | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | EDMA3_RM_ResDesc * | firstResIdObj,
 |  | uint32_t | numResources
 | ) |  |

Allocate a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC.

This API is used to allocate a contiguous region of specified EDMA3 Resources like DMA channel, QDMA channel, PaRAM Set or TCC.

User can specify a particular resource Id to start with and go up to the number of resources requested. The specific resource id to start from could be passed in 'firstResIdObject->resId' and the number of resources requested in 'numResources'.

User can also request ANY available resource(s) of the type 'firstResIdObject->type' by specifying 'firstResIdObject->resId' as EDMA3_RM_RES_ANY.

ANY types of resources are those resources when user doesn't care about the actual resource allocated; user just wants a resource of the type specified. One use-case is to perform memory-to-memory data transfer operation. This operation can be performed using any available DMA or QDMA channel. User doesn't need any specific channel for the same.

To allocate specific contiguous resources, first this API checks whether those requested resources are OWNED by the Resource Manager instance. Then it checks the current availability of those resources.

To allocate ANY available contiguous resources, this API tries to allocate resources from the pool of (owned && non_reserved && available_right_now) resources.

After allocating DMA/QDMA channels, the same resources are enabled in the shadow region specific register (DRAE/DRAEH/QRAE). DRAE/DRAEH register for a TCC is updated only when user registers a callback function against that TCC using EDMA3_RM_registerTccCb(). Allocated PaRAM Sets are initialized to NULL before this API returns.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
firstResIdObj | [IN] Handle to the first resource descriptor object, which needs to be allocated. firstResIdObject->resId could be a valid resource id in case user wants to allocate specific resources OR it could be EDMA3_RM_RES_ANY in case user wants only the required number of resources and doesn't care about which resources were allocated.
numResources | [IN] Number of contiguous resources user wants to allocate.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It is re-entrant, but should not be called from the user callback function (ISR context).
EDMA3_RM_Result EDMA3_RM_freeContiguousResource | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | EDMA3_RM_ResDesc * | firstResIdObj,
 |  | uint32_t | numResources
 | ) |  |

Free a contiguous region of specified EDMA3 Resource like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated.

This API frees a contiguous region of specified EDMA3 Resources like DMA channel, QDMA channel, PaRAM Set or TCC, which have been previously allocated. In case of an error during the freeing of any specific resource, user can check the 'firstResIdObj' object to know the last resource id whose freeing has failed. In case of success, there is no need to check this object.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
firstResIdObj | [IN/OUT] Handle to the first resource descriptor object, which needs to be freed. In case of an error while freeing any particular resource, the last resource id whose freeing has failed is returned in this resource descriptor object.
numResources | [IN] Number of contiguous resources allocated previously which user wants to release
Note:
This is a re-entrant function which internally calls EDMA3_RM_freeResource() for resource de-allocation.
Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by doxygen 1.6.1


EDMA3 Resource Manager: EDMA3 Resource Manager Advanced APIs

EDMA3 Resource Manager Advanced APIs
[EDMA3 Resource Manager APIs]

Data Structures

struct | EDMA3_RM_GblXbarToChanConfigParams
Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...

Typedefs

typedef EDMA3_RM_Result(* | EDMA3_RM_mapXbarEvtToChan )(uint32_t eventNum, uint32_t *chanNum, const EDMA3_RM_GblXbarToChanConfigParams *edmaGblXbarConfig)
Associates cross bar mapped event to channel.
typedef EDMA3_RM_Result(* | EDMA3_RM_xbarConfigScr )(uint32_t eventNum, uint32_t chanNum)
Writes to the cross bar mapped event to channel to system configuration register.

Functions

EDMA3_RM_Result | EDMA3_RM_allocLogicalChannel (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, uint32_t *pParam, uint32_t *pTcc)
Request a DMA/QDMA/Link channel.
EDMA3_RM_Result | EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj)
This API is used to free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc).
EDMA3_RM_Result | EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle hEdmaResMgr, uint32_t channelId, uint32_t paRAMId)
Bind the resources DMA Channel and PaRAM Set. Both the DMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error.
EDMA3_RM_Result | EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle hEdmaResMgr, uint32_t channelId, uint32_t paRAMId, EDMA3_RM_QdmaTrigWord trigWord)
Bind the resources QDMA Channel and PaRAM Set. Also, Set the trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error.
EDMA3_RM_Result | EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr, uint32_t regOffset, uint32_t newRegValue)
Set the Channel Controller (CC) Register value.
EDMA3_RM_Result | EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr, uint32_t regOffset, uint32_t *regValue)
Get the Channel Controller (CC) Register value.
EDMA3_RM_Result | EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle hEdmaResMgr, uint32_t tccNo)
Wait for a transfer completion interrupt to occur and clear it.
EDMA3_RM_Result | EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle hEdmaResMgr, uint32_t tccNo, uint16_t *tccStatus)
Returns the status of a previously initiated transfer.
EDMA3_RM_Result | EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, const EDMA3_RM_PaRAMRegs *newPaRAM)
Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).
EDMA3_RM_Result | EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, EDMA3_RM_PaRAMRegs *currPaRAM)
Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).
EDMA3_RM_Result | EDMA3_RM_getPaRAMPhyAddr (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_ResDesc *lChObj, uint32_t *paramPhyAddr)
Get the PaRAM Set Physical Address associated with a logical channel.
EDMA3_RM_Result | EDMA3_RM_getBaseAddress (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_Cntrlr_PhyAddr controllerId, uint32_t *phyAddress)
Get the Channel Controller or Transfer Controller (n) Physical Address.
EDMA3_RM_Result | EDMA3_RM_getGblConfigParams (uint32_t phyCtrllerInstId, EDMA3_RM_GblConfigParams *gblCfgParams)
Get the SoC specific configuration structure for the EDMA3 Hardware.
EDMA3_RM_Result | EDMA3_RM_getInstanceInitCfg (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_InstanceInitConfig *instanceInitConfig)
Get the RM Instance specific configuration structure for different EDMA3 resources' usage (owned resources, reserved resources etc).
EDMA3_RM_Result | EDMA3_RM_Ioctl (EDMA3_RM_Handle hEdmaResMgr, EDMA3_RM_IoctlCmd cmd, void *cmdArg, void *param)
EDMA3 Resource Manager IOCTL.
EDMA3_RM_Result | EDMA3_RM_initXbarEventMap (EDMA3_RM_Handle hEdma, const EDMA3_RM_GblXbarToChanConfigParams *edmaGblXbarConfig, EDMA3_RM_mapXbarEvtToChan mapXbarEvtFunc, EDMA3_RM_xbarConfigScr configXbarScr)
Initialize the cross bar mapped event to channel function.

Typedef Documentation

typedef EDMA3_RM_Result(* EDMA3_RM_mapXbarEvtToChan)(uint32_t eventNum, uint32_t *chanNum, const EDMA3_RM_GblXbarToChanConfigParams *edmaGblXbarConfig)

Associates cross bar mapped event to channel.

This function have to be defined in the configuration file. This function will be called only if the channel requested for is beyond the maximum number of channels. This function should read from the global cross bar mapped configuration data structure and return the mapped channel number to this event.

Parameters:
eventNum | [IN] Event number
chanNum | [IN/OUT]Return the channel number to which the request event is mapped to.
edmaGblXbarConfig | [IN] This is the configuration data structure for mapping the events to the channel
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is re-entrant for unique event values. It is non-re-entrant for same event values.
typedef EDMA3_RM_Result(* EDMA3_RM_xbarConfigScr)(uint32_t eventNum, uint32_t chanNum)

Writes to the cross bar mapped event to channel to system configuration register.

This function have to be defined in the configuration file. This function will be called only if the event number requested for is beyond the maximum number of channels and if any channel is allocated to this event. This function should read the cross bar mapped event number and write the allocated channel number in Control Config Event Mux registers.

Parameters:
eventNum | [IN] Event number
chanNum | [IN/OUT]Return the channel number to which the request event is mapped to.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is re-entrant for unique event values. It is non-re-entrant for same event values.

Function Documentation

EDMA3_RM_Result EDMA3_RM_allocLogicalChannel | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | EDMA3_RM_ResDesc * | lChObj,
 |  | uint32_t * | pParam,
 |  | uint32_t * | pTcc
 | ) |  |

Request a DMA/QDMA/Link channel.

This API is used to allocate a logical channel (DMA/QDMA/Link) along with the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are also allocated along with the requested channel. For Link channel, ONLY a PaRAM Set is allocated.

Note: To free the logical channel allocated by this API, user should call EDMA3_RM_freeLogicalChannel () ONLY to de-allocate all the allocated resources and remove certain mappings.

User can request a specific logical channel by passing the channel id in 'lChObj->resId' and channel type in 'lChObj->type'. Note that the channel id is the same as the actual resource id. For e.g. in the case of QDMA channels, valid channel ids are from 0 to 7 only.

User can also request ANY available logical channel of the type 'lChObj->type' by specifying 'lChObj->resId' as: a) EDMA3_RM_DMA_CHANNEL_ANY: For DMA channels b) EDMA3_RM_QDMA_CHANNEL_ANY: For QDMA channels, and c) EDMA3_RM_PARAM_ANY: For Link channels. Normally user should use this value to request link channels (PaRAM Sets used for linking purpose only), unless he wants to use some specific link channels (PaRAM Sets) which is also allowed.

This API internally uses EDMA3_RM_allocResource () to allocate the desired resources (DMA/QDMA channel, PaRAM Set and TCC).

For DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC.

For DMA channel, it also sets the DCHMAP register, if required.

For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and enables the QDMA channel by writing to the QEESR register.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
lChObj | [IN/OUT] Handle to the requested logical channel object, which needs to be allocated. It could be a specific logical channel or ANY available logical channel of the requested type. In case user passes a specific resource Id, lChObj value is left unchanged. In case user requests ANY available resource, the allocated resource id is returned in lChObj->resId.
pParam | [IN/OUT] PaRAM Set for a particular logical (DMA/QDMA) channel. Not used if user requested for a Link channel. In case user passes a specific PaRAM Set value, pParam value is left unchanged. In case user requests ANY available PaRAM Set by passing 'EDMA3_RM_PARAM_ANY' in pParam, the allocated one is returned in pParam.
pTcc | [IN/OUT] TCC for a particular logical (DMA/QDMA) channel. Not used if user requested for a Link channel. In case user passes a specific TCC value, pTcc value is left unchanged. In case user requests ANY available TCC by passing 'EDMA3_RM_TCC_ANY' in pTcc, the allocated one is returned in pTcc.
Returns:
EDMA3_RM_SOK or EDMA_RM Error Code
Note:
This function internally calls EDMA3_RM_allocResource (), which acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It is re-entrant for unique logical channel values, but SHOULD NOT be called from the user callback function (ISR context).
EDMA3_RM_Result EDMA3_RM_freeLogicalChannel | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | EDMA3_RM_ResDesc * | lChObj
 | ) |  |

This API is used to free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc).

This API internally uses EDMA3_RM_freeResource () to free the desired resources.

For DMA/QDMA channels, it also clears the DCHMAP/QCHMAP registers

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
lChObj | [IN] Handle to the logical channel object, which needs to be freed
Returns:
EDMA3_RM_SOK or EDMA_RM Error Code
Note:
This is a re-entrant function which internally calls EDMA3_RM_freeResource () for resource de-allocation.
EDMA3_RM_Result EDMA3_RM_mapEdmaChannel | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | uint32_t | channelId,
 |  | uint32_t | paRAMId
 | ) |  |

Bind the resources DMA Channel and PaRAM Set. Both the DMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error.

This API sets the DCHMAP register for a specific DMA channel. This register is used to specify the PaRAM Set associated with that particular DMA Channel.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
channelId | [IN] Previously allocated DMA Channel on which Transfer will occur.
paRAMId | [IN] Previously allocated PaRAM Set which needs to be associated with the dma channel.
Returns:
EDMA3_RM_SOK or EDMA_RM Error Code
Note:
This API is useful only for the EDMA3 Controllers which have a register for mapping a DMA Channel to a particular PaRAM Set (DCHMAP register). On platforms where this feature is not supported, this API returns error code: EDMA3_RM_E_FEATURE_UNSUPPORTED. This function is re-entrant for unique channelId. It is non-re-entrant for same channelId values.
EDMA3_RM_Result EDMA3_RM_mapQdmaChannel | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | uint32_t | channelId,
 |  | uint32_t | paRAMId,
 |  | EDMA3_RM_QdmaTrigWord | trigWord
 | ) |  |

Bind the resources QDMA Channel and PaRAM Set. Also, Set the trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set should be previously allocated. If they are not, this API will result in error.

This API sets the QCHMAP register for a specific QDMA channel. This register is used to specify the PaRAM Set associated with that particular QDMA Channel along with the trigger word.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
channelId | [IN] Previously allocated QDMA Channel on which Transfer will occur.
paRAMId | [IN] Previously allocated PaRAM Set, which needs to be associated with channelId
trigWord | [IN] The Trigger Word for the channel. Trigger Word is the word in the PaRAM Register Set which - when written to by CPU -will start the QDMA transfer automatically
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is re-entrant for unique channelId. It is non-re-entrant for same channelId values.
EDMA3_RM_Result EDMA3_RM_setCCRegister | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | uint32_t | regOffset,
 |  | uint32_t | newRegValue
 | ) |  |

Set the Channel Controller (CC) Register value.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
regOffset | [IN] CC Register offset whose value needs to be set. It should be word-aligned.
newRegValue | [IN] New CC Register Value
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is non re-entrant for users using the same Resource Manager handle. Before modifying a register, it tries to acquire a semaphore (RM instance specific), to protect simultaneous modification of the same register by two different users. After the successful change, it releases the semaphore. For users using different RM handles, this function is re-entrant.
EDMA3_RM_Result EDMA3_RM_getCCRegister | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | uint32_t | regOffset,
 |  | uint32_t * | regValue
 | ) |  |

Get the Channel Controller (CC) Register value.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
regOffset | [IN] CC Register offset whose value is needed. It should be word-aligned.
regValue | [IN/OUT] Fetched CC Register Value
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is re-entrant.
EDMA3_RM_Result EDMA3_RM_waitAndClearTcc | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | uint32_t | tccNo
 | ) |  |

Wait for a transfer completion interrupt to occur and clear it.

This is a blocking function that returns when the IPR/IPRH bit corresponding to the tccNo specified, is SET. It clears the corresponding bit while returning also.

This function waits for the specific bit indefinitely in a tight loop, with out any delay in between. USE IT CAUTIOUSLY.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
tccNo | [IN] TCC, specific to which the function waits on a IPR/IPRH bit.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is re-entrant for different tccNo.
EDMA3_RM_Result EDMA3_RM_checkAndClearTcc | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | uint32_t | tccNo,
 |  | uint16_t * | tccStatus
 | ) |  |

Returns the status of a previously initiated transfer.

This is a non-blocking function that returns the status of a previously initiated transfer, based on the IPR/IPRH bit. This bit corresponds to the tccNo specified by the user. It clears the corresponding bit, if SET, while returning also.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
tccNo | [IN] TCC, specific to which the function checks the status of the IPR/IPRH bit.
tccStatus | [IN/OUT] Status of the transfer is returned here. Returns "TRUE" if the transfer has completed (IPR/IPRH bit SET), "FALSE" if the transfer has not completed successfully (IPR/IPRH bit NOT SET).
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is re-entrant for different tccNo.
EDMA3_RM_Result EDMA3_RM_setPaRAM | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | EDMA3_RM_ResDesc * | lChObj,
 |  | const EDMA3_RM_PaRAMRegs * | newPaRAM
 | ) |  |

Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).

This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set associated with the logical channel. OPT field of the PaRAM Set is written first and the CCNT field is written last.

Caution: It should be used carefully when programming the QDMA channels whose trigger words are not CCNT field.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
lChObj | [IN] Logical Channel object for which new PaRAM set is specified. User should pass the resource type and id in this object.
newPaRAM | [IN] PaRAM set to be copied onto existing one
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is re-entrant for unique lChObj values. It is non- re-entrant for same lChObj value.
EDMA3_RM_Result EDMA3_RM_getPaRAM | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | EDMA3_RM_ResDesc * | lChObj,
 |  | EDMA3_RM_PaRAMRegs * | currPaRAM
 | ) |  |

Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
lChObj | [IN] Logical Channel object for which the PaRAM set is requested. User should pass the resource type and id in this object.
currPaRAM | [IN/OUT] User gets the existing PaRAM here.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is re-entrant.
EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | EDMA3_RM_ResDesc * | lChObj,
 |  | uint32_t * | paramPhyAddr
 | ) |  |

Get the PaRAM Set Physical Address associated with a logical channel.

This function returns the PaRAM Set Phy Address (unsigned 32 bits). The returned address could be used by the advanced users to program the PaRAM Set directly without using any APIs.

Least significant 16 bits of this address could be used to program the LINK field in the PaRAM Set. Users which program the LINK field directly SHOULD use this API to get the associated PaRAM Set address with the LINK channel.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
lChObj | [IN] Logical Channel object for which the PaRAM set physical address is required. User should pass the resource type and id in this object.
paramPhyAddr | [IN/OUT] PaRAM Set physical address is returned here.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is re-entrant.
EDMA3_RM_Result EDMA3_RM_getBaseAddress | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | EDMA3_RM_Cntrlr_PhyAddr | controllerId,
 |  | uint32_t * | phyAddress
 | ) |  |

Get the Channel Controller or Transfer Controller (n) Physical Address.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
controllerId | [IN] Channel Controller or Transfer Controller (n) for which the physical address is required.
phyAddress | [IN/OUT] Physical address is returned here.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is re-entrant.
EDMA3_RM_Result EDMA3_RM_getGblConfigParams | ( | uint32_t | phyCtrllerInstId,
 |  | EDMA3_RM_GblConfigParams * | gblCfgParams
 | ) |  |

Get the SoC specific configuration structure for the EDMA3 Hardware.

This API is used to fetch the global SoC specific configuration structure for the EDMA3 Hardware. It is useful for the user who has not passed this information during EDMA3_RM_create() and taken the default configuration coming along with the package.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
gblCfgParams | [IN/OUT] SoC specific configuration structure for the EDMA3 Hardware will be returned here.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is re-entrant.
EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | EDMA3_RM_InstanceInitConfig * | instanceInitConfig
 | ) |  |

Get the RM Instance specific configuration structure for different EDMA3 resources' usage (owned resources, reserved resources etc).

This API is used to fetch the Resource Manager Instance specific configuration structure, for a specific shadow region. It is useful for the user who has not passed this information during EDMA3_RM_opn() and taken the default configuration coming along with the package. EDMA3 resources, owned and reserved by this RM instance, will be returned from this API.

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
instanceInitConfig | [IN/OUT] RM Instance specific configuration structure will be returned here.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function is re-entrant.
EDMA3_RM_Result EDMA3_RM_Ioctl | ( | EDMA3_RM_Handle | hEdmaResMgr,
 |  | EDMA3_RM_IoctlCmd | cmd,
 |  | void * | cmdArg,
 |  | void * | param
 | ) |  |

EDMA3 Resource Manager IOCTL.

This function provides IOCTL functionality for EDMA3 Resource Manager

Parameters:
hEdmaResMgr | [IN] Handle to the previously opened Resource Manager Instance.
cmd | [IN] IOCTL command to be performed
cmdArg | [IN/OUT] IOCTL command argument (if any)
param | [IN/OUT] Device/Cmd specific argument.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
For 'EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant. For 'EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for different Resource Manager Instances (handles).
EDMA3_RM_Result EDMA3_RM_initXbarEventMap | ( | EDMA3_RM_Handle | hEdma,
 |  | const EDMA3_RM_GblXbarToChanConfigParams * | edmaGblXbarConfig,
 |  | EDMA3_RM_mapXbarEvtToChan | mapXbarEvtFunc,
 |  | EDMA3_RM_xbarConfigScr | configXbarScr
 | ) |  |

Initialize the cross bar mapped event to channel function.

This API provides interface to associate the cross bar mapped event to edma channel in the driver. This function will called by the application during initilization. User could pass the application specific configuration structure during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
edmaGblXbarConfig | [IN] This is the configuration data structure for mapping the events to the channel
mapXbarEvtFunc | [IN] This is the user defined function for mapping the cross bar event to channel.
Returns:
EDMA3_RM_SOK or EDMA3_RM Error Code
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant.
Generated on Mon Feb 14 18:31:17 2011 for EDMA3 Resource Manager by doxygen 1.6.1


EDMA3 Resource Manager: Data Structures

  • Data Structure Index
  • Data Fields

Data Structures

Here are the data structures with brief descriptions:
EDMA3_RM_ChBoundResources | EDMA3 Channel-Bound resources
EDMA3_RM_GblConfigParams | Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information
EDMA3_RM_GblErrCallbackParams | Global Error Callback parameters
EDMA3_RM_GblXbarToChanConfigParams | Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information
EDMA3_RM_Instance | EDMA3 RM Instance Specific Configuration Structure
EDMA3_RM_InstanceInitConfig | Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information
EDMA3_RM_MiscParam | Used to specify the miscellaneous options during Resource Manager Initialization
EDMA3_RM_Obj | EDMA3 Hardware Instance Configuration Structure
EDMA3_RM_Param | Used to Initialize the Resource Manager Instance
EDMA3_RM_ParamentryRegs | EDMA3 PaRAM Set
EDMA3_RM_PaRAMRegs | EDMA3 PaRAM Set in User Configurable format
EDMA3_RM_ResDesc | Handle to a Resource
EDMA3_RM_TccCallbackParams | TCC Callback - Caters to channel specific status reporting
Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by doxygen 1.6.1


EDMA3 Resource Manager: EDMA3_RM_ChBoundResources Struct Reference

EDMA3_RM_ChBoundResources Struct Reference

EDMA3 Channel-Bound resources. More...

#include <edma3resmgr.h>

Data Fields

int | paRAMId
unsigned int | tcc

Detailed Description

EDMA3 Channel-Bound resources.

Used to maintain information of the EDMA3 resources (specifically Parameter RAM set and TCC), bound to the particular channel within EDMA3_RM_allocLogicalChannel ().

Field Documentation

int EDMA3_RM_ChBoundResources::paRAMId

PaRAM Set number associated with the particular channel

unsigned int EDMA3_RM_ChBoundResources::tcc

TCC associated with the particular channel

The documentation for this struct was generated from the following file:
  • edma3resmgr.h


EDMA3 Resource Manager: EDMA3_RM_GblConfigParams Struct Reference

EDMA3_RM_GblConfigParams Struct Reference
[EDMA3 Resource Manager Data Structures]

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...

#include <edma3_rm.h>

Data Fields

uint32_t | numDmaChannels
uint32_t | numQdmaChannels
uint32_t | numTccs
uint32_t | numPaRAMSets
uint32_t | numEvtQueue
uint32_t | numTcs
uint32_t | numRegions
uint32_t | dmaChPaRAMMapExists
Channel mapping existence.
uint32_t | memProtectionExists
void * | globalRegs
void * | tcRegs [EDMA3_MAX_TC]
uint32_t | xferCompleteInt
uint32_t | ccError
uint32_t | tcError [EDMA3_MAX_TC]
uint32_t | evtQPri [EDMA3_MAX_EVT_QUE]
EDMA3 TC priority setting.
uint32_t | evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE]
Event Queues Watermark Levels.
uint32_t | tcDefaultBurstSize [EDMA3_MAX_TC]
Default Burst Size (DBS) of TCs.
uint32_t | dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH]
Mapping from DMA channels to PaRAM Sets.
uint32_t | dmaChannelTccMap [EDMA3_MAX_DMA_CH]
Mapping from DMA channels to TCCs.
uint32_t | dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS]
Mapping from DMA channels to Hardware Events.

Detailed Description

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.

This configuration structure is used to specify the EDMA3 Resource Manager global settings, specific to the SoC. For e.g. number of DMA/QDMA channels, number of PaRAM sets, TCCs, event queues, transfer controllers, base addresses of CC global registers and TC registers, interrupt number for EDMA3 transfer completion, CC error, event queues' priority, watermark threshold level etc. This configuration information is SoC specific and could be provided by the user at run-time while creating the EDMA3 RM Object, using API EDMA3_RM_create. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

Field Documentation

uint32_t EDMA3_RM_GblConfigParams::numDmaChannels

Number of DMA Channels supported by the underlying EDMA3 Controller.

uint32_t EDMA3_RM_GblConfigParams::numQdmaChannels

Number of QDMA Channels supported by the underlying EDMA3 Controller

uint32_t EDMA3_RM_GblConfigParams::numTccs

Number of Interrupt Channels supported by the underlying EDMA3 Controller

uint32_t EDMA3_RM_GblConfigParams::numPaRAMSets

Number of PaRAM Sets supported by the underlying EDMA3 Controller

uint32_t EDMA3_RM_GblConfigParams::numEvtQueue

Number of Event Queues in the underlying EDMA3 Controller

uint32_t EDMA3_RM_GblConfigParams::numTcs

Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller

uint32_t EDMA3_RM_GblConfigParams::numRegions

Number of Regions in the underlying EDMA3 Controller

uint32_t EDMA3_RM_GblConfigParams::dmaChPaRAMMapExists

Channel mapping existence.

A value of 0 (No channel mapping) implies that there is fixed association between a DMA channel and a PaRAM Set or, in other words, DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP registers) for transfers to happen.

A value of 1 implies the presence of DCHMAP registers for the DMA channels and hence the flexibility of associating any DMA channel to any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA channel (like QDMA Channels).

uint32_t EDMA3_RM_GblConfigParams::memProtectionExists

Existence of memory protection feature

void* EDMA3_RM_GblConfigParams::globalRegs

Base address of EDMA3 CC memory mapped registers.

void* EDMA3_RM_GblConfigParams::tcRegs[EDMA3_MAX_TC]

Base address of EDMA3 TCs memory mapped registers.

uint32_t EDMA3_RM_GblConfigParams::xferCompleteInt

EDMA3 transfer completion interrupt line (could be different for ARM and DSP)

uint32_t EDMA3_RM_GblConfigParams::ccError

EDMA3 CC error interrupt line (could be different for ARM and DSP)

uint32_t EDMA3_RM_GblConfigParams::tcError[EDMA3_MAX_TC]

EDMA3 TCs error interrupt line (could be different for ARM and DSP)

uint32_t EDMA3_RM_GblConfigParams::evtQPri[EDMA3_MAX_EVT_QUE]

EDMA3 TC priority setting.

User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Controllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc)

uint32_t EDMA3_RM_GblConfigParams::evtQueueWaterMarkLvl[EDMA3_MAX_EVT_QUE]

Event Queues Watermark Levels.

To Configure the Threshold level of number of events that can be queued up in the Event queues. EDMA3CC error register (CCERR) will indicate whether or not at any instant of time the number of events queued up in any of the event queues exceeds or equals the threshold/watermark value that is set in the queue watermark threshold register (QWMTHRA).

uint32_t EDMA3_RM_GblConfigParams::tcDefaultBurstSize[EDMA3_MAX_TC]

Default Burst Size (DBS) of TCs.

An optimally-sized command is defined by the transfer controller default burst size (DBS). Different TCs can have different DBS values. It is defined in Bytes.

uint32_t EDMA3_RM_GblConfigParams::dmaChannelPaRAMMap[EDMA3_MAX_DMA_CH]

Mapping from DMA channels to PaRAM Sets.

If channel mapping exists (DCHMAP registers are present), this array stores the respective PaRAM Set for each DMA channel. User can initialize each array member with a specific PaRAM Set or with EDMA3_DRV_CH_NO_PARAM_MAP. If channel mapping doesn't exist, it is of no use as the EDMA3 RM automatically uses the right PaRAM Set for that DMA channel. Useful only if mapping exists, otherwise of no use.

uint32_t EDMA3_RM_GblConfigParams::dmaChannelTccMap[EDMA3_MAX_DMA_CH]

Mapping from DMA channels to TCCs.

This array stores the respective TCC (interrupt channel) for each DMA channel. User can initialize each array member with a specific TCC or with EDMA3_DRV_CH_NO_TCC_MAP. This specific TCC code will be returned when the transfer is completed on the mapped DMA channel.

uint32_t EDMA3_RM_GblConfigParams::dmaChannelHwEvtMap[EDMA3_MAX_DMA_CHAN_DWRDS]

Mapping from DMA channels to Hardware Events.

Each bit in this array corresponds to one DMA channel and tells whether this DMA channel is tied to any peripheral. That is whether any peripheral can send the synch event on this DMA channel or not. 1 means the channel is tied to some peripheral; 0 means it is not. DMA channels which are tied to some peripheral are RESERVED for that peripheral only. They are not allocated when user asks for 'ANY' DMA channel. All channels need not be mapped, some can be free also.

The documentation for this struct was generated from the following file:
  • edma3_rm.h


EDMA3 Resource Manager: EDMA3_RM_GblErrCallbackParams Struct Reference

EDMA3_RM_GblErrCallbackParams Struct Reference
[EDMA3 Resource Manager Data Structures]

Global Error Callback parameters. More...

#include <edma3_rm.h>

Data Fields

EDMA3_RM_GblErrCallback gblerrCb
void * gblerrData

Detailed Description

Global Error Callback parameters.

Consists of the Callback function and the data to be passed to it.

Field Documentation

EDMA3_RM_GblErrCallback EDMA3_RM_GblErrCallbackParams::gblerrCb

Instance wide callback function to catch non-channel specific errors.

void* EDMA3_RM_GblErrCallbackParams::gblerrData

Application data to be passed back to the Global Error callback

The documentation for this struct was generated from the following file:
  • edma3_rm.h


EDMA3 Resource Manager: EDMA3_RM_GblXbarToChanConfigParams Struct Reference

EDMA3_RM_GblXbarToChanConfigParams Struct Reference
[EDMA3 Resource Manager Advanced APIs]

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...

#include <edma3_rm.h>

Data Fields

int32_t dmaMapXbarToChan [EDMA3_RM_MAX_XBAR_EVENTS]
Mapping from DMA channels to Hardware Events.

Detailed Description

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.

This configuration structure is used to specify the EDMA3 Driver global settings, specific to the SoC. This configuraion structure provides the details of the mapping of cross bar events to available channels. This configuration information is SoC specific and could be provided by the user at run-time while creating the EDMA3 Driver Object, using API EDMA3_RM_initXbarEventMap. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, incase it is available.

Field Documentation

int32_t EDMA3_RM_GblXbarToChanConfigParams::dmaMapXbarToChan[EDMA3_RM_MAX_XBAR_EVENTS]

Mapping from DMA channels to Hardware Events.

Each element in this array corresponds to one cross bar event and tells whether this event is mapped to any DMA channel. That is whether any free or unused DMA channel can be mapped to this event. -1 means the cross bar event is not mapped to any DMA channel; Any number from 0 to 63 means this event is mapped to specified channel. All channels need not be mapped, some can be free also. For the cross bar event mapped to DMA channel, appropriate Control Config register of TPCC event mux register should be configured.

The documentation for this struct was generated from the following file:
  • edma3_rm.h


EDMA3 Resource Manager: EDMA3_RM_Instance Struct Reference

EDMA3_RM_Instance Struct Reference

EDMA3 RM Instance Specific Configuration Structure. More...

#include <edma3resmgr.h>

Data Fields

EDMA3_RM_Param initParam
EDMA3_CCRL_ShadowRegs * | shadowRegs
EDMA3_RM_Obj * pResMgrObjHandle
unsigned int | avlblDmaChannels [EDMA3_MAX_DMA_CHAN_DWRDS]
unsigned int | avlblQdmaChannels [EDMA3_MAX_QDMA_CHAN_DWRDS]
unsigned int | avlblPaRAMSets [EDMA3_MAX_PARAM_DWRDS]
unsigned int | avlblTccs [EDMA3_MAX_TCC_DWRDS]
unsigned int | paramInitRequired
unsigned int | regModificationRequired
EDMA3_RM_mapXbarEvtToChan mapXbarToChan
EDMA3_RM_xbarConfigScr configScrMapXbarToEvt
EDMA3_RM_GblXbarToChanConfigParams rmXbarToEvtMapConfig

Detailed Description

EDMA3 RM Instance Specific Configuration Structure.

Used to maintain information of the EDMA3 Res Mgr instances. One such storage exists for each instance of the EDMA3 Res Mgr.

Maximum EDMA3_MAX_RM_INSTANCES instances are allowed for each EDMA3 hardware instance, for same or different shadow regions.

Field Documentation

EDMA3_RM_Param EDMA3_RM_Instance::initParam

Configuration such as region id, IsMaster, Callback function This configuration is passed to the "Open" API. For a single EDMA3 HW controller, there can be EDMA3_MAX_REGIONS different instances tied to different regions.

EDMA3_CCRL_ShadowRegs* EDMA3_RM_Instance::shadowRegs

Pointer to appropriate Shadow Register region of CC Registers

EDMA3_RM_Obj* EDMA3_RM_Instance::pResMgrObjHandle

Pointer to the EDMA3 RM Object (HW specific) opened by RM instance.

unsigned int EDMA3_RM_Instance::avlblDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]

Available DMA Channels to the RM Instance

unsigned int EDMA3_RM_Instance::avlblQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]

Available QDMA Channels to the RM Instance

unsigned int EDMA3_RM_Instance::avlblPaRAMSets[EDMA3_MAX_PARAM_DWRDS]

Available PaRAM Sets to the RM Instance

unsigned int EDMA3_RM_Instance::avlblTccs[EDMA3_MAX_TCC_DWRDS]

Available TCCs to the RM Instance

unsigned int EDMA3_RM_Instance::paramInitRequired

Sometimes, PaRAM clearing is not required for some particular RM Instances. In that case, PaRAM Sets allocated will NOT be cleared before allocating to any particular user. It is the responsibility of user to program it accordingly, without assuming anything for a specific field because the PaRAM Set might contain junk values. Not programming it fully might result in erroneous behavior. On the other hand, RM instances can also use this variable to get the PaRAM Sets cleared before allocating them to the specific user. User can program only the selected fields in this case.

Value '0' : PaRAM Sets will NOT be cleared during their allocation. Value '1' : PaRAM Sets will be cleared during their allocation.

This value can be modified using the IOCTL commands.

unsigned int EDMA3_RM_Instance::regModificationRequired

Sometimes, global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets should not be modified during EDMA3_RM_allocLogicalChannel (), for some particular RM Instances. In that case, it is the responsibility of user to program them accordingly, when needed, without assuming anything because they might contain junk values. Not programming the registers/PaRAMs fully might result in erroneous behavior. On the other hand, RM instances can also use this variable to get the global registers and PaRAM Sets minimally programmed before allocating them to the specific user. User can program only the remaining fields in this case.

Value '0' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will NOT be programmed during their allocation. Value '1' : EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be programmed during their allocation.

This value can be modified using the IOCTL commands.

EDMA3_RM_mapXbarEvtToChan EDMA3_RM_Instance::mapXbarToChan

Pointer to the user defined function for mapping cross bar events to channel.

EDMA3_RM_xbarConfigScr EDMA3_RM_Instance::configScrMapXbarToEvt

Pointer to the user defined function for configuring the cross bar events to appropriate channel in the Control Config TPCC Event Config registers.

EDMA3_RM_GblXbarToChanConfigParams EDMA3_RM_Instance::rmXbarToEvtMapConfig

Pointer to the configuration data structure for mapping cross bar events to channel.

The documentation for this struct was generated from the following file:
  • edma3resmgr.h


EDMA3 Resource Manager: EDMA3_RM_InstanceInitConfig Struct Reference

EDMA3_RM_InstanceInitConfig Struct Reference
[EDMA3 Resource Manager Data Structures]

Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information. More...

#include <edma3_rm.h>

Data Fields

uint32_t | ownPaRAMSets [EDMA3_MAX_PARAM_DWRDS]
uint32_t | ownDmaChannels [EDMA3_MAX_DMA_CHAN_DWRDS]
uint32_t | ownQdmaChannels [EDMA3_MAX_QDMA_CHAN_DWRDS]
uint32_t | ownTccs [EDMA3_MAX_TCC_DWRDS]
uint32_t | resvdPaRAMSets [EDMA3_MAX_PARAM_DWRDS]
Reserved PaRAM Sets.
uint32_t | resvdDmaChannels [EDMA3_MAX_DMA_CHAN_DWRDS]
Reserved DMA channels.
uint32_t | resvdQdmaChannels [EDMA3_MAX_QDMA_CHAN_DWRDS]
Reserved QDMA channels.
uint32_t | resvdTccs [EDMA3_MAX_TCC_DWRDS]
Reserved TCCs.

Detailed Description

Init-time Region Specific Configuration structure for EDMA3 RM, to provide region specific Information.

This configuration structure is used to specify which EDMA3 resources are owned and reserved by the EDMA3 RM instance. This configuration structure is shadow region specific and will be provided by the user at run-time while calling EDMA3_RM_open ().

Owned resources: ****************

EDMA3 RM Instances are tied to different shadow regions and hence different masters. Regions could be:

a) ARM, b) DSP, c) IMCOP (Imaging Co-processor) etc.

User can assign each EDMA3 resource to a shadow region using this structure. In this way, user specifies which resources are owned by the specific EDMA3 RM Instance. This assignment should also ensure that the same resource is not assigned to more than one shadow regions (unless desired in that way). Any assignment not following the above mentioned approach may have catastrophic consequences.

Reserved resources: *******************

During EDMA3 RM initialization, user can reserve some of the EDMA3 resources for future use, by specifying which resources to reserve in the configuration data structure. These (critical) resources are reserved in advance so that they should not be allocated to someone else and thus could be used in future for some specific purpose.

User can request different EDMA3 resources using two methods: a) By passing the resource type and the actual resource id, b) By passing the resource type and ANY as resource id

For e.g. to request DMA channel 31, user will pass 31 as the resource id. But to request ANY available DMA channel (mainly used for memory-to-memory data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the resource id.

During initialization, user may have reserved some of the DMA channels for some specific purpose (mainly for peripherals using EDMA). These reserved DMA channels then will not be returned when user requests ANY as the resource id.

Same logic applies for QDMA channels and TCCs.

For PaRAM Set, there is one difference. If the DMA channels are one-to-one tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set for a particular DMA channel), EDMA3 RM automatically reserves all those PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would not be returned when user requests for ANY PaRAM Set (specifically for linking purpose). This is done in order to avoid allocating the PaRAM Set, tied to a particular DMA channel, for linking purpose. If this constraint is not there, that DMA channel thus could not be used at all, because of the unavailability of the desired PaRAM Set.

Field Documentation

uint32_t EDMA3_RM_InstanceInitConfig::ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS]

PaRAM Sets owned by the EDMA3 RM Instance.

uint32_t EDMA3_RM_InstanceInitConfig::ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]

DMA Channels owned by the EDMA3 RM Instance.

uint32_t EDMA3_RM_InstanceInitConfig::ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]

QDMA Channels owned by the EDMA3 RM Instance.

uint32_t EDMA3_RM_InstanceInitConfig::ownTccs[EDMA3_MAX_TCC_DWRDS]

TCCs owned by the EDMA3 RM Instance.

uint32_t EDMA3_RM_InstanceInitConfig::resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS]

Reserved PaRAM Sets.

PaRAM Sets reserved during initialization for future use. These will not be given when user requests for ANY available PaRAM Set using 'EDMA3_RM_PARAM_ANY' as resource/channel id.

uint32_t EDMA3_RM_InstanceInitConfig::resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]

Reserved DMA channels.

DMA channels reserved during initialization for future use. These will not be given when user requests for ANY available DMA channel using 'EDMA3_RM_DMA_CHANNEL_ANY' as resource/channel id.

uint32_t EDMA3_RM_InstanceInitConfig::resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]

Reserved QDMA channels.

QDMA channels reserved during initialization for future use. These will not be given when user requests for ANY available QDMA channel using 'EDMA3_RM_QDMA_CHANNEL_ANY' as resource/channel id.

uint32_t EDMA3_RM_InstanceInitConfig::resvdTccs[EDMA3_MAX_TCC_DWRDS]

Reserved TCCs.

TCCs reserved during initialization for future use. These will not be given when user requests for ANY available TCC using 'EDMA3_RM_TCC_ANY' as resource/channel id.

The documentation for this struct was generated from the following file:
  • edma3_rm.h


EDMA3 Resource Manager: EDMA3_RM_MiscParam Struct Reference

EDMA3_RM_MiscParam Struct Reference
[EDMA3 Resource Manager Data Structures]

Used to specify the miscellaneous options during Resource Manager Initialization. More...

#include <edma3_rm.h>

Data Fields

uint16_t | isSlave
uint16_t | param

Detailed Description

Used to specify the miscellaneous options during Resource Manager Initialization.

This configuration structure is used to specify some misc options while creating the RM Object. New options may also be added into this structure in future.

Field Documentation

uint16_t EDMA3_RM_MiscParam::isSlave

In a multi-master system (for e.g. ARM + DSP), this option is used to distinguish between Master and Slave. Only the Master is allowed to program the global EDMA3 registers (like Queue priority, Queue water- mark level, error registers etc).

uint16_t EDMA3_RM_MiscParam::param

For future use

The documentation for this struct was generated from the following file:
  • edma3_rm.h


EDMA3 Resource Manager: EDMA3_RM_Obj Struct Reference

EDMA3_RM_Obj Struct Reference

EDMA3 Hardware Instance Configuration Structure. More...

#include <edma3resmgr.h>

Data Fields

unsigned int | phyCtrllerInstId
EDMA3_RM_ObjState | state
unsigned int | numOpens
EDMA3_RM_GblConfigParams gblCfgParams
Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.

Detailed Description

EDMA3 Hardware Instance Configuration Structure.

Used to maintain information of the EDMA3 HW configuration. One such storage exists for each instance of the EDMA 3 HW.

Field Documentation

unsigned int EDMA3_RM_Obj::phyCtrllerInstId

HW Instance Id of the EDMA3 Controller

EDMA3_RM_ObjState EDMA3_RM_Obj::state

State information of the Resource Manager object

unsigned int EDMA3_RM_Obj::numOpens

Number of active opens of RM Instances

EDMA3_RM_GblConfigParams EDMA3_RM_Obj::gblCfgParams

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.

This configuration will can be provided by the user at run-time, while calling EDMA3_RM_create().

The documentation for this struct was generated from the following file:
  • edma3resmgr.h


EDMA3 Resource Manager: EDMA3_RM_Param Struct Reference

EDMA3_RM_Param Struct Reference
[EDMA3 Resource Manager Data Structures]

Used to Initialize the Resource Manager Instance. More...

#include <edma3_rm.h>

Data Fields

EDMA3_RM_RegionId regionId
uint32_t | isMaster
EDMA3_RM_InstanceInitConfig * rmInstInitConfig
void * | rmSemHandle
uint32_t | regionInitEnable
EDMA3_RM_GblErrCallbackParams gblerrCbParams

Detailed Description

Used to Initialize the Resource Manager Instance.

This configuration structure is used to initialize the EDMA3 RM Instance. This configuration information is passed while opening the RM instance.

Field Documentation

EDMA3_RM_RegionId EDMA3_RM_Param::regionId

Shadow Region Identification

uint32_t EDMA3_RM_Param::isMaster

It tells whether the EDMA3 RM instance is Master or not. Only the shadow region associated with this master instance will receive the EDMA3 interrupts (if enabled).

EDMA3_RM_InstanceInitConfig* EDMA3_RM_Param::rmInstInitConfig

EDMA3 resources related shadow region specific information. Which all EDMA3 resources are owned and reserved by this particular instance are told in this configuration structure. User can also pass this structure as NULL. In that case, default static configuration would be taken from the platform specific configuration files (part of the Resource Manager), if available.

void* EDMA3_RM_Param::rmSemHandle

EDMA3 RM Instance specific semaphore handle. Used to share resources (DMA/QDMA channels, PaRAM Sets, TCCs etc) among different users.

uint32_t EDMA3_RM_Param::regionInitEnable

Whether initialization of Region Specific Registers is required or not?

EDMA3_RM_GblErrCallbackParams EDMA3_RM_Param::gblerrCbParams

Instance wide Global Error callback parameters

The documentation for this struct was generated from the following file:
  • edma3_rm.h


EDMA3 Resource Manager: EDMA3_RM_ParamentryRegs Struct Reference

EDMA3_RM_ParamentryRegs Struct Reference
[EDMA3 Resource Manager Data Structures]

EDMA3 PaRAM Set. More...

#include <edma3_rm.h>

Data Fields

volatile uint32_t | OPT
volatile uint32_t | SRC
Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
volatile uint32_t | A_B_CNT
volatile uint32_t | DST
Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0.
volatile uint32_t | SRC_DST_BIDX
volatile uint32_t | LINK_BCNTRLD
Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits).
volatile uint32_t | SRC_DST_CIDX
Index between consecutive frames of a Source Block (SRCCIDX) (16 bits) and Index between consecutive frames of a Dest Block (DSTCIDX) (16 bits).
volatile uint32_t | CCNT
Number of Frames in a block (CCNT) (16 bits).

Detailed Description

EDMA3 PaRAM Set.

This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual PaRAM words.

It could be used by the advanced users to program the PaRAM Set directly, without using any API.

Field Documentation

volatile uint32_t EDMA3_RM_ParamentryRegs::OPT

OPT field of PaRAM Set

volatile uint32_t EDMA3_RM_ParamentryRegs::A_B_CNT

Number of bytes in each Array (ACNT) (16 bits) and Number of Arrays in each Frame (BCNT) (16 bits).

volatile uint32_t EDMA3_RM_ParamentryRegs::SRC_DST_BIDX

Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and Index between consec. arrays of a Destination Frame (DSTBIDX) (16 bits).

If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.

If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes

volatile uint32_t EDMA3_RM_ParamentryRegs::LINK_BCNTRLD

Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits).

Link field must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking.

B count reload field is relevant only for A-sync transfers.

The documentation for this struct was generated from the following file:
  • edma3_rm.h


EDMA3 Resource Manager: EDMA3_RM_PaRAMRegs Struct Reference

EDMA3_RM_PaRAMRegs Struct Reference
[EDMA3 Resource Manager Data Structures]

EDMA3 PaRAM Set in User Configurable format. More...

#include <edma3_rm.h>

Data Fields

volatile uint32_t | opt
volatile uint32_t | srcAddr
Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
volatile uint16_t | aCnt
Number of bytes in each Array (ACNT).
volatile uint16_t | bCnt
Number of Arrays in each Frame (BCNT).
volatile uint32_t | destAddr
Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0.
volatile int16_t | srcBIdx
Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.
volatile int16_t | destBIdx
Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes.
volatile uint16_t | linkAddr
Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers.
volatile uint16_t | bCntReload
Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers.
volatile int16_t | srcCIdx
Index between consecutive frames of a Source Block (SRCCIDX).
volatile int16_t | destCIdx
Index between consecutive frames of a Dest Block (DSTCIDX).
volatile uint16_t | cCnt
Number of Frames in a block (CCNT).
volatile int16_t | reserved
Reserved.

Detailed Description

EDMA3 PaRAM Set in User Configurable format.

This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual fields.

Field Documentation

volatile uint32_t EDMA3_RM_PaRAMRegs::opt

OPT field of PaRAM Set

The documentation for this struct was generated from the following file:
  • edma3_rm.h


EDMA3 Resource Manager: EDMA3_RM_ResDesc Struct Reference

EDMA3_RM_ResDesc Struct Reference
[EDMA3 Resource Manager Data Structures]

Handle to a Resource. More...

#include <edma3_rm.h>

Data Fields

uint32_t resId
EDMA3_RM_ResType type

Detailed Description

Handle to a Resource.

Field Documentation

uint32_t EDMA3_RM_ResDesc::resId

Resource Id Range of resId values : As an example, for resource Type = EDMA3_RM_RES_DMA_CHANNEL, resId can take values from 0 to EDMA3_MAX_DMA_CH Or resId can take the value EDMA3_RM_RES_ANY.

EDMA3_RM_ResType EDMA3_RM_ResDesc::type

Resource Type

The documentation for this struct was generated from the following file:
  • edma3_rm.h


EDMA3 Resource Manager: EDMA3_RM_TccCallbackParams Struct Reference

EDMA3_RM_TccCallbackParams Struct Reference

TCC Callback - Caters to channel specific status reporting. More...

#include <edma3resmgr.h>

Data Fields

EDMA3_RM_TccCallback tccCb
void * cbData

Detailed Description

TCC Callback - Caters to channel specific status reporting.

Field Documentation

EDMA3_RM_TccCallback EDMA3_RM_TccCallbackParams::tccCb

Callback function

void* EDMA3_RM_TccCallbackParams::cbData

Callback data, passed to the Callback function

The documentation for this struct was generated from the following file:
  • edma3resmgr.h


EDMA3 Resource Manager: Data Fields

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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- a -

  • A_B_CNT : EDMA3_RM_ParamentryRegs
  • aCnt : EDMA3_RM_PaRAMRegs
  • avlblDmaChannels : EDMA3_RM_Instance
  • avlblPaRAMSets : EDMA3_RM_Instance
  • avlblQdmaChannels : EDMA3_RM_Instance
  • avlblTccs : EDMA3_RM_Instance

- b -

  • bCnt : EDMA3_RM_PaRAMRegs
  • bCntReload : EDMA3_RM_PaRAMRegs

- c -

  • cbData : EDMA3_RM_TccCallbackParams
  • ccError : EDMA3_RM_GblConfigParams
  • cCnt : EDMA3_RM_PaRAMRegs
  • CCNT : EDMA3_RM_ParamentryRegs
  • configScrMapXbarToEvt : EDMA3_RM_Instance

- d -

  • destAddr : EDMA3_RM_PaRAMRegs
  • destBIdx : EDMA3_RM_PaRAMRegs
  • destCIdx : EDMA3_RM_PaRAMRegs
  • dmaChannelHwEvtMap : EDMA3_RM_GblConfigParams
  • dmaChannelPaRAMMap : EDMA3_RM_GblConfigParams
  • dmaChannelTccMap : EDMA3_RM_GblConfigParams
  • dmaChPaRAMMapExists : EDMA3_RM_GblConfigParams
  • dmaMapXbarToChan : EDMA3_RM_GblXbarToChanConfigParams
  • DST : EDMA3_RM_ParamentryRegs

- e -

  • evtQPri : EDMA3_RM_GblConfigParams
  • evtQueueWaterMarkLvl : EDMA3_RM_GblConfigParams

- g -

  • gblCfgParams : EDMA3_RM_Obj
  • gblerrCb : EDMA3_RM_GblErrCallbackParams
  • gblerrCbParams : EDMA3_RM_Param
  • gblerrData : EDMA3_RM_GblErrCallbackParams
  • globalRegs : EDMA3_RM_GblConfigParams

- i -

  • initParam : EDMA3_RM_Instance
  • isMaster : EDMA3_RM_Param
  • isSlave : EDMA3_RM_MiscParam

- l -

  • LINK_BCNTRLD : EDMA3_RM_ParamentryRegs
  • linkAddr : EDMA3_RM_PaRAMRegs

- m -

  • mapXbarToChan : EDMA3_RM_Instance
  • memProtectionExists : EDMA3_RM_GblConfigParams

- n -

  • numDmaChannels : EDMA3_RM_GblConfigParams
  • numEvtQueue : EDMA3_RM_GblConfigParams
  • numOpens : EDMA3_RM_Obj
  • numPaRAMSets : EDMA3_RM_GblConfigParams
  • numQdmaChannels : EDMA3_RM_GblConfigParams
  • numRegions : EDMA3_RM_GblConfigParams
  • numTccs : EDMA3_RM_GblConfigParams
  • numTcs : EDMA3_RM_GblConfigParams

- o -

  • OPT : EDMA3_RM_ParamentryRegs
  • opt : EDMA3_RM_PaRAMRegs
  • ownDmaChannels : EDMA3_RM_InstanceInitConfig
  • ownPaRAMSets : EDMA3_RM_InstanceInitConfig
  • ownQdmaChannels : EDMA3_RM_InstanceInitConfig
  • ownTccs : EDMA3_RM_InstanceInitConfig

- p -

  • param : EDMA3_RM_MiscParam
  • paRAMId : EDMA3_RM_ChBoundResources
  • paramInitRequired : EDMA3_RM_Instance
  • phyCtrllerInstId : EDMA3_RM_Obj
  • pResMgrObjHandle : EDMA3_RM_Instance

- r -

  • regionId : EDMA3_RM_Param
  • regionInitEnable : EDMA3_RM_Param
  • regModificationRequired : EDMA3_RM_Instance
  • reserved : EDMA3_RM_PaRAMRegs
  • resId : EDMA3_RM_ResDesc
  • resvdDmaChannels : EDMA3_RM_InstanceInitConfig
  • resvdPaRAMSets : EDMA3_RM_InstanceInitConfig
  • resvdQdmaChannels : EDMA3_RM_InstanceInitConfig
  • resvdTccs : EDMA3_RM_InstanceInitConfig
  • rmInstInitConfig : EDMA3_RM_Param
  • rmSemHandle : EDMA3_RM_Param
  • rmXbarToEvtMapConfig : EDMA3_RM_Instance

- s -

  • shadowRegs : EDMA3_RM_Instance
  • SRC : EDMA3_RM_ParamentryRegs
  • SRC_DST_BIDX : EDMA3_RM_ParamentryRegs
  • SRC_DST_CIDX : EDMA3_RM_ParamentryRegs
  • srcAddr : EDMA3_RM_PaRAMRegs
  • srcBIdx : EDMA3_RM_PaRAMRegs
  • srcCIdx : EDMA3_RM_PaRAMRegs
  • state : EDMA3_RM_Obj

- t -

  • tcc : EDMA3_RM_ChBoundResources
  • tccCb : EDMA3_RM_TccCallbackParams
  • tcDefaultBurstSize : EDMA3_RM_GblConfigParams
  • tcError : EDMA3_RM_GblConfigParams
  • tcRegs : EDMA3_RM_GblConfigParams
  • type : EDMA3_RM_ResDesc

- x -

  • xferCompleteInt : EDMA3_RM_GblConfigParams


EDMA3 Resource Manager: Alphabetical List

Data Structure Index

E
E
EDMA3_RM_GblXbarToChanConfigParams EDMA3_RM_Obj EDMA3_RM_PaRAMRegs
EDMA3_RM_ChBoundResources EDMA3_RM_Instance EDMA3_RM_Param EDMA3_RM_ResDesc
EDMA3_RM_GblConfigParams EDMA3_RM_InstanceInitConfig EDMA3_RM_ParamentryRegs EDMA3_RM_TccCallbackParams
EDMA3_RM_GblErrCallbackParams EDMA3_RM_MiscParam
E
Generated on Mon Feb 14 18:31:18 2011 for EDMA3 Resource Manager by doxygen 1.6.1


EDMA3 Resource Manager: Data Fields - Variables

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- a -

  • A_B_CNT : EDMA3_RM_ParamentryRegs
  • aCnt : EDMA3_RM_PaRAMRegs
  • avlblDmaChannels : EDMA3_RM_Instance
  • avlblPaRAMSets : EDMA3_RM_Instance
  • avlblQdmaChannels : EDMA3_RM_Instance
  • avlblTccs : EDMA3_RM_Instance

- b -

  • bCnt : EDMA3_RM_PaRAMRegs
  • bCntReload : EDMA3_RM_PaRAMRegs

- c -

  • cbData : EDMA3_RM_TccCallbackParams
  • ccError : EDMA3_RM_GblConfigParams
  • cCnt : EDMA3_RM_PaRAMRegs
  • CCNT : EDMA3_RM_ParamentryRegs
  • configScrMapXbarToEvt : EDMA3_RM_Instance

- d -

  • destAddr : EDMA3_RM_PaRAMRegs
  • destBIdx : EDMA3_RM_PaRAMRegs
  • destCIdx : EDMA3_RM_PaRAMRegs
  • dmaChannelHwEvtMap : EDMA3_RM_GblConfigParams
  • dmaChannelPaRAMMap : EDMA3_RM_GblConfigParams
  • dmaChannelTccMap : EDMA3_RM_GblConfigParams
  • dmaChPaRAMMapExists : EDMA3_RM_GblConfigParams
  • dmaMapXbarToChan : EDMA3_RM_GblXbarToChanConfigParams
  • DST : EDMA3_RM_ParamentryRegs

- e -

  • evtQPri : EDMA3_RM_GblConfigParams
  • evtQueueWaterMarkLvl : EDMA3_RM_GblConfigParams

- g -

  • gblCfgParams : EDMA3_RM_Obj
  • gblerrCb : EDMA3_RM_GblErrCallbackParams
  • gblerrCbParams : EDMA3_RM_Param
  • gblerrData : EDMA3_RM_GblErrCallbackParams
  • globalRegs : EDMA3_RM_GblConfigParams

- i -

  • initParam : EDMA3_RM_Instance
  • isMaster : EDMA3_RM_Param
  • isSlave : EDMA3_RM_MiscParam

- l -

  • LINK_BCNTRLD : EDMA3_RM_ParamentryRegs
  • linkAddr : EDMA3_RM_PaRAMRegs

- m -

  • mapXbarToChan : EDMA3_RM_Instance
  • memProtectionExists : EDMA3_RM_GblConfigParams

- n -

  • numDmaChannels : EDMA3_RM_GblConfigParams
  • numEvtQueue : EDMA3_RM_GblConfigParams
  • numOpens : EDMA3_RM_Obj
  • numPaRAMSets : EDMA3_RM_GblConfigParams
  • numQdmaChannels : EDMA3_RM_GblConfigParams
  • numRegions : EDMA3_RM_GblConfigParams
  • numTccs : EDMA3_RM_GblConfigParams
  • numTcs : EDMA3_RM_GblConfigParams

- o -

  • OPT : EDMA3_RM_ParamentryRegs
  • opt : EDMA3_RM_PaRAMRegs
  • ownDmaChannels : EDMA3_RM_InstanceInitConfig
  • ownPaRAMSets : EDMA3_RM_InstanceInitConfig
  • ownQdmaChannels : EDMA3_RM_InstanceInitConfig
  • ownTccs : EDMA3_RM_InstanceInitConfig

- p -

  • param : EDMA3_RM_MiscParam
  • paRAMId : EDMA3_RM_ChBoundResources
  • paramInitRequired : EDMA3_RM_Instance
  • phyCtrllerInstId : EDMA3_RM_Obj
  • pResMgrObjHandle : EDMA3_RM_Instance

- r -

  • regionId : EDMA3_RM_Param
  • regionInitEnable : EDMA3_RM_Param
  • regModificationRequired : EDMA3_RM_Instance
  • reserved : EDMA3_RM_PaRAMRegs
  • resId : EDMA3_RM_ResDesc
  • resvdDmaChannels : EDMA3_RM_InstanceInitConfig
  • resvdPaRAMSets : EDMA3_RM_InstanceInitConfig
  • resvdQdmaChannels : EDMA3_RM_InstanceInitConfig
  • resvdTccs : EDMA3_RM_InstanceInitConfig
  • rmInstInitConfig : EDMA3_RM_Param
  • rmSemHandle : EDMA3_RM_Param
  • rmXbarToEvtMapConfig : EDMA3_RM_Instance

- s -

  • shadowRegs : EDMA3_RM_Instance
  • SRC : EDMA3_RM_ParamentryRegs
  • SRC_DST_BIDX : EDMA3_RM_ParamentryRegs
  • SRC_DST_CIDX : EDMA3_RM_ParamentryRegs
  • srcAddr : EDMA3_RM_PaRAMRegs
  • srcBIdx : EDMA3_RM_PaRAMRegs
  • srcCIdx : EDMA3_RM_PaRAMRegs
  • state : EDMA3_RM_Obj

- t -

  • tcc : EDMA3_RM_ChBoundResources
  • tccCb : EDMA3_RM_TccCallbackParams
  • tcDefaultBurstSize : EDMA3_RM_GblConfigParams
  • tcError : EDMA3_RM_GblConfigParams
  • tcRegs : EDMA3_RM_GblConfigParams
  • type : EDMA3_RM_ResDesc

- x -

  • xferCompleteInt : EDMA3_RM_GblConfigParams


EDMA3 Resource Manager: Main Page

EDMA3 Resource Manager Documentation

02.11.01

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