EDMA3 Driver: Module Index

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Modules

Here is a list of all modules:
  • EDMA3 Driver
    • EDMA3 Driver Symbols
      • EDMA3 Driver Defines
      • EDMA3 Driver Enums
    • EDMA3 Driver Data Structures
    • EDMA3 Driver APIs
      • EDMA3 Driver Initialization APIs
      • EDMA3 Driver Basic APIs
      • EDMA3 Driver Advanced APIs
Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3 Driver

EDMA3 Driver

Modules

EDMA3 Driver Symbols
EDMA3 Driver Data Structures
EDMA3 Driver APIs

Detailed Description

Introduction

Overview

EDMA3 Driver is a functional library providing APIs for programming, scheduling and synchronizing with EDMA transfers and many more.

Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3 Driver Symbols

EDMA3 Driver Symbols
[EDMA3 Driver]

Modules

EDMA3 Driver Defines
EDMA3 Driver Enums
Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3 Driver Defines

EDMA3 Driver Defines
[EDMA3 Driver Symbols]

Defines

#define | EDMA3_DRV_E_BASE (-128)
EDMA3 Driver Error Codes Base define.
#define | EDMA3_DRV_E_OBJ_NOT_DELETED (EDMA3_DRV_E_BASE)
#define | EDMA3_DRV_E_OBJ_NOT_CLOSED (EDMA3_DRV_E_BASE-1)
#define | EDMA3_DRV_E_OBJ_NOT_OPENED (EDMA3_DRV_E_BASE-2)
#define | EDMA3_DRV_E_RM_CLOSE_FAIL (EDMA3_DRV_E_BASE-3)
#define | EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-4)
#define | EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-5)
#define | EDMA3_DRV_E_PARAM_SET_UNAVAIL (EDMA3_DRV_E_BASE-6)
#define | EDMA3_DRV_E_TCC_UNAVAIL (EDMA3_DRV_E_BASE-7)
#define | EDMA3_DRV_E_TCC_REGISTER_FAIL (EDMA3_DRV_E_BASE-8)
#define | EDMA3_DRV_E_CH_PARAM_BIND_FAIL (EDMA3_DRV_E_BASE-9)
#define | EDMA3_DRV_E_ADDRESS_NOT_ALIGNED (EDMA3_DRV_E_BASE-10)
#define | EDMA3_DRV_E_INVALID_PARAM (EDMA3_DRV_E_BASE-11)
#define | EDMA3_DRV_E_INVALID_STATE (EDMA3_DRV_E_BASE-12)
#define | EDMA3_DRV_E_INST_ALREADY_EXISTS (EDMA3_DRV_E_BASE-13)
#define | EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED (EDMA3_DRV_E_BASE-14)
#define | EDMA3_DRV_E_SEMAPHORE (EDMA3_DRV_E_BASE-15)
#define | EDMA3_DRV_E_INST_NOT_OPENED (EDMA3_DRV_E_BASE-16)
#define | EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP
#define | EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP
#define | EDMA3_DRV_DMA_CHANNEL_ANY 1002u
#define | EDMA3_DRV_QDMA_CHANNEL_ANY 1003u
#define | EDMA3_DRV_TCC_ANY 1004u
#define | EDMA3_DRV_LINK_CHANNEL 1005u
#define | EDMA3_DRV_LINK_CHANNEL_WITH_TCC 1006u
#define | EDMA3_DRV_QDMA_CHANNEL_0 (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
QDMA Channel defines.
#define | EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1u)
#define | EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2u)
#define | EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3u)
#define | EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4u)
#define | EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5u)
#define | EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6u)
#define | EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7u)
#define | EDMA3_DRV_CHANNEL_CLEAN 0x0000u
Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from EDMA3_DRV_getChannelStatus().
#define | EDMA3_DRV_CHANNEL_EVENT_PENDING 0x0001u
#define | EDMA3_DRV_CHANNEL_XFER_COMPLETE 0x0002u
#define | EDMA3_DRV_CHANNEL_ERR 0x0004u

Define Documentation

#define EDMA3_DRV_E_OBJ_NOT_DELETED (EDMA3_DRV_E_BASE)

EDMA3 Driver Object Not Deleted yet. So it cannot be created.

#define EDMA3_DRV_E_OBJ_NOT_CLOSED (EDMA3_DRV_E_BASE-1)

EDMA3 Driver Object Not Closed yet. So it cannot be deleted.

#define EDMA3_DRV_E_OBJ_NOT_OPENED (EDMA3_DRV_E_BASE-2)

EDMA3 Driver Object Not Opened yet So it cannot be closed.

#define EDMA3_DRV_E_RM_CLOSE_FAIL (EDMA3_DRV_E_BASE-3)

While closing EDMA3 Driver, Resource Manager Close Failed.

#define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-4)

The requested DMA Channel not available

#define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-5)

The requested QDMA Channel not available

#define EDMA3_DRV_E_PARAM_SET_UNAVAIL (EDMA3_DRV_E_BASE-6)

The requested PaRAM Set not available

#define EDMA3_DRV_E_TCC_UNAVAIL (EDMA3_DRV_E_BASE-7)

The requested TCC not available

#define EDMA3_DRV_E_TCC_REGISTER_FAIL (EDMA3_DRV_E_BASE-8)

The registration of TCC failed

#define EDMA3_DRV_E_CH_PARAM_BIND_FAIL (EDMA3_DRV_E_BASE-9)

The binding of Channel and PaRAM Set failed

#define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED (EDMA3_DRV_E_BASE-10)

The address of the memory location passed as argument is not properly aligned. It should be 32 bytes aligned.

#define EDMA3_DRV_E_INVALID_PARAM (EDMA3_DRV_E_BASE-11)

Invalid Parameter passed to API

#define EDMA3_DRV_E_INVALID_STATE (EDMA3_DRV_E_BASE-12)

Invalid State of EDMA3 HW Obj

#define EDMA3_DRV_E_INST_ALREADY_EXISTS (EDMA3_DRV_E_BASE-13)

EDMA3 Driver instance already exists for the specified region

#define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED (EDMA3_DRV_E_BASE-14)

FIFO width not supported by the requested TC

#define EDMA3_DRV_E_SEMAPHORE (EDMA3_DRV_E_BASE-15)

Semaphore related error

#define EDMA3_DRV_E_INST_NOT_OPENED (EDMA3_DRV_E_BASE-16)

EDMA3 Driver Instance does not exist, it is not opened yet

#define EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP

This define is used to specify that a DMA channel is NOT tied to any PaRAM Set and hence any available PaRAM Set could be used for that DMA channel. It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.

This value should mandatorily be used to mark DMA channels with no initial mapping to specific PaRAM Sets.

#define EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP

This define is used to specify that the DMA/QDMA channel is not tied to any TCC and hence any available TCC could be used for that DMA/QDMA channel. It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.

This value should mandatorily be used to mark DMA channels with no initial mapping to specific TCCs.

#define EDMA3_DRV_DMA_CHANNEL_ANY 1002u

Used to specify any available DMA Channel while requesting one. Used in the API EDMA3_DRV_requestChannel(). DMA channel from the pool of (owned && non_reserved && available_right_now) DMA channels will be chosen and returned.

#define EDMA3_DRV_QDMA_CHANNEL_ANY 1003u

Used to specify any available QDMA Channel while requesting one. Used in the API EDMA3_DRV_requestChannel(). QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned.

#define EDMA3_DRV_TCC_ANY 1004u

Used to specify any available TCC while requesting one. Used in the API EDMA3_DRV_requestChannel(), for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned.

#define EDMA3_DRV_LINK_CHANNEL 1005u

Used to specify any available PaRAM Set while requesting one. Used in the API EDMA3_DRV_requestChannel(), for Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned.

#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC 1006u

Used to specify any available PaRAM Set while requesting one. Used in the API EDMA3_DRV_requestChannel(), for Link channels. TCC code should also be specified and it will be used to populate the LINK field of the PaRAM Set. Without TCC code, the call will fail. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned.

#define EDMA3_DRV_QDMA_CHANNEL_0 (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)

QDMA Channel defines.

They should be used while requesting a specific QDMA channel in API EDMA3_DRV_requestChannel() as the argument (*pLch). Please note that these defines should ONLY be used in the API EDMA3_DRV_requestChannel() and not in any other API to perform further operations. They are only provided to allow user allocate specific QDMA channels. QDMA Channel 0

#define EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1u)

QDMA Channel 1

#define EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2u)

QDMA Channel 2

#define EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3u)

QDMA Channel 3

#define EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4u)

QDMA Channel 4

#define EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5u)

QDMA Channel 5

#define EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6u)

QDMA Channel 6

#define EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7u)

QDMA Channel 7

#define EDMA3_DRV_CHANNEL_CLEAN 0x0000u

Channel status defines These defines suggest the current state of the DMA / QDMA channel. They are used while returning the channel status from EDMA3_DRV_getChannelStatus().

Channel is clean; no pending event, completion interrupt and event miss interrupt

#define EDMA3_DRV_CHANNEL_EVENT_PENDING 0x0001u

Pending event is detected on the DMA channel

#define EDMA3_DRV_CHANNEL_XFER_COMPLETE 0x0002u

Transfer completion interrupt is detected on the DMA/QDMA channel

#define EDMA3_DRV_CHANNEL_ERR 0x0004u

Event miss error interrupt is detected on the DMA/QDMA channel

Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3 Driver Enums

EDMA3 Driver Enums
[EDMA3 Driver Symbols]

Enumerations

enum EDMA3_DRV_HW_CHANNEL_EVENT {
EDMA3_DRV_HW_CHANNEL_EVENT_0 = 0,
EDMA3_DRV_HW_CHANNEL_EVENT_1,
EDMA3_DRV_HW_CHANNEL_EVENT_2,
EDMA3_DRV_HW_CHANNEL_EVENT_3,
EDMA3_DRV_HW_CHANNEL_EVENT_4,
EDMA3_DRV_HW_CHANNEL_EVENT_5,
EDMA3_DRV_HW_CHANNEL_EVENT_6,
EDMA3_DRV_HW_CHANNEL_EVENT_7,
EDMA3_DRV_HW_CHANNEL_EVENT_8,
EDMA3_DRV_HW_CHANNEL_EVENT_9,
EDMA3_DRV_HW_CHANNEL_EVENT_10,
EDMA3_DRV_HW_CHANNEL_EVENT_11,
EDMA3_DRV_HW_CHANNEL_EVENT_12,
EDMA3_DRV_HW_CHANNEL_EVENT_13,
EDMA3_DRV_HW_CHANNEL_EVENT_14,
EDMA3_DRV_HW_CHANNEL_EVENT_15,
EDMA3_DRV_HW_CHANNEL_EVENT_16,
EDMA3_DRV_HW_CHANNEL_EVENT_17,
EDMA3_DRV_HW_CHANNEL_EVENT_18,
EDMA3_DRV_HW_CHANNEL_EVENT_19,
EDMA3_DRV_HW_CHANNEL_EVENT_20,
EDMA3_DRV_HW_CHANNEL_EVENT_21,
EDMA3_DRV_HW_CHANNEL_EVENT_22,
EDMA3_DRV_HW_CHANNEL_EVENT_23,
EDMA3_DRV_HW_CHANNEL_EVENT_24,
EDMA3_DRV_HW_CHANNEL_EVENT_25,
EDMA3_DRV_HW_CHANNEL_EVENT_26,
EDMA3_DRV_HW_CHANNEL_EVENT_27,
EDMA3_DRV_HW_CHANNEL_EVENT_28,
EDMA3_DRV_HW_CHANNEL_EVENT_29,
EDMA3_DRV_HW_CHANNEL_EVENT_30,
EDMA3_DRV_HW_CHANNEL_EVENT_31,
EDMA3_DRV_HW_CHANNEL_EVENT_32,
EDMA3_DRV_HW_CHANNEL_EVENT_33,
EDMA3_DRV_HW_CHANNEL_EVENT_34,
EDMA3_DRV_HW_CHANNEL_EVENT_35,
EDMA3_DRV_HW_CHANNEL_EVENT_36,
EDMA3_DRV_HW_CHANNEL_EVENT_37,
EDMA3_DRV_HW_CHANNEL_EVENT_38,
EDMA3_DRV_HW_CHANNEL_EVENT_39,
EDMA3_DRV_HW_CHANNEL_EVENT_40,
EDMA3_DRV_HW_CHANNEL_EVENT_41,
EDMA3_DRV_HW_CHANNEL_EVENT_42,
EDMA3_DRV_HW_CHANNEL_EVENT_43,
EDMA3_DRV_HW_CHANNEL_EVENT_44,
EDMA3_DRV_HW_CHANNEL_EVENT_45,
EDMA3_DRV_HW_CHANNEL_EVENT_46,
EDMA3_DRV_HW_CHANNEL_EVENT_47,
EDMA3_DRV_HW_CHANNEL_EVENT_48,
EDMA3_DRV_HW_CHANNEL_EVENT_49,
EDMA3_DRV_HW_CHANNEL_EVENT_50,
EDMA3_DRV_HW_CHANNEL_EVENT_51,
EDMA3_DRV_HW_CHANNEL_EVENT_52,
EDMA3_DRV_HW_CHANNEL_EVENT_53,
EDMA3_DRV_HW_CHANNEL_EVENT_54,
EDMA3_DRV_HW_CHANNEL_EVENT_55,
EDMA3_DRV_HW_CHANNEL_EVENT_56,
EDMA3_DRV_HW_CHANNEL_EVENT_57,
EDMA3_DRV_HW_CHANNEL_EVENT_58,
EDMA3_DRV_HW_CHANNEL_EVENT_59,
EDMA3_DRV_HW_CHANNEL_EVENT_60,
EDMA3_DRV_HW_CHANNEL_EVENT_61,
EDMA3_DRV_HW_CHANNEL_EVENT_62,
EDMA3_DRV_HW_CHANNEL_EVENT_63
}

DMA Channels assigned to different Hardware Events.

More...
enum EDMA3_DRV_OptField {
EDMA3_DRV_OPT_FIELD_SAM = 0,
EDMA3_DRV_OPT_FIELD_DAM = 1,
EDMA3_DRV_OPT_FIELD_SYNCDIM = 2,
EDMA3_DRV_OPT_FIELD_STATIC = 3,
EDMA3_DRV_OPT_FIELD_FWID = 4,
EDMA3_DRV_OPT_FIELD_TCCMODE = 5,
EDMA3_DRV_OPT_FIELD_TCC = 6,
EDMA3_DRV_OPT_FIELD_TCINTEN = 7,
EDMA3_DRV_OPT_FIELD_ITCINTEN = 8,
EDMA3_DRV_OPT_FIELD_TCCHEN = 9,
EDMA3_DRV_OPT_FIELD_ITCCHEN = 10
}

OPT Field Offset.

More...
enum EDMA3_DRV_AddrMode {
EDMA3_DRV_ADDR_MODE_INCR = 0,
EDMA3_DRV_ADDR_MODE_FIFO = 1
}

EDMA Addressing modes.

More...
enum EDMA3_DRV_SyncType {
EDMA3_DRV_SYNC_A = 0,
EDMA3_DRV_SYNC_AB = 1
}

EDMA Transfer Synchronization type.

More...
enum EDMA3_DRV_StaticMode {
EDMA3_DRV_STATIC_DIS = 0,
EDMA3_DRV_STATIC_EN = 1
}

True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted.

More...
enum EDMA3_DRV_FifoWidth {
EDMA3_DRV_W8BIT = 0,
EDMA3_DRV_W16BIT = 1,
EDMA3_DRV_W32BIT = 2,
EDMA3_DRV_W64BIT = 3,
EDMA3_DRV_W128BIT = 4,
EDMA3_DRV_W256BIT = 5
}

EDMA3 FIFO width.

More...
enum EDMA3_DRV_TccMode {
EDMA3_DRV_TCCMODE_NORMAL = 0,
EDMA3_DRV_TCCMODE_EARLY = 1
}

Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation.

More...
enum EDMA3_DRV_TcintEn {
EDMA3_DRV_TCINTEN_DIS = 0,
EDMA3_DRV_TCINTEN_EN = 1
}

Transfer complete interrupt enable.

More...
enum EDMA3_DRV_ItcintEn {
EDMA3_DRV_ITCINTEN_DIS = 0,
EDMA3_DRV_ITCINTEN_EN = 1
}

Intermediate Transfer complete interrupt enable.

More...
enum EDMA3_DRV_TcchEn {
EDMA3_DRV_TCCHEN_DIS = 0,
EDMA3_DRV_TCCHEN_EN = 1
}

Transfer complete chaining enable.

More...
enum EDMA3_DRV_ItcchEn {
EDMA3_DRV_ITCCHEN_DIS = 0,
EDMA3_DRV_ITCCHEN_EN = 1
}

Intermediate Transfer complete chaining enable.

More...
enum EDMA3_DRV_TrigMode {
EDMA3_DRV_TRIG_MODE_MANUAL = 0,
EDMA3_DRV_TRIG_MODE_QDMA = 1,
EDMA3_DRV_TRIG_MODE_EVENT = 2,
EDMA3_DRV_TRIG_MODE_NONE = 3
}

EDMA Trigger Mode Selection.

More...
enum EDMA3_DRV_PaRAMEntry {
EDMA3_DRV_PARAM_ENTRY_OPT = 0,
EDMA3_DRV_PARAM_ENTRY_SRC = 1,
EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2,
EDMA3_DRV_PARAM_ENTRY_DST = 3,
EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4,
EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5,
EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6,
EDMA3_DRV_PARAM_ENTRY_CCNT = 7
}

PaRAM Set Entry type.

More...
enum EDMA3_DRV_PaRAMField {
EDMA3_DRV_PARAM_FIELD_OPT = 0,
EDMA3_DRV_PARAM_FIELD_SRCADDR = 1,
EDMA3_DRV_PARAM_FIELD_ACNT = 2,
EDMA3_DRV_PARAM_FIELD_BCNT = 3,
EDMA3_DRV_PARAM_FIELD_DESTADDR = 4,
EDMA3_DRV_PARAM_FIELD_SRCBIDX = 5,
EDMA3_DRV_PARAM_FIELD_DESTBIDX = 6,
EDMA3_DRV_PARAM_FIELD_LINKADDR = 7,
EDMA3_DRV_PARAM_FIELD_BCNTRELOAD = 8,
EDMA3_DRV_PARAM_FIELD_SRCCIDX = 9,
EDMA3_DRV_PARAM_FIELD_DESTCIDX = 10,
EDMA3_DRV_PARAM_FIELD_CCNT = 11
}

PaRAM Set Field type.

More...
enum EDMA3_DRV_IoctlCmd { ,
EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION,
EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION
}

EDMA3 Driver IOCTL commands.

More...
enum EDMA3_DRV_Tc_Err {
EDMA3_DRV_TC_ERR_BUSERR_DIS = 0,
EDMA3_DRV_TC_ERR_BUSERR_EN,
EDMA3_DRV_TC_ERR_TRERR_DIS,
EDMA3_DRV_TC_ERR_TRERR_EN,
EDMA3_DRV_TC_ERR_MMRAERR_DIS,
EDMA3_DRV_TC_ERR_MMRAERR_EN,
EDMA3_DRV_TC_ERR_DIS,
EDMA3_DRV_TC_ERR_EN
}

TC Error Enablers.

More...

Enumeration Type Documentation

enum EDMA3_DRV_HW_CHANNEL_EVENT

DMA Channels assigned to different Hardware Events.

They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. for eg, the sample SoC specific file "soc.h" can have these defines:

define EDMA3_DRV_HW_CHANNEL_MCBSP_TX EDMA3_DRV_HW_CHANNEL_EVENT_2 define EDMA3_DRV_HW_CHANNEL_MCBSP_RX EDMA3_DRV_HW_CHANNEL_EVENT_3

These defines will be used by the MCBSP driver. The same event EDMA3_DRV_HW_CHANNEL_EVENT_2/3 could be mapped to some other peripheral also.

Enumerator:
EDMA3_DRV_HW_CHANNEL_EVENT_0

Channel assigned to EDMA3 Event 0

EDMA3_DRV_HW_CHANNEL_EVENT_1

Channel assigned to EDMA3 Event 1

EDMA3_DRV_HW_CHANNEL_EVENT_2

Channel assigned to EDMA3 Event 2

EDMA3_DRV_HW_CHANNEL_EVENT_3

Channel assigned to EDMA3 Event 3

EDMA3_DRV_HW_CHANNEL_EVENT_4

Channel assigned to EDMA3 Event 4

EDMA3_DRV_HW_CHANNEL_EVENT_5

Channel assigned to EDMA3 Event 5

EDMA3_DRV_HW_CHANNEL_EVENT_6

Channel assigned to EDMA3 Event 6

EDMA3_DRV_HW_CHANNEL_EVENT_7

Channel assigned to EDMA3 Event 7

EDMA3_DRV_HW_CHANNEL_EVENT_8

Channel assigned to EDMA3 Event 8

EDMA3_DRV_HW_CHANNEL_EVENT_9

Channel assigned to EDMA3 Event 9

EDMA3_DRV_HW_CHANNEL_EVENT_10

Channel assigned to EDMA3 Event 10

EDMA3_DRV_HW_CHANNEL_EVENT_11

Channel assigned to EDMA3 Event 11

EDMA3_DRV_HW_CHANNEL_EVENT_12

Channel assigned to EDMA3 Event 12

EDMA3_DRV_HW_CHANNEL_EVENT_13

Channel assigned to EDMA3 Event 13

EDMA3_DRV_HW_CHANNEL_EVENT_14

Channel assigned to EDMA3 Event 14

EDMA3_DRV_HW_CHANNEL_EVENT_15

Channel assigned to EDMA3 Event 15

EDMA3_DRV_HW_CHANNEL_EVENT_16

Channel assigned to EDMA3 Event 16

EDMA3_DRV_HW_CHANNEL_EVENT_17

Channel assigned to EDMA3 Event 17

EDMA3_DRV_HW_CHANNEL_EVENT_18

Channel assigned to EDMA3 Event 18

EDMA3_DRV_HW_CHANNEL_EVENT_19

Channel assigned to EDMA3 Event 19

EDMA3_DRV_HW_CHANNEL_EVENT_20

Channel assigned to EDMA3 Event 20

EDMA3_DRV_HW_CHANNEL_EVENT_21

Channel assigned to EDMA3 Event 21

EDMA3_DRV_HW_CHANNEL_EVENT_22

Channel assigned to EDMA3 Event 22

EDMA3_DRV_HW_CHANNEL_EVENT_23

Channel assigned to EDMA3 Event 23

EDMA3_DRV_HW_CHANNEL_EVENT_24

Channel assigned to EDMA3 Event 24

EDMA3_DRV_HW_CHANNEL_EVENT_25

Channel assigned to EDMA3 Event 25

EDMA3_DRV_HW_CHANNEL_EVENT_26

Channel assigned to EDMA3 Event 26

EDMA3_DRV_HW_CHANNEL_EVENT_27

Channel assigned to EDMA3 Event 27

EDMA3_DRV_HW_CHANNEL_EVENT_28

Channel assigned to EDMA3 Event 28

EDMA3_DRV_HW_CHANNEL_EVENT_29

Channel assigned to EDMA3 Event 29

EDMA3_DRV_HW_CHANNEL_EVENT_30

Channel assigned to EDMA3 Event 30

EDMA3_DRV_HW_CHANNEL_EVENT_31

Channel assigned to EDMA3 Event 31

EDMA3_DRV_HW_CHANNEL_EVENT_32

Channel assigned to EDMA3 Event 32

EDMA3_DRV_HW_CHANNEL_EVENT_33

Channel assigned to EDMA3 Event 33

EDMA3_DRV_HW_CHANNEL_EVENT_34

Channel assigned to EDMA3 Event 34

EDMA3_DRV_HW_CHANNEL_EVENT_35

Channel assigned to EDMA3 Event 35

EDMA3_DRV_HW_CHANNEL_EVENT_36

Channel assigned to EDMA3 Event 36

EDMA3_DRV_HW_CHANNEL_EVENT_37

Channel assigned to EDMA3 Event 37

EDMA3_DRV_HW_CHANNEL_EVENT_38

Channel assigned to EDMA3 Event 38

EDMA3_DRV_HW_CHANNEL_EVENT_39

Channel assigned to EDMA3 Event 39

EDMA3_DRV_HW_CHANNEL_EVENT_40

Channel assigned to EDMA3 Event 40

EDMA3_DRV_HW_CHANNEL_EVENT_41

Channel assigned to EDMA3 Event 41

EDMA3_DRV_HW_CHANNEL_EVENT_42

Channel assigned to EDMA3 Event 42

EDMA3_DRV_HW_CHANNEL_EVENT_43

Channel assigned to EDMA3 Event 43

EDMA3_DRV_HW_CHANNEL_EVENT_44

Channel assigned to EDMA3 Event 44

EDMA3_DRV_HW_CHANNEL_EVENT_45

Channel assigned to EDMA3 Event 45

EDMA3_DRV_HW_CHANNEL_EVENT_46

Channel assigned to EDMA3 Event 46

EDMA3_DRV_HW_CHANNEL_EVENT_47

Channel assigned to EDMA3 Event 47

EDMA3_DRV_HW_CHANNEL_EVENT_48

Channel assigned to EDMA3 Event 48

EDMA3_DRV_HW_CHANNEL_EVENT_49

Channel assigned to EDMA3 Event 49

EDMA3_DRV_HW_CHANNEL_EVENT_50

Channel assigned to EDMA3 Event 50

EDMA3_DRV_HW_CHANNEL_EVENT_51

Channel assigned to EDMA3 Event 51

EDMA3_DRV_HW_CHANNEL_EVENT_52

Channel assigned to EDMA3 Event 52

EDMA3_DRV_HW_CHANNEL_EVENT_53

Channel assigned to EDMA3 Event 53

EDMA3_DRV_HW_CHANNEL_EVENT_54

Channel assigned to EDMA3 Event 54

EDMA3_DRV_HW_CHANNEL_EVENT_55

Channel assigned to EDMA3 Event 55

EDMA3_DRV_HW_CHANNEL_EVENT_56

Channel assigned to EDMA3 Event 56

EDMA3_DRV_HW_CHANNEL_EVENT_57

Channel assigned to EDMA3 Event 57

EDMA3_DRV_HW_CHANNEL_EVENT_58

Channel assigned to EDMA3 Event 58

EDMA3_DRV_HW_CHANNEL_EVENT_59

Channel assigned to EDMA3 Event 59

EDMA3_DRV_HW_CHANNEL_EVENT_60

Channel assigned to EDMA3 Event 60

EDMA3_DRV_HW_CHANNEL_EVENT_61

Channel assigned to EDMA3 Event 61

EDMA3_DRV_HW_CHANNEL_EVENT_62

Channel assigned to EDMA3 Event 62

EDMA3_DRV_HW_CHANNEL_EVENT_63

Channel assigned to EDMA3 Event 63

enum EDMA3_DRV_OptField

OPT Field Offset.

Use this enum to set or get any of the Fields within an OPT of a Parameter RAM set.

Enumerator:
EDMA3_DRV_OPT_FIELD_SAM

Source addressing mode (INCR / FIFO) (Bit 0)

EDMA3_DRV_OPT_FIELD_DAM

Destination addressing mode (INCR / FIFO) (Bit 1)

EDMA3_DRV_OPT_FIELD_SYNCDIM

Transfer synchronization dimension (A-synchronized / AB-synchronized) (Bit 2)

EDMA3_DRV_OPT_FIELD_STATIC

The STATIC field PaRAM set is static/non-static? (Bit 3)

EDMA3_DRV_OPT_FIELD_FWID

FIFO Width. Applies if either SAM or DAM is set to FIFO mode. (Bitfield 8-10)

EDMA3_DRV_OPT_FIELD_TCCMODE

Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. (Bit 11)

EDMA3_DRV_OPT_FIELD_TCC

Transfer Complete Code (TCC). This 6-bit code is used to set the relevant bit in chaining enable register (CER[TCC]/CERH[TCC]) for chaining or in interrupt pending register (IPR[TCC]/IPRH[TCC]) for interrupts. (Bitfield 12-17)

EDMA3_DRV_OPT_FIELD_TCINTEN

Transfer complete interrupt enable/disable. (Bit 20)

EDMA3_DRV_OPT_FIELD_ITCINTEN

Intermediate transfer complete interrupt enable/disable. (Bit 21)

EDMA3_DRV_OPT_FIELD_TCCHEN

Transfer complete chaining enable/disable (Bit 22)

EDMA3_DRV_OPT_FIELD_ITCCHEN

Intermediate transfer completion chaining enable/disable (Bit 23)

enum EDMA3_DRV_AddrMode

EDMA Addressing modes.

The EDMA3 TC supports two addressing modes

  1. Increment transfer
  2. FIFO transfer

The SAM (Source Addressing Mode) and the DAM (Destination Addressing Mode) can be independently set to either of the two via the OPT register.

Enumerator:
EDMA3_DRV_ADDR_MODE_INCR

Increment (INCR) mode. Source addressing within an array increments. Source is not a FIFO.

EDMA3_DRV_ADDR_MODE_FIFO

FIFO mode. Source addressing within an array wraps around upon reaching FIFO width.

enum EDMA3_DRV_SyncType

EDMA Transfer Synchronization type.

Two types of Synchronization of transfers are possible

  1. A Synchronized
  2. AB Syncronized

A Sync

  1. Each Array is submitted as one TR
  2. (BCNT*CCNT) number of sync events are needed to completely service a PaRAM set. (Where BCNT = Num of Arrays in a Frame; CCNT = Num of Frames in a Block)
  3. (S/D)CIDX = (Addr of First array in next frame) minus (Addr of Last array in present frame) (Where CIDX is the Inter-Frame index)
  • AB Sync
    1. Each Frame is submitted as one TR
    2. Only CCNT number of sync events are needed to completely service a PaRAM set
    3. (S/D)CIDX = (Addr of First array in next frame) minus (Addr of First array of present frame)
Note:
ABC sync transfers can be achieved logically by chaining multiple AB sync transfers
Enumerator:
EDMA3_DRV_SYNC_A

A-synchronized. Each event triggers the transfer of a single array of ACNT bytes

EDMA3_DRV_SYNC_AB

AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes

enum EDMA3_DRV_StaticMode

True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted.

Enumerator:
EDMA3_DRV_STATIC_DIS

PaRAM set is not Static. PaRAM set is updated or linked after TR is submitted. A value of 0 should be used for DMA channels and for nonfinal transfers in a linked list of QDMA transfers

EDMA3_DRV_STATIC_EN

PaRAM set is Static. PaRAM set is not updated or linked after TR is submitted. A value of 1 should be used for isolated QDMA transfers or for the final transfer in a linked list of QDMA transfers.

enum EDMA3_DRV_FifoWidth

EDMA3 FIFO width.

The user can set the width of the FIFO using this enum. This is done via the OPT register. This is valid only if the EDMA3_DRV_ADDR_MODE_FIFO value is used for the enum EDMA3_DRV_AddrMode.

Enumerator:
EDMA3_DRV_W8BIT

FIFO width is 8-bit.

EDMA3_DRV_W16BIT

FIFO width is 16-bit.

EDMA3_DRV_W32BIT

FIFO width is 32-bit.

EDMA3_DRV_W64BIT

FIFO width is 64-bit.

EDMA3_DRV_W128BIT

FIFO width is 128-bit.

EDMA3_DRV_W256BIT

FIFO width is 256-bit.

enum EDMA3_DRV_TccMode

Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation.

Enumerator:
EDMA3_DRV_TCCMODE_NORMAL

A transfer is considered completed after transfer of data

EDMA3_DRV_TCCMODE_EARLY

A transfer is considered completed after the EDMA3CC submits a TR to the EDMA3TC. TC may still be transferring data when interrupt/chain is triggered.

enum EDMA3_DRV_TcintEn

Transfer complete interrupt enable.

Enumerator:
EDMA3_DRV_TCINTEN_DIS

Transfer complete interrupt is disabled

EDMA3_DRV_TCINTEN_EN

Transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on transfer completion (upon completion of the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1.

enum EDMA3_DRV_ItcintEn

Intermediate Transfer complete interrupt enable.

Enumerator:
EDMA3_DRV_ITCINTEN_DIS

Intermediate Transfer complete interrupt is disabled

EDMA3_DRV_ITCINTEN_EN

Intermediate transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on every intermediate transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1.

enum EDMA3_DRV_TcchEn

Transfer complete chaining enable.

Enumerator:
EDMA3_DRV_TCCHEN_DIS

Transfer complete chaining is disabled

EDMA3_DRV_TCCHEN_EN

Transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on final chained transfer completion (upon completion of the final / last TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified.

enum EDMA3_DRV_ItcchEn

Intermediate Transfer complete chaining enable.

Enumerator:
EDMA3_DRV_ITCCHEN_DIS

Intermediate Transfer complete chaining is disabled

EDMA3_DRV_ITCCHEN_EN

Intermediate transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on every intermediate chained transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified.

enum EDMA3_DRV_TrigMode

EDMA Trigger Mode Selection.

Use this enum to select the EDMA trigger mode while enabling the EDMA transfer

Enumerator:
EDMA3_DRV_TRIG_MODE_MANUAL

Set the Trigger mode to Manual . The CPU manually triggers a transfer by writing a 1 to the corresponding bit in the event set register (ESR/ESRH).

EDMA3_DRV_TRIG_MODE_QDMA

Set the Trigger mode to QDMA. A QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel parameter set (autotriggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered).

EDMA3_DRV_TRIG_MODE_EVENT

Set the Trigger mode to Event. Allows for a peripheral, system, or externally-generated event to trigger a transfer request.

EDMA3_DRV_TRIG_MODE_NONE

Used to specify the trigger mode NONE

enum EDMA3_DRV_PaRAMEntry

PaRAM Set Entry type.

Use this enum to set or get any of the 8 DWords(unsigned int) within a Parameter RAM set

Enumerator:
EDMA3_DRV_PARAM_ENTRY_OPT

The OPT field (Offset Address 0x0 Bytes)

EDMA3_DRV_PARAM_ENTRY_SRC

The SRC field (Offset Address 0x4 Bytes)

EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT

The (ACNT+BCNT) field (Offset Address 0x8 Bytes)

EDMA3_DRV_PARAM_ENTRY_DST

The DST field (Offset Address 0xC Bytes)

EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX

The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes)

EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD

The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes)

EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX

The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes)

EDMA3_DRV_PARAM_ENTRY_CCNT

The (CCNT+RSVD) field (Offset Address 0x1C Bytes)

enum EDMA3_DRV_PaRAMField

PaRAM Set Field type.

Use this enum to set or get any of the PaRAM set fields

Enumerator:
EDMA3_DRV_PARAM_FIELD_OPT

OPT field of PaRAM Set

EDMA3_DRV_PARAM_FIELD_SRCADDR

Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.

EDMA3_DRV_PARAM_FIELD_ACNT

Number of bytes in each Array (ACNT).

EDMA3_DRV_PARAM_FIELD_BCNT

Number of Arrays in each Frame (BCNT).

EDMA3_DRV_PARAM_FIELD_DESTADDR

Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address.

EDMA3_DRV_PARAM_FIELD_SRCBIDX

Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.

EDMA3_DRV_PARAM_FIELD_DESTBIDX

Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes.

EDMA3_DRV_PARAM_FIELD_LINKADDR

Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers.

EDMA3_DRV_PARAM_FIELD_BCNTRELOAD

Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers.

EDMA3_DRV_PARAM_FIELD_SRCCIDX

Index between consecutive frames of a Source Block (SRCCIDX).

EDMA3_DRV_PARAM_FIELD_DESTCIDX

Index between consecutive frames of a Dest Block (DSTCIDX).

EDMA3_DRV_PARAM_FIELD_CCNT

Number of Frames in a block (CCNT).

enum EDMA3_DRV_IoctlCmd

EDMA3 Driver IOCTL commands.

Enumerator:
EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION

PaRAM Sets will be cleared OR will not be cleared during allocation, depending upon this option.

For e.g., To clear the PaRAM Sets during allocation, cmdArg = (void *)1;

To NOT clear the PaRAM Sets during allocation, cmdArg = (void *)0;

For all other values, it will return error.

By default, PaRAM Sets will be cleared during allocation. Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources.

EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION

To check whether PaRAM Sets will be cleared or not during allocation. If the value read is '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation. For e.g., unsigned short isParamClearingDone; cmdArg =

enum EDMA3_DRV_Tc_Err

TC Error Enablers.

Use this enum to enable/disable the specific EDMA3 Transfer Controller Interrupts.

Enumerator:
EDMA3_DRV_TC_ERR_BUSERR_DIS

Interrupt disable for bus error

EDMA3_DRV_TC_ERR_BUSERR_EN

Interrupt enable for bus error

EDMA3_DRV_TC_ERR_TRERR_DIS

Interrupt disable for transfer request error

EDMA3_DRV_TC_ERR_TRERR_EN

Interrupt enable for transfer request error

EDMA3_DRV_TC_ERR_MMRAERR_DIS

Interrupt disable for MMR address error

EDMA3_DRV_TC_ERR_MMRAERR_EN

Interrupt enable for MMR address error

EDMA3_DRV_TC_ERR_DIS

Disable all TC error interrupts

EDMA3_DRV_TC_ERR_EN

Enable all TC error interrupts

Generated on Fri Jan 28 15:45:38 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3 Driver Data Structures

EDMA3 Driver Data Structures
[EDMA3 Driver]

Data Structures

struct | EDMA3_DRV_GblConfigParams
Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...
struct | EDMA3_DRV_InstanceInitConfig
Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information. More...
struct | EDMA3_DRV_InitConfig
Used to Initialize the EDMA3 Driver Instance. More...
struct | EDMA3_DRV_MiscParam
Used to specify the miscellaneous options during EDMA3 Driver Initialization. More...
struct | EDMA3_DRV_ChainOptions
Structure to be used to configure interrupt generation and chaining options. More...
struct | EDMA3_DRV_ParamentryRegs
EDMA3 PaRAM Set. More...
struct | EDMA3_DRV_PaRAMRegs
EDMA3 Parameter RAM Set in User Configurable format. More...
struct | EDMA3_DRV_EvtQuePriority
Event queue priorities setup. More...
Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3 Driver APIs

EDMA3 Driver APIs
[EDMA3 Driver]

Modules

EDMA3 Driver Initialization APIs
EDMA3 Driver Basic APIs
EDMA3 Driver Advanced APIs
Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3 Driver Initialization APIs

EDMA3 Driver Initialization APIs
[EDMA3 Driver APIs]

Functions

EDMA3_DRV_Result | EDMA3_DRV_create (unsigned int phyCtrllerInstId, const EDMA3_DRV_GblConfigParams *gblCfgParams, const void *miscParam)
Create EDMA3 Driver Object.
EDMA3_DRV_Result | EDMA3_DRV_delete (unsigned int phyCtrllerInstId, const void *param)
Delete EDMA3 Driver Object.
EDMA3_DRV_Handle | EDMA3_DRV_open (unsigned int phyCtrllerInstId, const EDMA3_DRV_InitConfig *initCfg, EDMA3_DRV_Result *errorCode)
Open EDMA3 Driver Instance.
EDMA3_DRV_Result | EDMA3_DRV_close (EDMA3_DRV_Handle hEdma, const void *param)
Close the EDMA3 Driver Instance.

Function Documentation

EDMA3_DRV_Result EDMA3_DRV_create | ( | unsigned int | phyCtrllerInstId,
 |  | const EDMA3_DRV_GblConfigParams * | gblCfgParams,
 |  | const void * | miscParam
 | ) |  |

Create EDMA3 Driver Object.

This API is used to create the EDMA3 Driver Object. It should be called only ONCE for each EDMA3 hardware instance.

Init-time Configuration structure for EDMA3 hardware is provided to pass the SoC specific information. This configuration information could be provided by the user at init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam' argument is NULL. User can avoid these registers' programming (in some specific use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration structure and passing this structure as the third argument (miscParam).

After successful completion of this API, Driver Object's state changes to EDMA3_DRV_CREATED from EDMA3_DRV_DELETED.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
gblCfgParams | [IN] SoC specific configuration structure for the EDMA3 Hardware.
miscParam | [IN] Misc configuration options provided in the structure 'EDMA3_DRV_MiscParam'. For default options, user can pass NULL in this argument.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
EDMA3_DRV_Result EDMA3_DRV_delete | ( | unsigned int | phyCtrllerInstId,
 |  | const void * | param
 | ) |  |

Delete EDMA3 Driver Object.

Use this API to delete the EDMA3 Driver Object. It should be called only ONCE for each EDMA3 hardware instance. It should be called ONLY after closing all the EDMA3 Driver Instances.

This API is used to delete the EDMA3 Driver Object. It should be called once for each EDMA3 hardware instance, ONLY after closing all the previously opened EDMA3 Driver Instances.

After successful completion of this API, Driver Object's state changes to EDMA3_DRV_DELETED.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Phy Controller Instance Id (Hardware instance id, starting from 0).
param | [IN] For possible future use.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
EDMA3_DRV_Handle EDMA3_DRV_open | ( | unsigned int | phyCtrllerInstId,
 |  | const EDMA3_DRV_InitConfig * | initCfg,
 |  | EDMA3_DRV_Result * | errorCode
 | ) |  |

Open EDMA3 Driver Instance.

This API is used to open an EDMA3 Driver Instance. It could be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_REGIONS instances are allowed for each EDMA3 hardware instance. Multiple instances on the same shadow region are NOT allowed.

Also, only ONE Master Driver Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled.

User could pass the instance specific configuration structure (initCfg.drvInstInitConfig) as a part of the 'initCfg' structure, during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

By default, this EDMA3 Driver instance will clear the PaRAM Sets while allocating them. To change the default behavior, user should use the IOCTL interface appropriately.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
initCfg | [IN] Used to Initialize the EDMA3 Driver Instance (Master or Slave).
errorCode | [OUT] Error code while opening DRV instance.
Returns:
EDMA3_DRV_Handle : If successfully opened, the API will return the associated driver's instance handle.
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant.
EDMA3_DRV_Result EDMA3_DRV_close | ( | EDMA3_DRV_Handle | hEdma,
 |  | const void * | param
 | ) |  |

Close the EDMA3 Driver Instance.

This API is used to close a previously opened EDMA3 Driver Instance.

Parameters:
hEdma | [IN] Handle to the previously opened EDMA3 Driver Instance.
param | [IN] For possible future use
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant.
Generated on Fri Jan 28 15:45:38 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3 Driver Basic APIs

EDMA3 Driver Basic APIs
[EDMA3 Driver APIs]

Functions

EDMA3_DRV_Result | EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)
Request a DMA/QDMA/Link channel.
EDMA3_DRV_Result | EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma, unsigned int channelId)
Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings.
EDMA3_DRV_Result | EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma, unsigned int channelId)
Disables the DMA Channel by clearing the Event Enable Register and clears Error Register & Secondary Event Register for a specific DMA channel.
EDMA3_DRV_Result | EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int newOptFieldVal)
Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.
EDMA3_DRV_Result | EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int *optFieldVal)
Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.
EDMA3_DRV_Result | EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)
DMA source parameters setup.
EDMA3_DRV_Result | EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)
DMA Destination parameters setup.
EDMA3_DRV_Result | EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)
DMA source index setup.
EDMA3_DRV_Result | EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)
DMA destination index setup.
EDMA3_DRV_Result | EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, EDMA3_DRV_SyncType syncType)
DMA transfer parameters setup.
EDMA3_DRV_Result | EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
Start EDMA transfer on the specified channel.
EDMA3_DRV_Result | EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
Disable DMA transfer on the specified channel.
EDMA3_DRV_Result | EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
Disable the event driven DMA channel or QDMA channel.

Function Documentation

EDMA3_DRV_Result EDMA3_DRV_requestChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int * | pLCh,
 |  | unsigned int * | pTcc,
 |  | EDMA3_RM_EventQueue | evtQueue,
 |  | EDMA3_RM_TccCallback | tccCb,
 |  | void * | cbData
 | ) |  |

Request a DMA/QDMA/Link channel.

Each channel (DMA/QDMA/Link) must be requested before initiating a DMA transfer on that channel.

This API is used to allocate a logical channel (DMA/QDMA/Link) along with the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are also allocated along with the requested channel. User can also specify a specific TCC which needs to be allocated with the DMA/QDMA channel or else can request any available TCC.

For Link channels, ONLY a PaRAM Set is allocated and the allocated PaRAM Set number is returned as the logical channel no. A TCC code can also be specified while making the request. This TCC code will be copied to the LINK field of the allocated PaRAM Set and will be associated with the Link channel.

User can request a specific logical channel - DMA, QDMA and Link, by passing the channel id in 'pLCh'. Note that the channel id is the same as the actual resource id in case of DMA channels and Link channels. For DMA channels, channel id lies between 0 and (max dma channels - 1). For Link channels, channel id lies between (max dma channels) and (max param sets - 1). To allocate specific QDMA channels, user SHOULD use the defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above.

User can also request ANY available logical channel by specifying the below mentioned values in '*pLCh': a) EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels b) EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and c) EDMA3_DRV_LINK_CHANNEL: For Link channels. Normally user should use this value to request link channels (PaRAM Sets used for linking purpose only), unless he wants to use some specific link channels (PaRAM Sets) which is also allowed. d) EDMA3_DRV_LINK_CHANNEL_WITH_TCC: For Link channels. User should use this value to request link channels with TCC code.

This API internally uses EDMA3_RM_allocResource () to allocate the desired resources (DMA/QDMA channel, PaRAM Set and TCC).

This API also registers a specific callback function, in case the same is provided, against the allocated TCC. To do this, this API calls EDMA3_RM_registerTccCb(), which is a part of the Resource Manager. Please note that the interrupts are enabled for the specific TCC only if callback function is provided. In the absence of this, the API assumes that the requested logical channel is going to be used in Poll mode environment.

For DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets the event queue for the channel allocated. The event queue needs to be specified by the user.

For DMA channel, it also sets the DCHMAP register, if required.

For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and enables the QDMA channel by writing to the QEESR register.

Parameters:
hEdma [IN] Handle to the previously opened Driver Instance.
pLCh [IN/OUT] Requested logical channel id. Examples:

  • EDMA3_DRV_HW_CHANNEL_EVENT_0
  • To request a DMA Master Channel mapped to EDMA Event 0.
  • EDMA3_DRV_DMA_CHANNEL_ANY
  • For requesting any DMA Master channel with no event mapping.
  • EDMA3_DRV_QDMA_CHANNEL_ANY
  • For requesting any QDMA Master channel
  • EDMA3_DRV_QDMA_CHANNEL_0
  • For requesting the QDMA Channel 0.
  • EDMA3_DRV_LINK_CHANNEL
  • For requesting a DMA Slave Channel,
  • to be linked to some other Master
  • channel.
  • EDMA3_DRV_LINK_CHANNEL_WITH_TCC
  • For requesting a DMA Slave Channel,
  • to be linked to some other Master
  • channel, with a TCC associated with it.

In case user passes a specific channel Id, pLCh value is left unchanged. In case user requests ANY available resource, the allocated channel id is returned in pLCh.

Note:
To request a PaRAM Set for the purpose of linking to another channel, call the function with

*pLCh = EDMA3_DRV_LINK_CHANNEL or EDMA3_DRV_LINK_CHANNEL_WITH_TCC

This function will update *pLCh with the allocated Link channel handle.

Parameters:
pTcc [IN/OUT] The channel number on which the completion/error interrupt is generated. Not used if user requested for a Link channel. Examples:

  • EDMA3_DRV_HW_CHANNEL_EVENT_0
  • To request TCC associated with
  • DMA Master Channel mapped to EDMA
  • event 0.
  • EDMA3_DRV_TCC_ANY
  • For requesting any TCC with no
  • channel mapping. In case user passes a specific TCC value, pTcc value is left unchanged. In case user requests ANY available TCC, the allocated one is returned in pTcc
Parameters:
evtQueue | [IN] Event Queue Number to which the channel will be mapped (valid only for the Master Channel (DMA/QDMA) request)
tccCb | [IN] TCC callback - caters to channel- specific events like "Event Miss Error" or "Transfer Complete"
cbData | [IN] Data which will be passed directly to the tccCb callback function
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
Note:
This function internally uses EDMA3 Resource Manager, which acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It also disables the global interrupts while modifying the global CC registers. It is re-entrant, but SHOULD NOT be called from the user callback function (ISR context).
EDMA3_DRV_Result EDMA3_DRV_freeChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | channelId
 | ) |  |

Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings.

This API internally uses EDMA3_RM_freeResource () to free the desired resources.

For Link channels, this API only frees the associated PaRAM Set.

For DMA/QDMA channels, it does the following operations: a) Disable any ongoing transfer on the channel, b) Unregister the TCC Callback function and disable the interrupts, c) Remove the channel to Event Queue mapping, d) For DMA channels, clear the DCHMAP register, if available e) For QDMA channels, clear the QCHMAP register, f) Frees the DMA/QDMA channel in the end.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
channelId | [IN] Logical Channel number to be freed.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
Note:
This function disables the global interrupts while modifying the global CC registers and while modifying global data structures, to prevent simultaneous access to the global pool of resources. It internally calls EDMA3_RM_freeResource () for resource de-allocation. It is re-entrant.
EDMA3_DRV_Result EDMA3_DRV_clearErrorBits | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | channelId
 | ) |  |

Disables the DMA Channel by clearing the Event Enable Register and clears Error Register & Secondary Event Register for a specific DMA channel.

This API clears the Event Enable register, Event Miss register and Secondary Event register for a specific DMA channel. It also clears the CC Error register.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
channelId | [IN] DMA Channel needs to be cleaned.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
Note:
This function is re-entrant for unique channelId values. It is non- re-entrant for same channelId value.
EDMA3_DRV_Result EDMA3_DRV_setOptField | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_OptField | optField,
 |  | unsigned int | newOptFieldVal
 | ) |  |

Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.

This API can be used to set various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
lCh | [IN] Logical Channel, bound to which PaRAM set OPT field needs to be set.
optField | [IN] The particular field of OPT Word that needs setting
newOptFieldVal | [IN] The new OPT field value
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
EDMA3_DRV_Result EDMA3_DRV_getOptField | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_OptField | optField,
 |  | unsigned int * | optFieldVal
 | ) |  |

Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.

This API can be used to read various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
lCh | [IN] Logical Channel, bound to which PaRAM set OPT field is required.
optField | [IN] The particular field of OPT Word that is needed
optFieldVal | [IN/OUT] Value of the OPT field
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.
EDMA3_DRV_Result EDMA3_DRV_setSrcParams | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | unsigned int | srcAddr,
 |  | EDMA3_DRV_AddrMode | addrMode,
 |  | EDMA3_DRV_FifoWidth | fifoWidth
 | ) |  |

DMA source parameters setup.

It is used to program the source address, source side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.

In FIFO Addressing mode, memory location must be 32 bytes aligned.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel for which the source parameters are to be configured
srcAddr | [IN] Source address
addrMode | [IN] Address mode [FIFO or Increment]
fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO)

  1. 0 - 8 bit
  2. 1 - 16 bit
  3. 2 - 32 bit
  4. 3 - 64 bit
  5. 4 - 128 bit
  6. 5 - 256 bit
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
EDMA3_DRV_Result EDMA3_DRV_setDestParams | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | unsigned int | destAddr,
 |  | EDMA3_DRV_AddrMode | addrMode,
 |  | EDMA3_DRV_FifoWidth | fifoWidth
 | ) |  |

DMA Destination parameters setup.

It is used to program the destination address, destination side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.

In FIFO Addressing mode, memory location must be 32 bytes aligned.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel for which the destination parameters are to be configured
destAddr | [IN] Destination address
addrMode | [IN] Address mode [FIFO or Increment]
fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO)

  1. 0 - 8 bit
  2. 1 - 16 bit
  3. 2 - 32 bit
  4. 3 - 64 bit
  5. 4 - 128 bit
  6. 5 - 256 bit
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
EDMA3_DRV_Result EDMA3_DRV_setSrcIndex | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | int | srcBIdx,
 |  | int | srcCIdx
 | ) |  |

DMA source index setup.

It is used to program the source B index and source C index.

SRCBIDX is a 16-bit signed value (2s complement) used for source address modification between each array in the 2nd dimension. Valid values for SRCBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-synchronized and AB-synchronized transfers.

SRCCIDX is a 16-bit signed value (2s complement) used for source address modification in the 3rd dimension. Valid values for SRCCIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when SRCCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in an AB-synchronized transfer is the first array in the frame.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel for which source indices are to be configured
srcBIdx | [IN] Source B index
srcCIdx | [IN] Source C index
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
EDMA3_DRV_Result EDMA3_DRV_setDestIndex | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | int | destBIdx,
 |  | int | destCIdx
 | ) |  |

DMA destination index setup.

It is used to program the destination B index and destination C index.

DSTBIDX is a 16-bit signed value (2s complement) used for destination address modification between each array in the 2nd dimension. Valid values for DSTBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-synchronized and AB-synchronized transfers.

DSTCIDX is a 16-bit signed value (2s complement) used for destination address modification in the 3rd dimension. Valid values are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array TR in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when DSTCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in a AB-synchronized transfer is the first array in the frame

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel for which dest indices are to be configured
destBIdx | [IN] Destination B index
destCIdx | [IN] Destination C index
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
EDMA3_DRV_Result EDMA3_DRV_setTransferParams | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | unsigned int | aCnt,
 |  | unsigned int | bCnt,
 |  | unsigned int | cCnt,
 |  | unsigned int | bCntReload,
 |  | EDMA3_DRV_SyncType | syncType
 | ) |  |

DMA transfer parameters setup.

It is used to specify the various counts (ACNT, BCNT and CCNT), B count reload and the synchronization type

ACNT represents the number of bytes within the 1st dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K - 1 bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to EDMA3 Transfer Controller. An ACNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.

BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT are between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K - 1 arrays). A BCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.

CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT are between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K - 1 frames). A CCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT. A CCNT value of 0 is considered either a null or dummy transfer.

BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-synchronized transfers. In this case, the EDMA3CC decrements the BCNT value by 1 on each TR submission. When BCNT (conceptually) reaches 0, the EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel for which transfer parameters are to be configured
aCnt | [IN] Count for 1st Dimension.
bCnt | [IN] Count for 2nd Dimension.
cCnt | [IN] Count for 3rd Dimension.
bCntReload | [IN] Reload value for bCnt.
syncType | [IN] Transfer synchronization dimension 0: A-synchronized. Each event triggers the transfer of a single array of ACNT bytes. 1: AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
EDMA3_DRV_Result EDMA3_DRV_enableTransfer | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_TrigMode | trigMode
 | ) |  |

Start EDMA transfer on the specified channel.

There are multiple ways to trigger an EDMA3 transfer. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.

In event triggered, a peripheral or an externally generated event triggers the transfer. This API clears the Secondary Event Register and Event Miss Register and then enables the DMA channel by writing to the EESR.

In manual triggered mode, CPU manually triggers a transfer by writing a 1 in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to start the transfer.

In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered). This API enables the QDMA channel by writing to the QEESR register.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Channel on which transfer has to be started
trigMode | [IN] Mode of triggering start of transfer (Manual, QDMA or Event)
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
EDMA3_DRV_Result EDMA3_DRV_disableTransfer | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_TrigMode | trigMode
 | ) |  |

Disable DMA transfer on the specified channel.

There are multiple ways by which an EDMA3 transfer could be triggered. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.

To disable a channel which was previously triggered in manual mode, this API clears the Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.

To disable a channel which was previously triggered in QDMA mode, this API clears the QDMA Event Enable Register, for the specific QDMA channel.

To disable a channel which was previously triggered in event mode, this API clears the Event Enable Register. It also clears Event Register, Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Channel on which transfer has to be stopped
trigMode | [IN] Mode of triggering start of transfer
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_TrigMode | trigMode
 | ) |  |

Disable the event driven DMA channel or QDMA channel.

This API disables the DMA channel (which was previously triggered in event mode) by clearing the Event Enable Register; it disables the QDMA channel by clearing the QDMA Event Enable Register.

This API should NOT be used for DMA channels which are not mapped to any hardware events and are used for memory-to-memory copy based transfers. In case of that, this API returns error.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] DMA/QDMA Channel which needs to be disabled
trigMode | [IN] Mode of triggering start of transfer
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
Generated on Fri Jan 28 15:45:38 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3 Driver Advanced APIs

EDMA3 Driver Advanced APIs
[EDMA3 Driver APIs]

Data Structures

struct | EDMA3_DRV_GblXbarToChanConfigParams
Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...

Typedefs

typedef EDMA3_DRV_Result(* | EDMA3_DRV_mapXbarEvtToChan )(unsigned int eventNum, unsigned int *chanNum, const EDMA3_DRV_GblXbarToChanConfigParams *edmaGblXbarConfig)
Associates cross bar mapped event to channel.
typedef EDMA3_DRV_Result(* | EDMA3_DRV_xbarConfigScr )(unsigned int eventNum, unsigned int chanNum)
Writes to the cross bar mapped event to channel to system configuration register.

Functions

EDMA3_DRV_Result | EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)
Link two logical channels.
EDMA3_DRV_Result | EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh)
Unlink the channel from the earlier linked logical channel.
EDMA3_DRV_Result | EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const EDMA3_DRV_ChainOptions *chainOptions)
Chain the two specified channels.
EDMA3_DRV_Result | EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh)
Unchain the two channels.
EDMA3_DRV_Result | EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)
Assign a Trigger Word to the specified QDMA channel.
EDMA3_DRV_Result | EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle hEdma, unsigned int lCh, const EDMA3_DRV_PaRAMRegs *newPaRAM)
Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).
EDMA3_DRV_Result | EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMRegs *currPaRAM)
Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).
EDMA3_DRV_Result | EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int newPaRAMEntryVal)
Set a particular PaRAM set entry of the specified PaRAM set.
EDMA3_DRV_Result | EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int *paRAMEntryVal)
Get a particular PaRAM set entry of the specified PaRAM set.
EDMA3_DRV_Result | EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int newPaRAMFieldVal)
Set a particular PaRAM set field of the specified PaRAM set.
EDMA3_DRV_Result | EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int *currPaRAMFieldVal)
Get a particular PaRAM set field of the specified PaRAM set.
EDMA3_DRV_Result | EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma, const EDMA3_DRV_EvtQuePriority *evtQPriObj)
Sets EDMA TC priority.
EDMA3_DRV_Result | EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)
Associate Channel to Event Queue.
EDMA3_DRV_Result | EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)
Get the Event Queue mapped to the specified DMA/QDMA channel.
EDMA3_DRV_Result | EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)
Set the Channel Controller (CC) Register value.
EDMA3_DRV_Result | EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)
Get the Channel Controller (CC) Register value.
EDMA3_DRV_Result | EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma, unsigned int tccNo)
Wait for a transfer completion interrupt to occur and clear it.
EDMA3_DRV_Result | EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)
Returns the status of a previously initiated transfer.
EDMA3_DRV_Result | EDMA3_DRV_getPaRAMPhyAddr (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)
Get the PaRAM Set Physical Address associated with a logical channel.
EDMA3_DRV_Result | EDMA3_DRV_Ioctl (EDMA3_DRV_Handle hEdma, EDMA3_DRV_IoctlCmd cmd, void *cmdArg, void *param)
EDMA3 Driver IOCTL.
EDMA3_DRV_Handle | EDMA3_DRV_getInstHandle (unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)
Return the previously opened EDMA3 Driver Instance handle.
EDMA3_DRV_Result | EDMA3_DRV_registerTccCb (EDMA3_DRV_Handle hEdma, const unsigned int channelId, EDMA3_RM_TccCallback tccCb, void *cbData)
Registers a transfer completion handler for a specific DMA/QDMA channel.
EDMA3_DRV_Result | EDMA3_DRV_unregisterTccCb (EDMA3_DRV_Handle hEdma, const unsigned int channelId)
Un-register the previously registered callback function against a DMA/QDMA channel.
EDMA3_DRV_Result | EDMA3_DRV_setTcErrorInt (unsigned int phyCtrllerInstId, unsigned int tcId, EDMA3_DRV_Tc_Err tcErr)
Enable/disable specific EDMA3 Transfer Controller Interrupts.
EDMA3_DRV_Result | EDMA3_DRV_getChannelStatus (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *lchStatus)
Get the current status of the DMA/QDMA channel.
EDMA3_DRV_Result | EDMA3_DRV_mapTccLinkCh (EDMA3_DRV_Handle hEdma, unsigned int linkCh, unsigned int tcc)
Associates a link channel and a TCC.
EDMA3_DRV_Result | EDMA3_DRV_initXbarEventMap (EDMA3_DRV_Handle hEdma, const EDMA3_DRV_GblXbarToChanConfigParams *edmaGblXbarConfig, EDMA3_DRV_mapXbarEvtToChan mapXbarEvtFunc, EDMA3_DRV_xbarConfigScr configXbarScr)
Initialize the cross bar mapped event to channel function.

Typedef Documentation

typedef EDMA3_DRV_Result(* EDMA3_DRV_mapXbarEvtToChan)(unsigned int eventNum, unsigned int *chanNum, const EDMA3_DRV_GblXbarToChanConfigParams *edmaGblXbarConfig)

Associates cross bar mapped event to channel.

This function have to be defined in the configuration file. This function will be called only if the channel requested for is beyond the maximum number of channels. This function should read from the global cross bar mapped configuration data structure and return the mapped channel number to this event.

Parameters:
eventNum | [IN] Event number
chanNum | [IN/OUT]Return the channel number to which the request event is mapped to.
edmaGblXbarConfig | [IN] This is the configuration data structure for mapping the events to the channel
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique event values. It is non-re-entrant for same event values.
typedef EDMA3_DRV_Result(* EDMA3_DRV_xbarConfigScr)(unsigned int eventNum, unsigned int chanNum)

Writes to the cross bar mapped event to channel to system configuration register.

This function have to be defined in the configuration file. This function will be called only if the event number requested for is beyond the maximum number of channels and if any channel is allocated to this event. This function should read the cross bar mapped event number and write the allocated channel number in Control Config Event Mux registers.

Parameters:
eventNum | [IN] Event number
chanNum | [IN/OUT]Return the channel number to which the request event is mapped to.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique event values. It is non-re-entrant for same event values.

Function Documentation

EDMA3_DRV_Result EDMA3_DRV_linkChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh1,
 |  | unsigned int | lCh2
 | ) |  |

Link two logical channels.

This API is used to link two previously allocated logical (DMA/QDMA/Link) channels.

It sets the Link field of the PaRAM set associated with first logical channel (lCh1) to point it to the PaRAM set associated with second logical channel (lCh2).

It also sets the TCC field of PaRAM set of second logical channel to the same as that of the first logical channel, only if the TCC field doesnot contain a valid TCC code. In case the second logical channel has its own TCC, the TCC field remains unchanged.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
lCh1 | [IN] Logical Channel to which particular channel will be linked.
lCh2 | [IN] Logical Channel which needs to be linked to the first channel. After the transfer based on the PaRAM set of lCh1 is over, the PaRAM set of lCh2 will be copied to the PaRAM set of lCh1 and transfer will resume. For DMA channels, another sync event is required to initiate the transfer on the Link channel.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh1 & lCh2 values. It is non-re-entrant for same lCh1 & lCh2 values.
EDMA3_DRV_Result EDMA3_DRV_unlinkChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh
 | ) |  |

Unlink the channel from the earlier linked logical channel.

This function breaks the link between the specified channel and the earlier linked logical channel by clearing the Link Address field.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
lCh | [IN] Channel for which linking has to be removed
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
EDMA3_DRV_Result EDMA3_DRV_chainChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh1,
 |  | unsigned int | lCh2,
 |  | const EDMA3_DRV_ChainOptions * | chainOptions
 | ) |  |

Chain the two specified channels.

This API is used to chain a DMA channel to a previously allocated DMA/QDMA channel.

Chaining is different from Linking. The EDMA3 link feature reloads the current channel parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any channel parameter set; it provides a synchronization event (or trigger) to the chained DMA channel, as soon as the transfer (final or intermediate) completes on the main DMA/QDMA channel.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
lCh1 | [IN] DMA/QDMA channel to which a particular DMA channel will be chained.
lCh2 | [IN] DMA channel which needs to be chained to the first DMA/QDMA channel.
chainOptions | [IN] Options such as intermediate interrupts are required or not, intermediate/final chaining is enabled or not etc.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh1 & lCh2 values. It is non-re-entrant for same lCh1 & lCh2 values.
EDMA3_DRV_Result EDMA3_DRV_unchainChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh
 | ) |  |

Unchain the two channels.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
lCh | [IN] Channel whose chaining with the other channel has to be removed.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_RM_QdmaTrigWord | trigWord
 | ) |  |

Assign a Trigger Word to the specified QDMA channel.

This API sets the Trigger word for the specific QDMA channel in the QCHMAP Register. Default QDMA trigger word is CCNT.

Parameters:
hEdma | [IN] Handle to the EDMA Instance object
lCh | [IN] QDMA Channel which needs to be assigned the Trigger Word
trigWord | [IN] The Trigger Word for the QDMA channel. Trigger Word is the word in the PaRAM Register Set which, when written to by CPU, will start the QDMA transfer automatically.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
EDMA3_DRV_Result EDMA3_DRV_setPaRAM | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | const EDMA3_DRV_PaRAMRegs * | newPaRAM
 | ) |  |

Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).

This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set associated with the logical channel. OPT field of the PaRAM Set is written first and the CCNT field is written last.

Caution: It should be used carefully when programming the QDMA channels whose trigger words are not CCNT field.

Parameters:
hEdma | [IN] Handle to the EDMA Instance object
lCh | [IN] Logical Channel for which new PaRAM set is specified
newPaRAM | [IN] Parameter RAM set to be copied onto existing PaRAM
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
EDMA3_DRV_Result EDMA3_DRV_getPaRAM | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_PaRAMRegs * | currPaRAM
 | ) |  |

Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).

Parameters:
hEdma | [IN] Handle to the EDMA Instance object
lCh | [IN] Logical Channel whose PaRAM set is requested
currPaRAM | [IN/OUT] User gets the existing PaRAM here
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.
EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_PaRAMEntry | paRAMEntry,
 |  | unsigned int | newPaRAMEntryVal
 | ) |  |

Set a particular PaRAM set entry of the specified PaRAM set.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel bound to the Parameter RAM set whose specified field needs to be set
paRAMEntry | [IN] Specify the PaRAM set entry which needs to be set
newPaRAMEntryVal | [IN] The new field setting
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This API should be used while setting the PaRAM set entry for QDMA channels. If EDMA3_DRV_setPaRAMField () used, it will trigger the QDMA channel before complete PaRAM set entry is written. For DMA channels, no such constraint is there.

This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_PaRAMEntry | paRAMEntry,
 |  | unsigned int * | paRAMEntryVal
 | ) |  |

Get a particular PaRAM set entry of the specified PaRAM set.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel bound to the Parameter RAM set whose specified field value is needed
paRAMEntry | [IN] Specify the PaRAM set entry which needs to be obtained
paRAMEntryVal | [IN/OUT] The value of the field is returned here
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.
EDMA3_DRV_Result EDMA3_DRV_setPaRAMField | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_PaRAMField | paRAMField,
 |  | unsigned int | newPaRAMFieldVal
 | ) |  |

Set a particular PaRAM set field of the specified PaRAM set.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel bound to the PaRAM set whose specified field needs to be set
paRAMField | [IN] Specify the PaRAM set field which needs to be set
newPaRAMFieldVal | [IN] The new field setting
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This API CANNOT be used while setting the PaRAM set field for QDMA channels. It can trigger the QDMA channel before complete PaRAM set ENTRY (4-bytes field) is written (for eg, as soon one sets the ACNT field for QDMA channel, transfer is started, before one modifies the BCNT field). For DMA channels, no such constraint is there.

This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

EDMA3_DRV_Result EDMA3_DRV_getPaRAMField | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_PaRAMField | paRAMField,
 |  | unsigned int * | currPaRAMFieldVal
 | ) |  |

Get a particular PaRAM set field of the specified PaRAM set.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel bound to the PaRAM set whose specified field value is needed
paRAMField | [IN] Specify the PaRAM set field which needs to be obtained
currPaRAMFieldVal | [IN/OUT] The value of the field is returned here
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.
EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority | ( | EDMA3_DRV_Handle | hEdma,
 |  | const EDMA3_DRV_EvtQuePriority * | evtQPriObj
 | ) |  |

Sets EDMA TC priority.

User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Ctrllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc)

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
evtQPriObj | [IN] Priority of the Event Queues
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant.
EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | channelId,
 |  | EDMA3_RM_EventQueue | eventQ
 | ) |  |

Associate Channel to Event Queue.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
channelId | [IN] Logical Channel to which the Event Queue is to be mapped
eventQ | [IN] The Event Queue which is to be mapped to the DMA channel
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
There should not be any data transfer going on while setting the mapping. Results could be unpredictable.

This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant.

EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | channelId,
 |  | unsigned int * | mappedEvtQ
 | ) |  |

Get the Event Queue mapped to the specified DMA/QDMA channel.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
channelId | [IN] Logical Channel whose associated Event Queue is needed
mappedEvtQ | [IN/OUT] The Event Queue which is mapped to the DMA/QDMA channel
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.
EDMA3_DRV_Result EDMA3_DRV_setCCRegister | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | regOffset,
 |  | unsigned int | newRegValue
 | ) |  |

Set the Channel Controller (CC) Register value.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
regOffset | [IN] CC Register offset whose value needs to be set
newRegValue | [IN] New CC Register Value
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is non re-entrant for users using the same EDMA handle i.e. working on the same shadow region. Before modifying a register, it tries to acquire a semaphore (Driver instance specific), to protect simultaneous modification of the same register by two different users. After the successful change, it releases the semaphore. For users working on different shadow regions, thus different EDMA handles, this function is re-entrant.
EDMA3_DRV_Result EDMA3_DRV_getCCRegister | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | regOffset,
 |  | unsigned int * | regValue
 | ) |  |

Get the Channel Controller (CC) Register value.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
regOffset | [IN] CC Register offset whose value is needed
regValue | [IN/OUT] CC Register Value
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.
EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | tccNo
 | ) |  |

Wait for a transfer completion interrupt to occur and clear it.

This is a blocking function that returns when the IPR/IPRH bit corresponding to the tccNo specified, is SET. It clears the corresponding bit while returning also.

This function waits for the specific bit indefinitely in a tight loop, with out any delay in between. USE IT CAUTIOUSLY.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
tccNo | [IN] TCC, specific to which the function waits on a IPR/IPRH bit.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for different tccNo.
EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | tccNo,
 |  | unsigned short * | tccStatus
 | ) |  |

Returns the status of a previously initiated transfer.

This is a non-blocking function that returns the status of a previously initiated transfer, based on the IPR/IPRH bit. This bit corresponds to the tccNo specified by the user. It clears the corresponding bit, if SET, while returning also.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
tccNo | [IN] TCC, specific to which the function checks the status of the IPR/IPRH bit.
tccStatus | [IN/OUT] Status of the transfer is returned here. Returns "TRUE" if the transfer has completed (IPR/IPRH bit SET), "FALSE" if the transfer has not completed successfully (IPR/IPRH bit NOT SET).
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for different tccNo.
EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | unsigned int * | paramPhyAddr
 | ) |  |

Get the PaRAM Set Physical Address associated with a logical channel.

This function returns the PaRAM Set Phy Address (unsigned 32 bits). The returned address could be used by the advanced users to program the PaRAM Set directly without using any APIs.

Least significant 16 bits of this address could be used to program the LINK field in the PaRAM Set. Users which program the LINK field directly SHOULD use this API to get the associated PaRAM Set address with the LINK channel.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel for which the PaRAM set physical address is required
paramPhyAddr | [IN/OUT] PaRAM Set physical address is returned here.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.
EDMA3_DRV_Result EDMA3_DRV_Ioctl | ( | EDMA3_DRV_Handle | hEdma,
 |  | EDMA3_DRV_IoctlCmd | cmd,
 |  | void * | cmdArg,
 |  | void * | param
 | ) |  |

EDMA3 Driver IOCTL.

This function provides IOCTL functionality for EDMA3 Driver.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
cmd | [IN] IOCTL command to be performed
cmdArg | [IN/OUT] IOCTL command argument (if any)
param | [IN/OUT] Device/Cmd specific argument
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
For 'EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant. For 'EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for different EDMA3 Driver Instances (handles).
EDMA3_DRV_Handle EDMA3_DRV_getInstHandle | ( | unsigned int | phyCtrllerInstId,
 |  | EDMA3_RM_RegionId | regionId,
 |  | EDMA3_DRV_Result * | errorCode
 | ) |  |

Return the previously opened EDMA3 Driver Instance handle.

This API is used to return the previously opened EDMA3 Driver's Instance Handle (region specific), which could be used to call other EDMA3 Driver APIs. Since EDMA3 Driver does not allow multiple instances, for a single shadow region, this API is provided. This API is meant for users who DO NOT want to / could not open a new Driver Instance and hence re-use the existing Driver Instance to allocate EDMA3 resources and use various other EDMA3 Driver APIs.

In case the Driver Instance is not yet opened, NULL is returned as the function return value whereas EDMA3_DRV_E_INST_NOT_OPENED is returned in the errorCode.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
regionId | [IN] Shadow Region id for which the previously opened driver's instance handle is required.
errorCode | [OUT] Error code while returning Driver Instance Handle.
Returns:
EDMA3_DRV_Handle : If successful, this API will return the driver's instance handle.
Note:
1) This API returns the previously opened EDMA3 Driver's Instance handle. The instance, if exists, could have been opened by some other user (most probably) or may be by the same user calling this API. If it was opened by some other user, then that user can very well close this instance anytime, without even knowing that the same instance handle is being used by other users as well. In that case, the handle becomes INVALID and user has to open a valid driver instance for his/her use.

2) This function is re-entrant.

EDMA3_DRV_Result EDMA3_DRV_registerTccCb | ( | EDMA3_DRV_Handle | hEdma,
 |  | const unsigned int | channelId,
 |  | EDMA3_RM_TccCallback | tccCb,
 |  | void * | cbData
 | ) |  |

Registers a transfer completion handler for a specific DMA/QDMA channel.

This function registers a non-NULL callback function for a specific DMA or QDMA channel and enables the completion interrupt for the TCC associated with the underlying channel in the IER/IERH register. It also sets the DRAE/DRAEH register for the TCC associated with the specified DMA/QDMA channel. If user enables the transfer completion interrupts (intermediate or final) in the OPT field of the associated PaRAM Set, the registered callback function will be called by the EDMA3 Resource Manager.

If a call-back function is already registered for the channel, the API fails with the error code EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
channelId | [IN] DMA/QDMA channel for which the callback function needs to be registered.
tccCb | [IN] The callback function to be registered.
cbData | [IN] Callback data to be passed while calling the callback function.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique channelId values. It is non- re-entrant for same channelId value.
EDMA3_DRV_Result EDMA3_DRV_unregisterTccCb | ( | EDMA3_DRV_Handle | hEdma,
 |  | const unsigned int | channelId
 | ) |  |

Un-register the previously registered callback function against a DMA/QDMA channel.

This function un-registers the previously registered callback function for the DMA/QDMA channel by removing any stored callback function. Moreover, it clears the: Interrupt Enable Register (IER/IERH) by writing to the IECR/IECRH register, for the TCC associated with that particular channel, DRA/DRAEH register for the TCC associated with the specified DMA/QDMA channel

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
channelId | [IN] DMA/QDMA channel for which the callback function needs to be un-registered.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique channelId. It is non-re-entrant for same channelId.
EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt | ( | unsigned int | phyCtrllerInstId,
 |  | unsigned int | tcId,
 |  | EDMA3_DRV_Tc_Err | tcErr
 | ) |  |

Enable/disable specific EDMA3 Transfer Controller Interrupts.

This function allows one to enable/disable specific EDMA3 Transfer Controller Interrupts. Since these interrupts don't get enabled by default, this API can be used to achieve the same.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
tcId | [IN] Transfer Controller Id. It starts from 0 for each EDMA3 hardware and can go upto (TCs available on EDMA3 Hardware - 1).
tcErr | [IN] TC Error Interrupts which need to be enabled/disabled.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
Note:
This function is re-entrant for unique combination of EDMA3 hw and TC. It is non-re-entrant for same combination.
EDMA3_DRV_Result EDMA3_DRV_getChannelStatus | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | unsigned int * | lchStatus
 | ) |  |

Get the current status of the DMA/QDMA channel.

This function returns the current status of the specific DMA/QDMA channel. For a DMA channel, it checks whether an event is pending in ER, transfer completion interrupt is pending in IPR and event miss error interrupt is pending in EMR or not. For a QDMA channel, it checks whether a transfer completion interrupt is pending in IPR and event miss error interrupt is pending in QEMR or not.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
lCh | [IN] DMA/QDMA channel for which the current status is required.
lchStatus | [IN/OUT]Status of the channel. Defines mentioned above are used (and may be combined) to return the actual status.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.
EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | linkCh,
 |  | unsigned int | tcc
 | ) |  |

Associates a link channel and a TCC.

This API is used to map a TCC to a LINK channel. It should be used with LINK channels ONLY else it will fail. It will copy the TCC code in the OPT field of the param set associated with the link channel.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
linkCh | [IN] Link Channel to which a particular TCC needs to be mapped.
tcc | [IN] TCC which needs to be mapped.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique linkCh values. It is non-re-entrant for same linkCh values.
EDMA3_DRV_Result EDMA3_DRV_initXbarEventMap | ( | EDMA3_DRV_Handle | hEdma,
 |  | const EDMA3_DRV_GblXbarToChanConfigParams * | edmaGblXbarConfig,
 |  | EDMA3_DRV_mapXbarEvtToChan | mapXbarEvtFunc,
 |  | EDMA3_DRV_xbarConfigScr | configXbarScr
 | ) |  |

Initialize the cross bar mapped event to channel function.

This API provides interface to associate the cross bar mapped event to edma channel in the driver. This function will called by the application during initilization. User could pass the application specific configuration structure during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
edmaGblXbarConfig | [IN] This is the configuration data structure for mapping the events to the channel
mapXbarEvtFunc | [IN] This is the user defined function for mapping the cross bar event to channel.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant.
Generated on Fri Jan 28 15:45:38 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: Data Structures

  • Data Structure Index
  • Data Fields

Data Structures

Here are the data structures with brief descriptions:
EDMA3_DRV_ChainOptions | Structure to be used to configure interrupt generation and chaining options
EDMA3_DRV_ChBoundResources | EDMA3 Channel-Bound resources
EDMA3_DRV_EvtQuePriority | Event queue priorities setup
EDMA3_DRV_GblConfigParams | Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information
EDMA3_DRV_GblXbarToChanConfigParams | Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information
EDMA3_DRV_InitConfig | Used to Initialize the EDMA3 Driver Instance
EDMA3_DRV_Instance | EDMA3 Driver Instance Configuration Structure
EDMA3_DRV_InstanceInitConfig | Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information
EDMA3_DRV_MiscParam | Used to specify the miscellaneous options during EDMA3 Driver Initialization
EDMA3_DRV_Object | EDMA3 Driver Object (HW Specific) Maintenance structure
EDMA3_DRV_ParamentryRegs | EDMA3 PaRAM Set
EDMA3_DRV_PaRAMRegs | EDMA3 Parameter RAM Set in User Configurable format
Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3_DRV_ChainOptions Struct Reference

EDMA3_DRV_ChainOptions Struct Reference
[EDMA3 Driver Data Structures]

Structure to be used to configure interrupt generation and chaining options. More...

#include <edma3_drv.h>

Data Fields

EDMA3_DRV_TcchEn tcchEn
EDMA3_DRV_ItcchEn itcchEn
EDMA3_DRV_TcintEn tcintEn
EDMA3_DRV_ItcintEn itcintEn

Detailed Description

Structure to be used to configure interrupt generation and chaining options.

Field Documentation

EDMA3_DRV_TcchEn EDMA3_DRV_ChainOptions::tcchEn

Transfer complete chaining enable

EDMA3_DRV_ItcchEn EDMA3_DRV_ChainOptions::itcchEn

Intermediate Transfer complete chaining enable

EDMA3_DRV_TcintEn EDMA3_DRV_ChainOptions::tcintEn

Transfer complete interrupt enable

EDMA3_DRV_ItcintEn EDMA3_DRV_ChainOptions::itcintEn

Intermediate Transfer complete interrupt enable

The documentation for this struct was generated from the following file:
  • edma3_drv.h
Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3_DRV_ChBoundResources Struct Reference

EDMA3_DRV_ChBoundResources Struct Reference

EDMA3 Channel-Bound resources. More...

#include <edma3.h>

Data Fields

int | paRAMId
unsigned int | tcc
EDMA3_DRV_TrigMode trigMode

Detailed Description

EDMA3 Channel-Bound resources.

Used to maintain information of the EDMA3 resources (specifically Parameter RAM set and TCC) and the mode of triggering transfer (Manual, HW event driven etc) bound to the particular channel within EDMA3_DRV_requestChannel().

Field Documentation

int EDMA3_DRV_ChBoundResources::paRAMId

PaRAM Set number associated with the particular channel

unsigned int EDMA3_DRV_ChBoundResources::tcc

TCC associated with the particular channel

EDMA3_DRV_TrigMode EDMA3_DRV_ChBoundResources::trigMode

Mode of triggering transfer

The documentation for this struct was generated from the following file:
  • edma3.h
Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3_DRV_EvtQuePriority Struct Reference

EDMA3_DRV_EvtQuePriority Struct Reference
[EDMA3 Driver Data Structures]

Event queue priorities setup. More...

#include <edma3_drv.h>

Data Fields

unsigned int evtQPri [EDMA3_MAX_EVT_QUE]
Event Queue Priorities.

Detailed Description

Event queue priorities setup.

It allows to change the priority of the individual queues and the priority of the transfer request (TR) associated with the events queued in the queue.

The documentation for this struct was generated from the following file:
  • edma3_drv.h
Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3_DRV_GblConfigParams Struct Reference

EDMA3_DRV_GblConfigParams Struct Reference
[EDMA3 Driver Data Structures]

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...

#include <edma3_drv.h>

Data Fields

unsigned int | numDmaChannels
unsigned int | numQdmaChannels
unsigned int | numTccs
unsigned int | numPaRAMSets
unsigned int | numEvtQueue
unsigned int | numTcs
unsigned int | numRegions
unsigned int | dmaChPaRAMMapExists
Channel mapping existence.
unsigned int | memProtectionExists
void * | globalRegs
void * | tcRegs [EDMA3_MAX_TC]
unsigned int | xferCompleteInt
unsigned int | ccError
unsigned int | tcError [EDMA3_MAX_TC]
unsigned int | evtQPri [EDMA3_MAX_EVT_QUE]
EDMA3 TC priority setting.
unsigned int | evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE]
Event Queues Watermark Levels.
unsigned int | tcDefaultBurstSize [EDMA3_MAX_TC]
Default Burst Size (DBS) of TCs.
unsigned int | dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH]
Mapping from DMA channels to PaRAM Sets.
unsigned int | dmaChannelTccMap [EDMA3_MAX_DMA_CH]
Mapping from DMA channels to TCCs.
unsigned int | dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS]
Mapping from DMA channels to Hardware Events.

Detailed Description

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.

This configuration structure is used to specify the EDMA3 Driver global settings, specific to the SoC. For e.g. number of DMA/QDMA channels, number of PaRAM sets, TCCs, event queues, transfer controllers, base addresses of CC global registers and TC registers, interrupt number for EDMA3 transfer completion, CC error, event queues' priority, watermark threshold level etc. This configuration information is SoC specific and could be provided by the user at run-time while creating the EDMA3 Driver Object, using API EDMA3_DRV_create. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

Field Documentation

unsigned int EDMA3_DRV_GblConfigParams::numDmaChannels

Number of DMA Channels supported by the underlying EDMA3 Controller.

unsigned int EDMA3_DRV_GblConfigParams::numQdmaChannels

Number of QDMA Channels supported by the underlying EDMA3 Controller

unsigned int EDMA3_DRV_GblConfigParams::numTccs

Number of Interrupt Channels supported by the underlying EDMA3 Controller

unsigned int EDMA3_DRV_GblConfigParams::numPaRAMSets

Number of PaRAM Sets supported by the underlying EDMA3 Controller

unsigned int EDMA3_DRV_GblConfigParams::numEvtQueue

Number of Event Queues in the underlying EDMA3 Controller

unsigned int EDMA3_DRV_GblConfigParams::numTcs

Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller

unsigned int EDMA3_DRV_GblConfigParams::numRegions

Number of Regions in the underlying EDMA3 Controller

unsigned int EDMA3_DRV_GblConfigParams::dmaChPaRAMMapExists

Channel mapping existence.

A value of 0 (No channel mapping) implies that there is fixed association between a DMA channel and a PaRAM Set or, in other words, DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP registers) for transfers to happen.

A value of 1 implies the presence of DCHMAP registers for the DMA channels and hence the flexibility of associating any DMA channel to any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA channel (like QDMA Channels).

unsigned int EDMA3_DRV_GblConfigParams::memProtectionExists

Existence of memory protection feature

void* EDMA3_DRV_GblConfigParams::globalRegs

Base address of EDMA3 CC memory mapped registers.

void* EDMA3_DRV_GblConfigParams::tcRegs[EDMA3_MAX_TC]

Base address of EDMA3 TCs memory mapped registers.

unsigned int EDMA3_DRV_GblConfigParams::xferCompleteInt

EDMA3 transfer completion interrupt line (could be different for ARM and DSP)

unsigned int EDMA3_DRV_GblConfigParams::ccError

EDMA3 CC error interrupt line (could be different for ARM and DSP)

unsigned int EDMA3_DRV_GblConfigParams::tcError[EDMA3_MAX_TC]

EDMA3 TCs error interrupt line (could be different for ARM and DSP)

unsigned int EDMA3_DRV_GblConfigParams::evtQPri[EDMA3_MAX_EVT_QUE]

EDMA3 TC priority setting.

User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Controllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc)

unsigned int EDMA3_DRV_GblConfigParams::evtQueueWaterMarkLvl[EDMA3_MAX_EVT_QUE]

Event Queues Watermark Levels.

To Configure the Threshold level of number of events that can be queued up in the Event queues. EDMA3CC error register (CCERR) will indicate whether or not at any instant of time the number of events queued up in any of the event queues exceeds or equals the threshold/watermark value that is set in the queue watermark threshold register (QWMTHRA).

unsigned int EDMA3_DRV_GblConfigParams::tcDefaultBurstSize[EDMA3_MAX_TC]

Default Burst Size (DBS) of TCs.

An optimally-sized command is defined by the transfer controller default burst size (DBS). Different TCs can have different DBS values. It is defined in Bytes.

unsigned int EDMA3_DRV_GblConfigParams::dmaChannelPaRAMMap[EDMA3_MAX_DMA_CH]

Mapping from DMA channels to PaRAM Sets.

If channel mapping exists (DCHMAP registers are present), this array stores the respective PaRAM Set for each DMA channel. User can initialize each array member with a specific PaRAM Set or with EDMA3_DRV_CH_NO_PARAM_MAP. If channel mapping doesn't exist, it is of no use as the EDMA3 RM automatically uses the right PaRAM Set for that DMA channel. Useful only if mapping exists, otherwise of no use.

unsigned int EDMA3_DRV_GblConfigParams::dmaChannelTccMap[EDMA3_MAX_DMA_CH]

Mapping from DMA channels to TCCs.

This array stores the respective TCC (interrupt channel) for each DMA channel. User can initialize each array member with a specific TCC or with EDMA3_DRV_CH_NO_TCC_MAP. This specific TCC code will be returned when the transfer is completed on the mapped DMA channel.

unsigned int EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap[EDMA3_MAX_DMA_CHAN_DWRDS]

Mapping from DMA channels to Hardware Events.

Each bit in this array corresponds to one DMA channel and tells whether this DMA channel is tied to any peripheral. That is whether any peripheral can send the synch event on this DMA channel or not. 1 means the channel is tied to some peripheral; 0 means it is not. DMA channels which are tied to some peripheral are RESERVED for that peripheral only. They are not allocated when user asks for 'ANY' DMA channel. All channels need not be mapped, some can be free also.

The documentation for this struct was generated from the following file:
  • edma3_drv.h
Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3_DRV_GblXbarToChanConfigParams Struct Reference

EDMA3_DRV_GblXbarToChanConfigParams Struct Reference
[EDMA3 Driver Advanced APIs]

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...

#include <edma3_drv.h>

Data Fields

int dmaMapXbarToChan [EDMA3_DRV_MAX_XBAR_EVENTS]
Mapping from DMA channels to Hardware Events.

Detailed Description

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.

This configuration structure is used to specify the EDMA3 Driver global settings, specific to the SoC. This configuraion structure provides the details of the mapping of cross bar events to available channels. This configuration information is SoC specific and could be provided by the user at run-time while creating the EDMA3 Driver Object, using API EDMA3_DRV_initXbarEventMap. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, incase it is available.

Field Documentation

int EDMA3_DRV_GblXbarToChanConfigParams::dmaMapXbarToChan[EDMA3_DRV_MAX_XBAR_EVENTS]

Mapping from DMA channels to Hardware Events.

Each element in this array corresponds to one cross bar event and tells whether this event is mapped to any DMA channel. That is whether any free or unused DMA channel can be mapped to this event. -1 means the cross bar event is not mapped to any DMA channel; Any number from 0 to 63 means this event is mapped to specified channel. All channels need not be mapped, some can be free also. For the cross bar event mapped to DMA channel, appropriate Control Config register of TPCC event mux register should be configured.

The documentation for this struct was generated from the following file:
  • edma3_drv.h
Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3_DRV_InitConfig Struct Reference

EDMA3_DRV_InitConfig Struct Reference
[EDMA3 Driver Data Structures]

Used to Initialize the EDMA3 Driver Instance. More...

#include <edma3_drv.h>

Data Fields

EDMA3_RM_RegionId | regionId
unsigned int | isMaster
EDMA3_DRV_InstanceInitConfig * drvInstInitConfig
void * | drvSemHandle
EDMA3_RM_GblErrCallback | gblerrCb
void * | gblerrData

Detailed Description

Used to Initialize the EDMA3 Driver Instance.

This configuration structure is used to initialize the EDMA3 DRV Instance. This configuration information is passed while opening the DRV instance.

Field Documentation

EDMA3_RM_RegionId EDMA3_DRV_InitConfig::regionId

Region Identification

unsigned int EDMA3_DRV_InitConfig::isMaster

It tells whether the EDMA3 DRV instance is Master or not. Only the shadow region associated with this master instance will receive the EDMA3 interrupts (if enabled).

EDMA3_DRV_InstanceInitConfig* EDMA3_DRV_InitConfig::drvInstInitConfig

EDMA3 resources related shadow region specific information. Which all EDMA3 resources are owned and reserved by this particular instance are told in this configuration structure. User can also pass this structure as NULL. In that case, default static configuration would be taken from the platform specific configuration files (part of the Resource Manager), if available.

void* EDMA3_DRV_InitConfig::drvSemHandle

EDMA3 Driver Instance specific semaphore handle. Used to share resources (DMA/QDMA channels, PaRAM Sets, TCCs etc) among different users.

EDMA3_RM_GblErrCallback EDMA3_DRV_InitConfig::gblerrCb

Instance wide global callback function to catch non-channel specific errors from the Channel controller. for eg, TCC error, queue threshold exceed error etc.

void* EDMA3_DRV_InitConfig::gblerrData

Application data to be passed back to the global error callback function

The documentation for this struct was generated from the following file:
  • edma3_drv.h
Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3_DRV_Instance Struct Reference

EDMA3_DRV_Instance Struct Reference

EDMA3 Driver Instance Configuration Structure. More...

#include <edma3.h>

Data Fields

EDMA3_RM_RegionId | regionId
unsigned int | isMaster
EDMA3_DRV_InstanceInitConfig drvInstInitConfig
void * | drvSemHandle
EDMA3_RM_GblErrCallbackParams | gblerrCbParams
EDMA3_CCRL_ShadowRegs * | shadowRegs
EDMA3_DRV_Object * pDrvObjectHandle
EDMA3_RM_Handle | resMgrInstance
EDMA3_DRV_mapXbarEvtToChan mapXbarToChan
EDMA3_DRV_xbarConfigScr configScrMapXbarToEvt
EDMA3_DRV_GblXbarToChanConfigParams drvXbarToEvtMapConfig

Detailed Description

EDMA3 Driver Instance Configuration Structure.

Used to maintain information of the EDMA3 Driver Instances. One such storage exists for each instance of the EDMA3 Driver. There could be as many Driver Instances as there are shadow regions. Multiple EDMA3 Driver instances on the same shadow region are NOT allowed.

Field Documentation

EDMA3_RM_RegionId EDMA3_DRV_Instance::regionId

Region Identification

unsigned int EDMA3_DRV_Instance::isMaster

Whether EDMA3 driver instance is Master or not. Only the master instance shadow region will receive the EDMA3 interrupts, if enabled.

EDMA3_DRV_InstanceInitConfig EDMA3_DRV_Instance::drvInstInitConfig

EDMA3 Driver Instance (Shadow Region) specific init configuration. If NULL, static values will be taken

void* EDMA3_DRV_Instance::drvSemHandle

EDMA3 Driver Instance specific semaphore handle

EDMA3_RM_GblErrCallbackParams EDMA3_DRV_Instance::gblerrCbParams

Instance wide Global Error callback parameters

EDMA3_CCRL_ShadowRegs* EDMA3_DRV_Instance::shadowRegs

Pointer to appropriate Shadow Register region of CC Registers

EDMA3_DRV_Object* EDMA3_DRV_Instance::pDrvObjectHandle

Pointer to the EDMA3 Driver Object, for HW specific / Global Information.

EDMA3_RM_Handle EDMA3_DRV_Instance::resMgrInstance

Pointer to the Resource Manager Instance opened by the EDMA3 Driver

EDMA3_DRV_mapXbarEvtToChan EDMA3_DRV_Instance::mapXbarToChan

Pointer to the user defined function for mapping cross bar events to channel.

EDMA3_DRV_xbarConfigScr EDMA3_DRV_Instance::configScrMapXbarToEvt

Pointer to the user defined function for configuring the cross bar events to appropriate channel in the Control Config TPCC Event Config registers.

EDMA3_DRV_GblXbarToChanConfigParams EDMA3_DRV_Instance::drvXbarToEvtMapConfig

Pointer to the configuration data structure for mapping cross bar events to channel.

The documentation for this struct was generated from the following file:
  • edma3.h
Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3_DRV_InstanceInitConfig Struct Reference

EDMA3_DRV_InstanceInitConfig Struct Reference
[EDMA3 Driver Data Structures]

Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information. More...

#include <edma3_drv.h>

Data Fields

unsigned int | ownPaRAMSets [EDMA3_MAX_PARAM_DWRDS]
unsigned int | ownDmaChannels [EDMA3_MAX_DMA_CHAN_DWRDS]
unsigned int | ownQdmaChannels [EDMA3_MAX_QDMA_CHAN_DWRDS]
unsigned int | ownTccs [EDMA3_MAX_TCC_DWRDS]
unsigned int | resvdPaRAMSets [EDMA3_MAX_PARAM_DWRDS]
Reserved PaRAM Sets.
unsigned int | resvdDmaChannels [EDMA3_MAX_DMA_CHAN_DWRDS]
Reserved DMA channels.
unsigned int | resvdQdmaChannels [EDMA3_MAX_QDMA_CHAN_DWRDS]
Reserved QDMA channels.
unsigned int | resvdTccs [EDMA3_MAX_TCC_DWRDS]
Reserved TCCs.

Detailed Description

Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information.

This configuration structure is used to specify which EDMA3 resources are owned and reserved by the EDMA3 Driver instance. This configuration structure is shadow region specific and will be provided by the user at run-time while calling EDMA3_DRV_open ().

Owned resources: ****************

EDMA3 Driver Instances are tied to different shadow regions and hence different masters. Regions could be:

a) ARM, b) DSP, c) IMCOP (Imaging Co-processor) etc.

User can assign each EDMA3 resource to a shadow region using this structure. In this way, user specifies which resources are owned by the specific EDMA3 DRV Instance. This assignment should also ensure that the same resource is not assigned to more than one shadow regions (unless desired in that way). Any assignment not following the above mentioned approach may have catastrophic consequences.

Reserved resources: *******************

During EDMA3 DRV initialization, user can reserve some of the EDMA3 resources for future use, by specifying which resources to reserve in the configuration data structure. These (critical) resources are reserved in advance so that they should not be allocated to someone else and thus could be used in future for some specific purpose.

User can request different EDMA3 resources using two methods: a) By passing the resource type and the actual resource id, b) By passing the resource type and ANY as resource id

For e.g. to request DMA channel 31, user will pass 31 as the resource id. But to request ANY available DMA channel (mainly used for memory-to-memory data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the resource id.

During initialization, user may have reserved some of the DMA channels for some specific purpose (mainly for peripherals using EDMA). These reserved DMA channels then will not be returned when user requests ANY as the resource id.

Same logic applies for QDMA channels and TCCs.

For PaRAM Set, there is one difference. If the DMA channels are one-to-one tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set for a particular DMA channel), EDMA3 Driver automatically reserves all those PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would not be returned when user requests for ANY PaRAM Set (specifically for linking purpose). This is done in order to avoid allocating the PaRAM Set, tied to a particular DMA channel, for linking purpose. If this constraint is not there, that DMA channel thus could not be used at all, because of the unavailability of the desired PaRAM Set.

Field Documentation

unsigned int EDMA3_DRV_InstanceInitConfig::ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS]

PaRAM Sets owned by the EDMA3 Driver Instance.

unsigned int EDMA3_DRV_InstanceInitConfig::ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]

DMA Channels owned by the EDMA3 Driver Instance.

unsigned int EDMA3_DRV_InstanceInitConfig::ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]

QDMA Channels owned by the EDMA3 Driver Instance.

unsigned int EDMA3_DRV_InstanceInitConfig::ownTccs[EDMA3_MAX_TCC_DWRDS]

TCCs owned by the EDMA3 Driver Instance.

unsigned int EDMA3_DRV_InstanceInitConfig::resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS]

Reserved PaRAM Sets.

PaRAM Sets reserved during initialization for future use. These will not be given when user requests for ANY available PaRAM Set for linking using 'EDMA3_DRV_LINK_CHANNEL' as channel id.

unsigned int EDMA3_DRV_InstanceInitConfig::resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]

Reserved DMA channels.

DMA channels reserved during initialization for future use. These will not be given when user requests for ANY available DMA channel using 'EDMA3_DRV_DMA_CHANNEL_ANY' as channel id.

unsigned int EDMA3_DRV_InstanceInitConfig::resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]

Reserved QDMA channels.

QDMA channels reserved during initialization for future use. These will not be given when user requests for ANY available QDMA channel using 'EDMA3_DRV_QDMA_CHANNEL_ANY' as channel id.

unsigned int EDMA3_DRV_InstanceInitConfig::resvdTccs[EDMA3_MAX_TCC_DWRDS]

Reserved TCCs.

TCCs reserved during initialization for future use. These will not be given when user requests for ANY available TCC using 'EDMA3_DRV_TCC_ANY' as resource id.

The documentation for this struct was generated from the following file:
  • edma3_drv.h
Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3_DRV_MiscParam Struct Reference

EDMA3_DRV_MiscParam Struct Reference
[EDMA3 Driver Data Structures]

Used to specify the miscellaneous options during EDMA3 Driver Initialization. More...

#include <edma3_drv.h>

Data Fields

unsigned short | isSlave
unsigned short | param

Detailed Description

Used to specify the miscellaneous options during EDMA3 Driver Initialization.

This configuration structure is used to specify some misc options while creating the Driver object. New options may also be added into this structure in future.

Field Documentation

unsigned short EDMA3_DRV_MiscParam::isSlave

In a multi-master system (for e.g. ARM + DSP), this option is used to distinguish between Master and Slave. Only the Master is allowed to program the global EDMA3 registers (like Queue priority, Queue water- mark level, error registers etc).

unsigned short EDMA3_DRV_MiscParam::param

For future use

The documentation for this struct was generated from the following file:
  • edma3_drv.h
Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3_DRV_Object Struct Reference

EDMA3_DRV_Object Struct Reference

EDMA3 Driver Object (HW Specific) Maintenance structure. More...

#include <edma3.h>

Data Fields

unsigned int | phyCtrllerInstId
EDMA3_DRV_ObjState | state
unsigned int | numOpens
EDMA3_DRV_GblConfigParams gblCfgParams
Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.

Detailed Description

EDMA3 Driver Object (HW Specific) Maintenance structure.

Used to maintain information of the EDMA3 HW configuration thoughout the lifetime of the EDMA3 Driver Object, one for each EDMA3 hardware instance.

Field Documentation

unsigned int EDMA3_DRV_Object::phyCtrllerInstId

Physical Instance ID of EDMA3 Controller

EDMA3_DRV_ObjState EDMA3_DRV_Object::state

State information of the EDMA3 Driver object

unsigned int EDMA3_DRV_Object::numOpens

Number of EDMA3 Driver instances

EDMA3_DRV_GblConfigParams EDMA3_DRV_Object::gblCfgParams

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.

This configuration info can be provided by the user at run-time, while calling EDMA3_DRV_create(). If not provided at run-time, this info will be taken from the config file edma3Cfg.c.

The documentation for this struct was generated from the following file:
  • edma3.h
Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3_DRV_ParamentryRegs Struct Reference

EDMA3_DRV_ParamentryRegs Struct Reference
[EDMA3 Driver Data Structures]

EDMA3 PaRAM Set. More...

#include <edma3_drv.h>

Data Fields

volatile unsigned int | OPT
volatile unsigned int | SRC
Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
volatile unsigned int | A_B_CNT
volatile unsigned int | DST
Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0.
volatile unsigned int | SRC_DST_BIDX
volatile unsigned int | LINK_BCNTRLD
Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits).
volatile unsigned int | SRC_DST_CIDX
Index between consecutive frames of a Source Block (SRCCIDX) (16 bits) and Index between consecutive frames of a Dest Block (DSTCIDX) (16 bits).
volatile unsigned int | CCNT
Number of Frames in a block (CCNT) (16 bits).

Detailed Description

EDMA3 PaRAM Set.

This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual PaRAM words.

Field Documentation

volatile unsigned int EDMA3_DRV_ParamentryRegs::OPT

OPT field of PaRAM Set

volatile unsigned int EDMA3_DRV_ParamentryRegs::A_B_CNT

Number of bytes in each Array (ACNT) (16 bits) and Number of Arrays in each Frame (BCNT) (16 bits).

volatile unsigned int EDMA3_DRV_ParamentryRegs::SRC_DST_BIDX

Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and Index between consec. arrays of a Destination Frame (DSTBIDX) (16 bits).

If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.

If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes

volatile unsigned int EDMA3_DRV_ParamentryRegs::LINK_BCNTRLD

Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits).

Link field must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking.

B count reload field is relevant only for A-sync transfers.

The documentation for this struct was generated from the following file:
  • edma3_drv.h
Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: EDMA3_DRV_PaRAMRegs Struct Reference

EDMA3_DRV_PaRAMRegs Struct Reference
[EDMA3 Driver Data Structures]

EDMA3 Parameter RAM Set in User Configurable format. More...

#include <edma3_drv.h>

Data Fields

volatile unsigned int | opt
volatile unsigned int | srcAddr
Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
volatile unsigned short | aCnt
Number of bytes in each Array (ACNT).
volatile unsigned short | bCnt
Number of Arrays in each Frame (BCNT).
volatile unsigned int | destAddr
Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0.
volatile short | srcBIdx
Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.
volatile short | destBIdx
Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes.
volatile unsigned short | linkAddr
Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers.
volatile unsigned short | bCntReload
Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers.
volatile short | srcCIdx
Index between consecutive frames of a Source Block (SRCCIDX).
volatile short | destCIdx
Index between consecutive frames of a Dest Block (DSTCIDX).
volatile unsigned short | cCnt
Number of Frames in a block (CCNT).
volatile short | reserved
Reserved.

Detailed Description

EDMA3 Parameter RAM Set in User Configurable format.

This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual fields

Field Documentation

volatile unsigned int EDMA3_DRV_PaRAMRegs::opt

OPT field of PaRAM Set

The documentation for this struct was generated from the following file:
  • edma3_drv.h
Generated on Fri Jan 28 15:45:40 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • g
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- a -

  • A_B_CNT : EDMA3_DRV_ParamentryRegs
  • aCnt : EDMA3_DRV_PaRAMRegs

- b -

  • bCnt : EDMA3_DRV_PaRAMRegs
  • bCntReload : EDMA3_DRV_PaRAMRegs

- c -

  • ccError : EDMA3_DRV_GblConfigParams
  • CCNT : EDMA3_DRV_ParamentryRegs
  • cCnt : EDMA3_DRV_PaRAMRegs
  • configScrMapXbarToEvt : EDMA3_DRV_Instance

- d -

  • destAddr : EDMA3_DRV_PaRAMRegs
  • destBIdx : EDMA3_DRV_PaRAMRegs
  • destCIdx : EDMA3_DRV_PaRAMRegs
  • dmaChannelHwEvtMap : EDMA3_DRV_GblConfigParams
  • dmaChannelPaRAMMap : EDMA3_DRV_GblConfigParams
  • dmaChannelTccMap : EDMA3_DRV_GblConfigParams
  • dmaChPaRAMMapExists : EDMA3_DRV_GblConfigParams
  • dmaMapXbarToChan : EDMA3_DRV_GblXbarToChanConfigParams
  • drvInstInitConfig : EDMA3_DRV_InitConfig , EDMA3_DRV_Instance
  • drvSemHandle : EDMA3_DRV_Instance , EDMA3_DRV_InitConfig
  • drvXbarToEvtMapConfig : EDMA3_DRV_Instance
  • DST : EDMA3_DRV_ParamentryRegs

- e -

  • evtQPri : EDMA3_DRV_GblConfigParams , EDMA3_DRV_EvtQuePriority
  • evtQueueWaterMarkLvl : EDMA3_DRV_GblConfigParams

- g -

  • gblCfgParams : EDMA3_DRV_Object
  • gblerrCb : EDMA3_DRV_InitConfig
  • gblerrCbParams : EDMA3_DRV_Instance
  • gblerrData : EDMA3_DRV_InitConfig
  • globalRegs : EDMA3_DRV_GblConfigParams

- i -

  • isMaster : EDMA3_DRV_InitConfig , EDMA3_DRV_Instance
  • isSlave : EDMA3_DRV_MiscParam
  • itcchEn : EDMA3_DRV_ChainOptions
  • itcintEn : EDMA3_DRV_ChainOptions

- l -

  • LINK_BCNTRLD : EDMA3_DRV_ParamentryRegs
  • linkAddr : EDMA3_DRV_PaRAMRegs

- m -

  • mapXbarToChan : EDMA3_DRV_Instance
  • memProtectionExists : EDMA3_DRV_GblConfigParams

- n -

  • numDmaChannels : EDMA3_DRV_GblConfigParams
  • numEvtQueue : EDMA3_DRV_GblConfigParams
  • numOpens : EDMA3_DRV_Object
  • numPaRAMSets : EDMA3_DRV_GblConfigParams
  • numQdmaChannels : EDMA3_DRV_GblConfigParams
  • numRegions : EDMA3_DRV_GblConfigParams
  • numTccs : EDMA3_DRV_GblConfigParams
  • numTcs : EDMA3_DRV_GblConfigParams

- o -

  • OPT : EDMA3_DRV_ParamentryRegs
  • opt : EDMA3_DRV_PaRAMRegs
  • ownDmaChannels : EDMA3_DRV_InstanceInitConfig
  • ownPaRAMSets : EDMA3_DRV_InstanceInitConfig
  • ownQdmaChannels : EDMA3_DRV_InstanceInitConfig
  • ownTccs : EDMA3_DRV_InstanceInitConfig

- p -

  • param : EDMA3_DRV_MiscParam
  • paRAMId : EDMA3_DRV_ChBoundResources
  • pDrvObjectHandle : EDMA3_DRV_Instance
  • phyCtrllerInstId : EDMA3_DRV_Object

- r -

  • regionId : EDMA3_DRV_InitConfig , EDMA3_DRV_Instance
  • reserved : EDMA3_DRV_PaRAMRegs
  • resMgrInstance : EDMA3_DRV_Instance
  • resvdDmaChannels : EDMA3_DRV_InstanceInitConfig
  • resvdPaRAMSets : EDMA3_DRV_InstanceInitConfig
  • resvdQdmaChannels : EDMA3_DRV_InstanceInitConfig
  • resvdTccs : EDMA3_DRV_InstanceInitConfig

- s -

  • shadowRegs : EDMA3_DRV_Instance
  • SRC : EDMA3_DRV_ParamentryRegs
  • SRC_DST_BIDX : EDMA3_DRV_ParamentryRegs
  • SRC_DST_CIDX : EDMA3_DRV_ParamentryRegs
  • srcAddr : EDMA3_DRV_PaRAMRegs
  • srcBIdx : EDMA3_DRV_PaRAMRegs
  • srcCIdx : EDMA3_DRV_PaRAMRegs
  • state : EDMA3_DRV_Object

- t -

  • tcc : EDMA3_DRV_ChBoundResources
  • tcchEn : EDMA3_DRV_ChainOptions
  • tcDefaultBurstSize : EDMA3_DRV_GblConfigParams
  • tcError : EDMA3_DRV_GblConfigParams
  • tcintEn : EDMA3_DRV_ChainOptions
  • tcRegs : EDMA3_DRV_GblConfigParams
  • trigMode : EDMA3_DRV_ChBoundResources

- x -

  • xferCompleteInt : EDMA3_DRV_GblConfigParams
Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: Alphabetical List

Data Structure Index

E
E
EDMA3_DRV_GblConfigParams EDMA3_DRV_Instance EDMA3_DRV_Object
EDMA3_DRV_ChainOptions EDMA3_DRV_GblXbarToChanConfigParams EDMA3_DRV_InstanceInitConfig EDMA3_DRV_ParamentryRegs
EDMA3_DRV_ChBoundResources EDMA3_DRV_InitConfig EDMA3_DRV_MiscParam EDMA3_DRV_PaRAMRegs
EDMA3_DRV_EvtQuePriority
E
Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: Data Fields - Variables

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • g
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • x

- a -

  • A_B_CNT : EDMA3_DRV_ParamentryRegs
  • aCnt : EDMA3_DRV_PaRAMRegs

- b -

  • bCnt : EDMA3_DRV_PaRAMRegs
  • bCntReload : EDMA3_DRV_PaRAMRegs

- c -

  • ccError : EDMA3_DRV_GblConfigParams
  • CCNT : EDMA3_DRV_ParamentryRegs
  • cCnt : EDMA3_DRV_PaRAMRegs
  • configScrMapXbarToEvt : EDMA3_DRV_Instance

- d -

  • destAddr : EDMA3_DRV_PaRAMRegs
  • destBIdx : EDMA3_DRV_PaRAMRegs
  • destCIdx : EDMA3_DRV_PaRAMRegs
  • dmaChannelHwEvtMap : EDMA3_DRV_GblConfigParams
  • dmaChannelPaRAMMap : EDMA3_DRV_GblConfigParams
  • dmaChannelTccMap : EDMA3_DRV_GblConfigParams
  • dmaChPaRAMMapExists : EDMA3_DRV_GblConfigParams
  • dmaMapXbarToChan : EDMA3_DRV_GblXbarToChanConfigParams
  • drvInstInitConfig : EDMA3_DRV_InitConfig , EDMA3_DRV_Instance
  • drvSemHandle : EDMA3_DRV_Instance , EDMA3_DRV_InitConfig
  • drvXbarToEvtMapConfig : EDMA3_DRV_Instance
  • DST : EDMA3_DRV_ParamentryRegs

- e -

  • evtQPri : EDMA3_DRV_GblConfigParams , EDMA3_DRV_EvtQuePriority
  • evtQueueWaterMarkLvl : EDMA3_DRV_GblConfigParams

- g -

  • gblCfgParams : EDMA3_DRV_Object
  • gblerrCb : EDMA3_DRV_InitConfig
  • gblerrCbParams : EDMA3_DRV_Instance
  • gblerrData : EDMA3_DRV_InitConfig
  • globalRegs : EDMA3_DRV_GblConfigParams

- i -

  • isMaster : EDMA3_DRV_InitConfig , EDMA3_DRV_Instance
  • isSlave : EDMA3_DRV_MiscParam
  • itcchEn : EDMA3_DRV_ChainOptions
  • itcintEn : EDMA3_DRV_ChainOptions

- l -

  • LINK_BCNTRLD : EDMA3_DRV_ParamentryRegs
  • linkAddr : EDMA3_DRV_PaRAMRegs

- m -

  • mapXbarToChan : EDMA3_DRV_Instance
  • memProtectionExists : EDMA3_DRV_GblConfigParams

- n -

  • numDmaChannels : EDMA3_DRV_GblConfigParams
  • numEvtQueue : EDMA3_DRV_GblConfigParams
  • numOpens : EDMA3_DRV_Object
  • numPaRAMSets : EDMA3_DRV_GblConfigParams
  • numQdmaChannels : EDMA3_DRV_GblConfigParams
  • numRegions : EDMA3_DRV_GblConfigParams
  • numTccs : EDMA3_DRV_GblConfigParams
  • numTcs : EDMA3_DRV_GblConfigParams

- o -

  • OPT : EDMA3_DRV_ParamentryRegs
  • opt : EDMA3_DRV_PaRAMRegs
  • ownDmaChannels : EDMA3_DRV_InstanceInitConfig
  • ownPaRAMSets : EDMA3_DRV_InstanceInitConfig
  • ownQdmaChannels : EDMA3_DRV_InstanceInitConfig
  • ownTccs : EDMA3_DRV_InstanceInitConfig

- p -

  • param : EDMA3_DRV_MiscParam
  • paRAMId : EDMA3_DRV_ChBoundResources
  • pDrvObjectHandle : EDMA3_DRV_Instance
  • phyCtrllerInstId : EDMA3_DRV_Object

- r -

  • regionId : EDMA3_DRV_InitConfig , EDMA3_DRV_Instance
  • reserved : EDMA3_DRV_PaRAMRegs
  • resMgrInstance : EDMA3_DRV_Instance
  • resvdDmaChannels : EDMA3_DRV_InstanceInitConfig
  • resvdPaRAMSets : EDMA3_DRV_InstanceInitConfig
  • resvdQdmaChannels : EDMA3_DRV_InstanceInitConfig
  • resvdTccs : EDMA3_DRV_InstanceInitConfig

- s -

  • shadowRegs : EDMA3_DRV_Instance
  • SRC : EDMA3_DRV_ParamentryRegs
  • SRC_DST_BIDX : EDMA3_DRV_ParamentryRegs
  • SRC_DST_CIDX : EDMA3_DRV_ParamentryRegs
  • srcAddr : EDMA3_DRV_PaRAMRegs
  • srcBIdx : EDMA3_DRV_PaRAMRegs
  • srcCIdx : EDMA3_DRV_PaRAMRegs
  • state : EDMA3_DRV_Object

- t -

  • tcc : EDMA3_DRV_ChBoundResources
  • tcchEn : EDMA3_DRV_ChainOptions
  • tcDefaultBurstSize : EDMA3_DRV_GblConfigParams
  • tcError : EDMA3_DRV_GblConfigParams
  • tcintEn : EDMA3_DRV_ChainOptions
  • tcRegs : EDMA3_DRV_GblConfigParams
  • trigMode : EDMA3_DRV_ChBoundResources

- x -

  • xferCompleteInt : EDMA3_DRV_GblConfigParams
Generated on Fri Jan 28 15:45:39 2011 for EDMA3 Driver by doxygen 1.6.1


EDMA3 Driver: Main Page

EDMA3 Driver Documentation

02.11.00

Generated on Fri Jan 28 15:45:37 2011 for EDMA3 Driver by doxygen 1.6.1