EDMA3 Driver: Module Index

  • Main Page
  • Modules
  • Data Structures
  • Files

Modules

Here is a list of all modules:
  • EDMA3 Driver Interface Definition
    • EDMA3 Driver Usage Guidelines
    • EDMA3 Driver Error Codes
    • EDMA3 Driver Channel Setup
    • EDMA3 Driver Typical EDMA Transfer Setup
    • EDMA3 Driver Optional Setup for EDMA
  • Internal Interface Definition for EDMA3 Driver
    • Boundary Values
    • Object Maintenance
Generated on Tue Jul 7 19:18:48 2009 for EDMA3 Driver by doxygen 1.5.9


EDMA3 Driver: EDMA3 Driver Interface Definition

  • Files

EDMA3 Driver Interface Definition

Data Structures

struct | EDMA3_DRV_GblConfigParams
Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...
struct | EDMA3_DRV_InstanceInitConfig
Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information. More...
struct | EDMA3_DRV_InitConfig
Used to Initialize the EDMA3 Driver Instance. More...
struct | EDMA3_DRV_MiscParam
Used to specify the miscellaneous options during EDMA3 Driver Initialization. More...

Modules

EDMA3 Driver Usage Guidelines
EDMA3 Driver Error Codes
Usage of EDMA3 Driver.
EDMA3 Driver Channel Setup
EDMA3 Driver Typical EDMA Transfer Setup
EDMA3 Driver Optional Setup for EDMA

Defines

#define | EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP
#define | EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP

Functions

EDMA3_DRV_Result | EDMA3_DRV_create (unsigned int phyCtrllerInstId, const EDMA3_DRV_GblConfigParams *gblCfgParams, const void *miscParam)
Create EDMA3 Driver Object.
EDMA3_DRV_Result | EDMA3_DRV_delete (unsigned int phyCtrllerInstId, const void *param)
Delete EDMA3 Driver Object.
EDMA3_DRV_Handle | EDMA3_DRV_open (unsigned int phyCtrllerInstId, const EDMA3_DRV_InitConfig *initCfg, EDMA3_DRV_Result *errorCode)
Open EDMA3 Driver Instance.
EDMA3_DRV_Result | EDMA3_DRV_close (EDMA3_DRV_Handle hEdma, const void *param)
Close the EDMA3 Driver Instance.

Detailed Description

Top-level Encapsulation of all documentation for EDMA3 Driver

Define Documentation

#define EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP

This define is used to specify that a DMA channel is NOT tied to any PaRAM Set and hence any available PaRAM Set could be used for that DMA channel. It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.

This value should mandatorily be used to mark DMA channels with no initial mapping to specific PaRAM Sets.

Referenced by EDMA3_DRV_requestChannel().

#define EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP

This define is used to specify that the DMA/QDMA channel is not tied to any TCC and hence any available TCC could be used for that DMA/QDMA channel. It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global configuration structure EDMA3_RM_GblConfigParams.

This value should mandatorily be used to mark DMA channels with no initial mapping to specific TCCs.

Referenced by EDMA3_DRV_requestChannel().

Function Documentation

EDMA3_DRV_Result EDMA3_DRV_close | ( | EDMA3_DRV_Handle | hEdma,
 |  | const void * | param
 | ) |  |

Close the EDMA3 Driver Instance.

This API is used to close a previously opened EDMA3 Driver Instance.

Parameters:
hEdma | [IN] Handle to the previously opened EDMA3 Driver Instance.
param | [IN] For possible future use
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant.

References EDMA3_DRV_Instance::drvInstInitConfig, EDMA3_DRV_CLOSED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_OBJ_NOT_OPENED, EDMA3_DRV_E_RM_CLOSE_FAIL, EDMA3_DRV_OPENED, EDMA3_DRV_Object::numOpens, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::resMgrInstance, EDMA3_DRV_Instance::shadowRegs, and EDMA3_DRV_Object::state.

EDMA3_DRV_Result EDMA3_DRV_create | ( | unsigned int | phyCtrllerInstId,
 |  | const EDMA3_DRV_GblConfigParams * | gblCfgParams,
 |  | const void * | miscParam
 | ) |  |

Create EDMA3 Driver Object.

This API is used to create the EDMA3 Driver Object. It should be called only ONCE for each EDMA3 hardware instance.

Init-time Configuration structure for EDMA3 hardware is provided to pass the SoC specific information. This configuration information could be provided by the user at init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR) and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam' argument is NULL. User can avoid these registers' programming (in some specific use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration structure and passing this structure as the third argument (miscParam).

After successful completion of this API, Driver Object's state changes to EDMA3_DRV_CREATED from EDMA3_DRV_DELETED.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
gblCfgParams | [IN] SoC specific configuration structure for the EDMA3 Hardware.
miscParam | [IN] Misc configuration options provided in the structure 'EDMA3_DRV_MiscParam'. For default options, user can pass NULL in this argument.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code

Used to reset the Internal EDMA3 Driver Data Structures for the first time.

We are NOT checking 'gblCfgParams' for NULL. Whatever user has passed is given to RM. If user passed NULL, config info from config file will be taken else user specific info will be passed to the RM. Similarly, 'miscParam' is not being checked and passed as it is to the Resource Manager layer.

Copy the global config info from the RM object to the driver object for future use.

References EDMA3_DRV_CREATED, EDMA3_DRV_DELETED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_OBJ_NOT_DELETED, EDMA3_DRV_TRIG_MODE_NONE, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_Object::numOpens, EDMA3_DRV_GblConfigParams::numRegions, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Object::state, EDMA3_DRV_ChBoundResources::tcc, and EDMA3_DRV_ChBoundResources::trigMode.

EDMA3_DRV_Result EDMA3_DRV_delete | ( | unsigned int | phyCtrllerInstId,
 |  | const void * | param
 | ) |  |

Delete EDMA3 Driver Object.

Use this API to delete the EDMA3 Driver Object. It should be called only ONCE for each EDMA3 hardware instance. It should be called ONLY after closing all the EDMA3 Driver Instances.

This API is used to delete the EDMA3 Driver Object. It should be called once for each EDMA3 hardware instance, ONLY after closing all the previously opened EDMA3 Driver Instances.

After successful completion of this API, Driver Object's state changes to EDMA3_DRV_DELETED.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Phy Controller Instance Id (Hardware instance id, starting from 0).
param | [IN] For possible future use.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code

If number of Driver Instances is 0, then state should be EDMA3_DRV_CLOSED OR EDMA3_DRV_CREATED.

If number of Driver Instances is NOT 0, then this function SHOULD NOT be called by anybody.

State is correct. Delete the RM Object.

Change state to EDMA3_DRV_DELETED

References EDMA3_DRV_CLOSED, EDMA3_DRV_CREATED, EDMA3_DRV_DELETED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_INVALID_STATE, EDMA3_DRV_E_OBJ_NOT_CLOSED, and EDMA3_DRV_Object::state.

EDMA3_DRV_Handle EDMA3_DRV_open | ( | unsigned int | phyCtrllerInstId,
 |  | const EDMA3_DRV_InitConfig * | initCfg,
 |  | EDMA3_DRV_Result * | errorCode
 | ) |  |

Open EDMA3 Driver Instance.

This API is used to open an EDMA3 Driver Instance. It could be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_REGIONS instances are allowed for each EDMA3 hardware instance. Multiple instances on the same shadow region are NOT allowed.

Also, only ONE Master Driver Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled.

User could pass the instance specific configuration structure (initCfg.drvInstInitConfig) as a part of the 'initCfg' structure, during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

By default, this EDMA3 Driver instance will clear the PaRAM Sets while allocating them. To change the default behavior, user should use the IOCTL interface appropriately.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
initCfg | [IN] Used to Initialize the EDMA3 Driver Instance (Master or Slave).
errorCode | [OUT] Error code while opening DRV instance.
Returns:
EDMA3_DRV_Handle : If successfully opened, the API will return the associated driver's instance handle.
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant.
This API is used to open an EDMA3 Driver Instance. It could be called multiple times, for each possible EDMA3 shadow region. Maximum EDMA3_MAX_REGIONS instances are allowed for each EDMA3 hardware instance. Multiple instances on the same shadow region are NOT allowed.

Also, only ONE Master Driver Instance is permitted. This master instance (and hence the region to which it belongs) will only receive the EDMA3 interrupts, if enabled.

User could pass the instance specific configuration structure (initCfg.drvInstInitConfig) as a part of the 'initCfg' structure, during init-time. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
initCfg | [IN] Used to Initialize the EDMA3 Driver Instance (Master or Slave).
errorCode | [OUT] Error code while opening DRV instance.
Returns:
EDMA3_DRV_Handle : If successfully opened, the API will return the associated driver's instance handle.
Note:
This function disables the global interrupts (by calling API edma3OsProtectEntry with protection level EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data structures, to make it re-entrant.

References EDMA3_DRV_Instance::drvInstInitConfig, EDMA3_DRV_InitConfig::drvInstInitConfig, EDMA3_DRV_Instance::drvSemHandle, EDMA3_DRV_InitConfig::drvSemHandle, EDMA3_DRV_CLOSED, EDMA3_DRV_CREATED, EDMA3_DRV_E_INST_ALREADY_EXISTS, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_INVALID_STATE, EDMA3_DRV_OPENED, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_InitConfig::gblerrCb, EDMA3_DRV_Instance::gblerrCbParams, EDMA3_DRV_InitConfig::gblerrData, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_InitConfig::isMaster, EDMA3_DRV_Instance::isMaster, EDMA3_DRV_Object::numOpens, EDMA3_DRV_GblConfigParams::numRegions, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Instance::regionId, EDMA3_DRV_InitConfig::regionId, EDMA3_DRV_Instance::shadowRegs, and EDMA3_DRV_Object::state.

Generated on Tue Jul 7 19:18:47 2009 for EDMA3 Driver by doxygen 1.5.9


EDMA3 Driver: EDMA3 Driver Usage Guidelines

EDMA3 Driver Usage Guidelines
[EDMA3 Driver Interface Definition]

Guidelines for typical usage of EDMA3 Driver.
Generated on Tue Jul 7 19:18:47 2009 for EDMA3 Driver by doxygen 1.5.9


EDMA3 Driver: EDMA3 Driver Error Codes

EDMA3 Driver Error Codes
[EDMA3 Driver Interface Definition]

Usage of EDMA3 Driver. More...

Defines

#define | EDMA3_DRV_E_BASE (-128)
#define | EDMA3_DRV_E_OBJ_NOT_DELETED (EDMA3_DRV_E_BASE)
#define | EDMA3_DRV_E_OBJ_NOT_CLOSED (EDMA3_DRV_E_BASE-1)
#define | EDMA3_DRV_E_OBJ_NOT_OPENED (EDMA3_DRV_E_BASE-2)
#define | EDMA3_DRV_E_RM_CLOSE_FAIL (EDMA3_DRV_E_BASE-3)
#define | EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-4)
#define | EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-5)
#define | EDMA3_DRV_E_PARAM_SET_UNAVAIL (EDMA3_DRV_E_BASE-6)
#define | EDMA3_DRV_E_TCC_UNAVAIL (EDMA3_DRV_E_BASE-7)
#define | EDMA3_DRV_E_TCC_REGISTER_FAIL (EDMA3_DRV_E_BASE-8)
#define | EDMA3_DRV_E_CH_PARAM_BIND_FAIL (EDMA3_DRV_E_BASE-9)
#define | EDMA3_DRV_E_ADDRESS_NOT_ALIGNED (EDMA3_DRV_E_BASE-10)
#define | EDMA3_DRV_E_INVALID_PARAM (EDMA3_DRV_E_BASE-11)
#define | EDMA3_DRV_E_INVALID_STATE (EDMA3_DRV_E_BASE-12)
#define | EDMA3_DRV_E_INST_ALREADY_EXISTS (EDMA3_DRV_E_BASE-13)
#define | EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED (EDMA3_DRV_E_BASE-14)
#define | EDMA3_DRV_E_SEMAPHORE (EDMA3_DRV_E_BASE-15)
#define | EDMA3_DRV_E_INST_NOT_OPENED (EDMA3_DRV_E_BASE-16)

Detailed Description

Usage of EDMA3 Driver.

  1. Create EDMA3 Driver Object (one for each EDMA3 hardware instance)
    • EDMA3_DRV_Result result = EDMA3_DRV_SOK;
    • unsigned int edma3HwInstanceId = 0;
    • EDMA3_DRV_GblConfigParams *gblCfgParams = NULL;
    • Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. This could be NULL also. In that case, static configuration will be taken.
    • result = EDMA3_DRV_create (edma3HwInstanceId, gblCfgParams, NULL);

  1. Open EDMA3 driver Instance
    • Steps
      • EDMA3_DRV_InitConfig initCfg;
      • EDMA3_DRV_Handle hEdma = NULL;
      • EDMA3_OS_SemAttrs semAttrs = {EDMA3_OS_SEMTYPE_FIFO, NULL};
      • EDMA3_DRV_Result edmaResult; -To get the error code while opening driver instance

  1. initCfg.regionId = One of the possible regions available for eg, (EDMA3_RM_RegionId)0 or (EDMA3_RM_RegionId)1 etc, for different masters.

  1. initCfg.isMaster = TRUE/FALSE (Whether this EDMA3 DRV instance is Master or not. The EDMA3 Shadow Region tied to the Master DRV Instance will ONLY receive the EDMA3 interrupts (error or completion), if enabled).

  1. initCfg.drvSemHandle = EDMA3 DRV Instance specific semaphore handle. It should be provided by the user for proper sharing of resources.
    • edma3Result = edma3OsSemCreate(1, &semAttrs, &initCfg.drvSemHandle);

  1. initCfg.drvInstInitConfig = Init-time Region Specific Configuration Structure. It can be provided by the user at run-time. If not provided by the user, this info would be taken from the platform specific config file, if it exists.

  1. initCfg.drvInstInitConfig->ownDmaChannels[] = The bitmap(s) which indicate the DMA channels owned by this instance of the EDMA3 Driver
    E.g. A '1' at bit position 24 indicates that this instance of the EDMA3 Driver owns DMA Channel Id 24
    Later when a request is made based on a particular Channel Id, the EDMA3 Driver will check first if it owns that channel. If it doesnot own it, EDMA3 Driver returns error.
  2. initCfg.drvInstInitConfig->ownQdmaChannels[] = The bitmap(s) which indicate the QDMA channels owned by this instance of the EDMA3 Driver
  3. initCfg.drvInstInitConfig->ownPaRAMSets[] = The bitmap(s) which indicate the PaRAM Sets owned by this instance of the EDMA3 Driver
  4. initCfg.drvInstInitConfig->ownTccs[] = The bitmap(s) which indicate the TCCs owned by this instance of the EDMA3 Driver

  1. initCfg.drvInstInitConfig->resvdDmaChannels[] = The bitmap(s) which indicate the DMA channels reserved by this instance of the EDMA3 Driver
    E.g. A '1' at bit position 24 indicates that this instance of the EDMA3 Driver reserves Channel Id 24
    These channels are reserved and may be mapped to HW events, these are not given to 'EDMA3_DRV_DMA_CHANNEL_ANY' requests.
  2. initCfg.drvInstInitConfig->resvdQdmaChannels[] = The bitmap(s) which indicate the QDMA channels reserved by this instance of the EDMA3 Driver
    E.g. A '1' at bit position 1 indicates that this instance of the EDMA3 Driver reserves QDMA Channel Id 1
    These channels are reserved for some specific purpose, these are not given to 'EDMA3_DRV_QDMA_CHANNEL_ANY' request
  3. initCfg.drvInstInitConfig->resvdPaRAMSets[] = PaRAM Sets which are reserved by this Region;
  4. initCfg.drvInstInitConfig->resvdTccs[] = TCCs which are reserved by this Region;

  1. initCfg.gblerrCb = Instance wide callback function to catch non-channel specific errors;
  2. initCfg.gblerrData = Application data to be passed back to the callback function;

  1. hEdma = EDMA3_DRV_open(edma3HwInstanceId, &initCfg, &edmaResult);

  1. EDMA3 driver APIs
    • EDMA3_RM_ResDesc resObj;
    • EDMA3_DRV_Result result;
    • unsigned int ch1Id = 0;
    • unsigned int ch2Id = 0;
    • unsigned int tcc1 = 0;
    • unsigned int tcc2 = 0;
    • unsigned int qCh1Id = 0;
    • unsigned int qTcc1 = 0;
    • unsigned int qCh2Id = 0;
    • unsigned int qTcc2 = 0;
    • unsigned int paRAMId;
    • int srcbidx = 0;
    • int desbidx = 0;
    • int srccidx = 0;
    • int descidx = 0;
    • unsigned int acnt = 0;
    • unsigned int bcnt = 0;
    • unsigned int ccnt = 0;
    • unsigned int bcntreload = 0;
    • EDMA3_DRV_SyncType synctype;
    • EDMA3_RM_TccCallback tccCb;
    • void *cbData;
    • Use Case 1: Memory to memory transfer on any available
    • DMA Channel

      • tcc1 = EDMA3_DRV_TCC_ANY;
      • ch1Id = EDMA3_DRV_DMA_CHANNEL_ANY;
      • result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1, (EDMA3_RM_EventQueue)0, &callback1, NULL);

  • result = EDMA3_DRV_setSrcParams (hEdma, ch1Id, (unsigned int)(srcBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
  • result = EDMA3_DRV_setDestParams (hEdma, ch1Id, (unsigned int)(dstBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);

  • Set EDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, SyncType) acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A;
  • result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt, ccnt, bcntreload, synctype);

  • Set srcbidx and srccidx to the appropriate values
  • srcbidx = acnt; srccidx = acnt;
  • result = EDMA3_DRV_setSrcIndex (hEdma, ch1Id, srcbidx, srccidx);

  • Set desbidx and descidx to the appropriate values
  • desbidx = acnt; descidx = acnt;
  • result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);

  • Enable the final completion interrupt.
  • result = EDMA3_DRV_setOptField (hEdma, ch1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);

  • Enable the transfer
  • result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL);

  • Use Case 2: Linked memory to memory transfer on any available
  • DMA Channel

    • Perform steps as for Use Case 1 for the Master logical channel ch1Id for configuration. DONOT enable the transfer for ch1Id.
    • Configure link channel, ch2Id.
    • tcc2 = EDMA3_DRV_TCC_ANY;
    • ch2Id = EDMA3_DRV_LINK_CHANNEL;
    • result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2, (EDMA3_RM_EventQueue)0, &callback2, NULL);

  • result = EDMA3_DRV_setSrcParams (hEdma, ch2Id, (unsigned int)(srcBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
  • result = EDMA3_DRV_setDestParams (hEdma, ch2Id,( unsigned int)(dstBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);

  • result = EDMA3_DRV_setSrcIndex (hEdma, ch2Id, srcbidx, srccidx);
  • result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);

  • result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt, ccnt, bcntreload, synctype);

  • Link both the channels
  • result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id);

  • Enable the final completion interrupts on both the channels
  • result = EDMA3_DRV_setOptField (hEdma, ch1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
  • result = EDMA3_DRV_setOptField (hEdma, ch2Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);

  • Enable the transfer on channel 1.
  • result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL);
  • Wait for the completion interrupt on Ch1 and then enable the transfer again for the LINK channel, to provide the required sync event.
  • result = EDMA3_DRV_enableTransfer (hEdma, ch1Id, EDMA3_DRV_TRIG_MODE_MANUAL);

  • Note: Enabling of transfers on channel 1 (for master and link channel) is required as many number of times as the sync events are required. For ASync mode, number of sync events=(bcnt * ccnt) and for ABSync mode, number of sync events = ccnt.

  • Use Case 3: Memory to memory transfer on any available
  • QDMA Channel

    • qTcc1 = EDMA3_DRV_TCC_ANY;
    • qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;

  • result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1, (EDMA3_RM_EventQueue)0, &callback1, NULL);

  • Set the QDMA trigger word.
  • result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id, EDMA3_RM_QDMA_TRIG_DST);
  • Note: DONOT write the destination address (trigger word) before completing the configuration as it will trigger the transfer. Also, DONOT use EDMA3_DRV_setDestParams() to set the destination address as it also sets other parameters. Use EDMA3_DRV_setPaRAMEntry() to set the destination address

  • result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id, (unsigned int)(srcBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);

  • Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, SyncType) acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A;
  • result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt, ccnt, bcntreload, synctype);

  • srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
  • result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
  • result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);

  • Enable the final completion interrupt.
  • result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);

  • Set the Destination Addressing Mode as Increment
  • result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_ADDR_MODE_INCR);

  • Trigger the QDMA channel by writing the destination address
  • result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_DST, (unsigned int)(dstBuff1));

  • Use Case 4: Linked memory to memory transfer on any available
  • QDMA Channel

    • Setup for any QDMA Channel
    • qTcc1 = EDMA3_DRV_TCC_ANY;
    • qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;
    • result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1, (EDMA3_RM_EventQueue)0, &callback1, NULL);

  • Setup for Channel 2
  • qCh2Id = EDMA3_DRV_LINK_CHANNEL;
  • qTcc2 = EDMA3_DRV_TCC_ANY;
  • result = EDMA3_DRV_requestChannel (hEdma, &qCh2Id, &qTcc2, (EDMA3_RM_EventQueue)0, &callback2, NULL);

  • result = EDMA3_DRV_setSrcParams (hEdma, qCh2Id, (unsigned int)(srcBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);
  • result = EDMA3_DRV_setDestParams(hEdma, qCh2Id, (unsigned int)(dstBuff2), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);

  • acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A;
  • result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt, ccnt, BRCnt, EDMA3_DRV_SYNC_A);

  • srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
  • result = EDMA3_DRV_setSrcIndex (hEdma, qCh2Id, srcbidx, srccidx);
  • result = EDMA3_DRV_setDestIndex (hEdma, qCh2Id, desbidx, descidx);

  • result = EDMA3_DRV_setOptField (hEdma, qCh2Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);

  • Make the PaRAM Set associated with qCh2Id as Static
  • result = EDMA3_DRV_setOptField (hEdma, qCh2Id, EDMA3_DRV_OPT_FIELD_STATIC, 1u);

  • Link both the channels
  • result = EDMA3_DRV_linkChannel (hEdma,qCh1Id,qCh2Id);

  • Set the QDMA trigger word.
  • result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id, EDMA3_DRV_QDMA_TRIG_DST);
  • Note: DONOT write the destination address (trigger word) before completing the configuration as it'll trigger the transfer. Also, DONOT use EDMA3_DRV_setDestParams () function to set the destination address as it also sets other parameters. Use EDMA3_DRV_setPaRAMEntry() to set the dest address.

  • result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id, (unsigned int)(srcBuff1), EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W8BIT);

  • Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload, SyncType) acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0; synctype = EDMA3_DRV_SYNC_A;
  • result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt, ccnt, bcntreload, synctype);

  • srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
  • result = EDMA3_DRV_setSrcIndex (hEdma, qCh1Id, srcbidx, srccidx);
  • result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);

  • result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);

  • Set the Destination Addressing Mode as Increment
  • result = EDMA3_DRV_setOptField (hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_ADDR_MODE_INCR);

  • Trigger the QDMA channel by writing the destination address
  • result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id, EDMA3_DRV_PARAM_ENTRY_DST, (unsigned int)(dstBuff1));

Error Codes returned by the EDMA3 Driver

Define Documentation

#define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED (EDMA3_DRV_E_BASE-10)

The address of the memory location passed as argument is not properly aligned. It should be 32 bytes aligned.

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_E_BASE (-128)

EDMA3 Driver Error Codes Base define

#define EDMA3_DRV_E_CH_PARAM_BIND_FAIL (EDMA3_DRV_E_BASE-9)

The binding of Channel and PaRAM Set failed

Referenced by EDMA3_DRV_requestChannel().

#define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-4)

The requested DMA Channel not available

Referenced by EDMA3_DRV_requestChannel().

#define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED (EDMA3_DRV_E_BASE-14)

FIFO width not supported by the requested TC

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_E_INST_ALREADY_EXISTS (EDMA3_DRV_E_BASE-13)

EDMA3 Driver instance already exists for the specified region

Referenced by EDMA3_DRV_open().

#define EDMA3_DRV_E_INST_NOT_OPENED (EDMA3_DRV_E_BASE-16)

EDMA3 Driver Instance does not exist, it is not opened yet

Referenced by EDMA3_DRV_getInstHandle().

#define EDMA3_DRV_E_INVALID_PARAM (EDMA3_DRV_E_BASE-11)

Invalid Parameter passed to API

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_clearErrorBits(), EDMA3_DRV_close(), EDMA3_DRV_create(), EDMA3_DRV_delete(), EDMA3_DRV_disableLogicalChannel(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getCCRegister(), EDMA3_DRV_getInstHandle(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_Ioctl(), EDMA3_DRV_linkChannel(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_open(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setCCRegister(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), and EDMA3_DRV_waitAndClearTcc().

#define EDMA3_DRV_E_INVALID_STATE (EDMA3_DRV_E_BASE-12)

Invalid State of EDMA3 HW Obj

Referenced by EDMA3_DRV_delete(), and EDMA3_DRV_open().

#define EDMA3_DRV_E_OBJ_NOT_CLOSED (EDMA3_DRV_E_BASE-1)

EDMA3 Driver Object Not Closed yet. So it cannot be deleted.

Referenced by EDMA3_DRV_delete().

#define EDMA3_DRV_E_OBJ_NOT_DELETED (EDMA3_DRV_E_BASE)

EDMA3 Driver Object Not Deleted yet. So it cannot be created.

Referenced by EDMA3_DRV_create().

#define EDMA3_DRV_E_OBJ_NOT_OPENED (EDMA3_DRV_E_BASE-2)

EDMA3 Driver Object Not Opened yet So it cannot be closed.

Referenced by EDMA3_DRV_close().

#define EDMA3_DRV_E_PARAM_SET_UNAVAIL (EDMA3_DRV_E_BASE-6)

The requested PaRAM Set not available

#define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-5)

The requested QDMA Channel not available

Referenced by EDMA3_DRV_requestChannel().

#define EDMA3_DRV_E_RM_CLOSE_FAIL (EDMA3_DRV_E_BASE-3)

While closing EDMA3 Driver, Resource Manager Close Failed.

Referenced by EDMA3_DRV_close().

#define EDMA3_DRV_E_SEMAPHORE (EDMA3_DRV_E_BASE-15)

Semaphore related error

#define EDMA3_DRV_E_TCC_REGISTER_FAIL (EDMA3_DRV_E_BASE-8)

The registration of TCC failed

Referenced by EDMA3_DRV_requestChannel().

#define EDMA3_DRV_E_TCC_UNAVAIL (EDMA3_DRV_E_BASE-7)

The requested TCC not available

Referenced by EDMA3_DRV_requestChannel().

Generated on Tue Jul 7 19:18:47 2009 for EDMA3 Driver by doxygen 1.5.9


EDMA3 Driver: EDMA3 Driver Channel Setup

EDMA3 Driver Channel Setup
[EDMA3 Driver Interface Definition]

Defines

#define | EDMA3_DRV_DMA_CHANNEL_ANY 1002u
#define | EDMA3_DRV_QDMA_CHANNEL_ANY 1003u
#define | EDMA3_DRV_TCC_ANY 1004u
#define | EDMA3_DRV_LINK_CHANNEL 1005u
#define | EDMA3_DRV_QDMA_CHANNEL_0 (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
QDMA Channel defines They should be used while requesting a specific QDMA channel.
#define | EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1u)
#define | EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2u)
#define | EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3u)
#define | EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4u)
#define | EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5u)
#define | EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6u)
#define | EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7u)

Enumerations

enum EDMA3_DRV_HW_CHANNEL_EVENT {
EDMA3_DRV_HW_CHANNEL_EVENT_0 = 0,
EDMA3_DRV_HW_CHANNEL_EVENT_1,
EDMA3_DRV_HW_CHANNEL_EVENT_2,
EDMA3_DRV_HW_CHANNEL_EVENT_3,
EDMA3_DRV_HW_CHANNEL_EVENT_4,
EDMA3_DRV_HW_CHANNEL_EVENT_5,
EDMA3_DRV_HW_CHANNEL_EVENT_6,
EDMA3_DRV_HW_CHANNEL_EVENT_7,
EDMA3_DRV_HW_CHANNEL_EVENT_8,
EDMA3_DRV_HW_CHANNEL_EVENT_9,
EDMA3_DRV_HW_CHANNEL_EVENT_10,
EDMA3_DRV_HW_CHANNEL_EVENT_11,
EDMA3_DRV_HW_CHANNEL_EVENT_12,
EDMA3_DRV_HW_CHANNEL_EVENT_13,
EDMA3_DRV_HW_CHANNEL_EVENT_14,
EDMA3_DRV_HW_CHANNEL_EVENT_15,
EDMA3_DRV_HW_CHANNEL_EVENT_16,
EDMA3_DRV_HW_CHANNEL_EVENT_17,
EDMA3_DRV_HW_CHANNEL_EVENT_18,
EDMA3_DRV_HW_CHANNEL_EVENT_19,
EDMA3_DRV_HW_CHANNEL_EVENT_20,
EDMA3_DRV_HW_CHANNEL_EVENT_21,
EDMA3_DRV_HW_CHANNEL_EVENT_22,
EDMA3_DRV_HW_CHANNEL_EVENT_23,
EDMA3_DRV_HW_CHANNEL_EVENT_24,
EDMA3_DRV_HW_CHANNEL_EVENT_25,
EDMA3_DRV_HW_CHANNEL_EVENT_26,
EDMA3_DRV_HW_CHANNEL_EVENT_27,
EDMA3_DRV_HW_CHANNEL_EVENT_28,
EDMA3_DRV_HW_CHANNEL_EVENT_29,
EDMA3_DRV_HW_CHANNEL_EVENT_30,
EDMA3_DRV_HW_CHANNEL_EVENT_31,
EDMA3_DRV_HW_CHANNEL_EVENT_32,
EDMA3_DRV_HW_CHANNEL_EVENT_33,
EDMA3_DRV_HW_CHANNEL_EVENT_34,
EDMA3_DRV_HW_CHANNEL_EVENT_35,
EDMA3_DRV_HW_CHANNEL_EVENT_36,
EDMA3_DRV_HW_CHANNEL_EVENT_37,
EDMA3_DRV_HW_CHANNEL_EVENT_38,
EDMA3_DRV_HW_CHANNEL_EVENT_39,
EDMA3_DRV_HW_CHANNEL_EVENT_40,
EDMA3_DRV_HW_CHANNEL_EVENT_41,
EDMA3_DRV_HW_CHANNEL_EVENT_42,
EDMA3_DRV_HW_CHANNEL_EVENT_43,
EDMA3_DRV_HW_CHANNEL_EVENT_44,
EDMA3_DRV_HW_CHANNEL_EVENT_45,
EDMA3_DRV_HW_CHANNEL_EVENT_46,
EDMA3_DRV_HW_CHANNEL_EVENT_47,
EDMA3_DRV_HW_CHANNEL_EVENT_48,
EDMA3_DRV_HW_CHANNEL_EVENT_49,
EDMA3_DRV_HW_CHANNEL_EVENT_50,
EDMA3_DRV_HW_CHANNEL_EVENT_51,
EDMA3_DRV_HW_CHANNEL_EVENT_52,
EDMA3_DRV_HW_CHANNEL_EVENT_53,
EDMA3_DRV_HW_CHANNEL_EVENT_54,
EDMA3_DRV_HW_CHANNEL_EVENT_55,
EDMA3_DRV_HW_CHANNEL_EVENT_56,
EDMA3_DRV_HW_CHANNEL_EVENT_57,
EDMA3_DRV_HW_CHANNEL_EVENT_58,
EDMA3_DRV_HW_CHANNEL_EVENT_59,
EDMA3_DRV_HW_CHANNEL_EVENT_60,
EDMA3_DRV_HW_CHANNEL_EVENT_61,
EDMA3_DRV_HW_CHANNEL_EVENT_62,
EDMA3_DRV_HW_CHANNEL_EVENT_63
}
DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed. More...

Functions

EDMA3_DRV_Result | EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma, unsigned int *pLCh, unsigned int *pTcc, EDMA3_RM_EventQueue evtQueue, EDMA3_RM_TccCallback tccCb, void *cbData)
Request a DMA/QDMA/Link channel.
EDMA3_DRV_Result | EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma, unsigned int channelId)
Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings.
EDMA3_DRV_Result | EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma, unsigned int channelId)
Clears Event Register and Error Register for a specific DMA channel and brings back EDMA3 to its initial state.
EDMA3_DRV_Result | EDMA3_DRV_linkChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2)
Link two logical channels.
EDMA3_DRV_Result | EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh)
Unlink the channel from the earlier linked logical channel.

Detailed Description

Channel related Interface of the EDMA3 Driver

Define Documentation

#define EDMA3_DRV_DMA_CHANNEL_ANY 1002u

Used to specify any available DMA Channel while requesting one. Used in the API EDMA3_DRV_requestChannel(). DMA channel from the pool of (owned && non_reserved && available_right_now) DMA channels will be chosen and returned.

Referenced by EDMA3_DRV_requestChannel().

#define EDMA3_DRV_LINK_CHANNEL 1005u

Used to specify any available PaRAM Set while requesting one. Used in the API EDMA3_DRV_requestChannel(), for Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned.

Referenced by EDMA3_DRV_requestChannel().

#define EDMA3_DRV_QDMA_CHANNEL_0 (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)

QDMA Channel defines They should be used while requesting a specific QDMA channel.

QDMA Channel 0

Referenced by EDMA3_DRV_setPaRAMField().

#define EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1u)

QDMA Channel 1

#define EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2u)

QDMA Channel 2

#define EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3u)

QDMA Channel 3

#define EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4u)

QDMA Channel 4

#define EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5u)

QDMA Channel 5

#define EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6u)

QDMA Channel 6

#define EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7u)

QDMA Channel 7

Referenced by EDMA3_DRV_setPaRAMField().

#define EDMA3_DRV_QDMA_CHANNEL_ANY 1003u

Used to specify any available QDMA Channel while requesting one. Used in the API EDMA3_DRV_requestChannel(). QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned.

Referenced by EDMA3_DRV_requestChannel().

#define EDMA3_DRV_TCC_ANY 1004u

Used to specify any available TCC while requesting one. Used in the API EDMA3_DRV_requestChannel(), for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned.

Referenced by EDMA3_DRV_requestChannel().

Enumeration Type Documentation

enum EDMA3_DRV_HW_CHANNEL_EVENT

DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed.

for eg, the sample SoC specific file "soc.h" can have these defines:

define EDMA3_DRV_HW_CHANNEL_MCBSP_TX EDMA3_DRV_HW_CHANNEL_EVENT_2 define EDMA3_DRV_HW_CHANNEL_MCBSP_RX EDMA3_DRV_HW_CHANNEL_EVENT_3

These defines will be used by the MCBSP driver. The same event EDMA3_DRV_HW_CHANNEL_EVENT_2/3 could be mapped to some other peripheral also.

Enumerator:
EDMA3_DRV_HW_CHANNEL_EVENT_0 | Channel assigned to EDMA3 Event 0
EDMA3_DRV_HW_CHANNEL_EVENT_1 | Channel assigned to EDMA3 Event 1
EDMA3_DRV_HW_CHANNEL_EVENT_2 | Channel assigned to EDMA3 Event 2
EDMA3_DRV_HW_CHANNEL_EVENT_3 | Channel assigned to EDMA3 Event 3
EDMA3_DRV_HW_CHANNEL_EVENT_4 | Channel assigned to EDMA3 Event 4
EDMA3_DRV_HW_CHANNEL_EVENT_5 | Channel assigned to EDMA3 Event 5
EDMA3_DRV_HW_CHANNEL_EVENT_6 | Channel assigned to EDMA3 Event 6
EDMA3_DRV_HW_CHANNEL_EVENT_7 | Channel assigned to EDMA3 Event 7
EDMA3_DRV_HW_CHANNEL_EVENT_8 | Channel assigned to EDMA3 Event 8
EDMA3_DRV_HW_CHANNEL_EVENT_9 | Channel assigned to EDMA3 Event 9
EDMA3_DRV_HW_CHANNEL_EVENT_10 | Channel assigned to EDMA3 Event 10
EDMA3_DRV_HW_CHANNEL_EVENT_11 | Channel assigned to EDMA3 Event 11
EDMA3_DRV_HW_CHANNEL_EVENT_12 | Channel assigned to EDMA3 Event 12
EDMA3_DRV_HW_CHANNEL_EVENT_13 | Channel assigned to EDMA3 Event 13
EDMA3_DRV_HW_CHANNEL_EVENT_14 | Channel assigned to EDMA3 Event 14
EDMA3_DRV_HW_CHANNEL_EVENT_15 | Channel assigned to EDMA3 Event 15
EDMA3_DRV_HW_CHANNEL_EVENT_16 | Channel assigned to EDMA3 Event 16
EDMA3_DRV_HW_CHANNEL_EVENT_17 | Channel assigned to EDMA3 Event 17
EDMA3_DRV_HW_CHANNEL_EVENT_18 | Channel assigned to EDMA3 Event 18
EDMA3_DRV_HW_CHANNEL_EVENT_19 | Channel assigned to EDMA3 Event 19
EDMA3_DRV_HW_CHANNEL_EVENT_20 | Channel assigned to EDMA3 Event 20
EDMA3_DRV_HW_CHANNEL_EVENT_21 | Channel assigned to EDMA3 Event 21
EDMA3_DRV_HW_CHANNEL_EVENT_22 | Channel assigned to EDMA3 Event 22
EDMA3_DRV_HW_CHANNEL_EVENT_23 | Channel assigned to EDMA3 Event 23
EDMA3_DRV_HW_CHANNEL_EVENT_24 | Channel assigned to EDMA3 Event 24
EDMA3_DRV_HW_CHANNEL_EVENT_25 | Channel assigned to EDMA3 Event 25
EDMA3_DRV_HW_CHANNEL_EVENT_26 | Channel assigned to EDMA3 Event 26
EDMA3_DRV_HW_CHANNEL_EVENT_27 | Channel assigned to EDMA3 Event 27
EDMA3_DRV_HW_CHANNEL_EVENT_28 | Channel assigned to EDMA3 Event 28
EDMA3_DRV_HW_CHANNEL_EVENT_29 | Channel assigned to EDMA3 Event 29
EDMA3_DRV_HW_CHANNEL_EVENT_30 | Channel assigned to EDMA3 Event 30
EDMA3_DRV_HW_CHANNEL_EVENT_31 | Channel assigned to EDMA3 Event 31
EDMA3_DRV_HW_CHANNEL_EVENT_32 | Channel assigned to EDMA3 Event 32
EDMA3_DRV_HW_CHANNEL_EVENT_33 | Channel assigned to EDMA3 Event 33
EDMA3_DRV_HW_CHANNEL_EVENT_34 | Channel assigned to EDMA3 Event 34
EDMA3_DRV_HW_CHANNEL_EVENT_35 | Channel assigned to EDMA3 Event 35
EDMA3_DRV_HW_CHANNEL_EVENT_36 | Channel assigned to EDMA3 Event 36
EDMA3_DRV_HW_CHANNEL_EVENT_37 | Channel assigned to EDMA3 Event 37
EDMA3_DRV_HW_CHANNEL_EVENT_38 | Channel assigned to EDMA3 Event 38
EDMA3_DRV_HW_CHANNEL_EVENT_39 | Channel assigned to EDMA3 Event 39
EDMA3_DRV_HW_CHANNEL_EVENT_40 | Channel assigned to EDMA3 Event 40
EDMA3_DRV_HW_CHANNEL_EVENT_41 | Channel assigned to EDMA3 Event 41
EDMA3_DRV_HW_CHANNEL_EVENT_42 | Channel assigned to EDMA3 Event 42
EDMA3_DRV_HW_CHANNEL_EVENT_43 | Channel assigned to EDMA3 Event 43
EDMA3_DRV_HW_CHANNEL_EVENT_44 | Channel assigned to EDMA3 Event 44
EDMA3_DRV_HW_CHANNEL_EVENT_45 | Channel assigned to EDMA3 Event 45
EDMA3_DRV_HW_CHANNEL_EVENT_46 | Channel assigned to EDMA3 Event 46
EDMA3_DRV_HW_CHANNEL_EVENT_47 | Channel assigned to EDMA3 Event 47
EDMA3_DRV_HW_CHANNEL_EVENT_48 | Channel assigned to EDMA3 Event 48
EDMA3_DRV_HW_CHANNEL_EVENT_49 | Channel assigned to EDMA3 Event 49
EDMA3_DRV_HW_CHANNEL_EVENT_50 | Channel assigned to EDMA3 Event 50
EDMA3_DRV_HW_CHANNEL_EVENT_51 | Channel assigned to EDMA3 Event 51
EDMA3_DRV_HW_CHANNEL_EVENT_52 | Channel assigned to EDMA3 Event 52
EDMA3_DRV_HW_CHANNEL_EVENT_53 | Channel assigned to EDMA3 Event 53
EDMA3_DRV_HW_CHANNEL_EVENT_54 | Channel assigned to EDMA3 Event 54
EDMA3_DRV_HW_CHANNEL_EVENT_55 | Channel assigned to EDMA3 Event 55
EDMA3_DRV_HW_CHANNEL_EVENT_56 | Channel assigned to EDMA3 Event 56
EDMA3_DRV_HW_CHANNEL_EVENT_57 | Channel assigned to EDMA3 Event 57
EDMA3_DRV_HW_CHANNEL_EVENT_58 | Channel assigned to EDMA3 Event 58
EDMA3_DRV_HW_CHANNEL_EVENT_59 | Channel assigned to EDMA3 Event 59
EDMA3_DRV_HW_CHANNEL_EVENT_60 | Channel assigned to EDMA3 Event 60
EDMA3_DRV_HW_CHANNEL_EVENT_61 | Channel assigned to EDMA3 Event 61
EDMA3_DRV_HW_CHANNEL_EVENT_62 | Channel assigned to EDMA3 Event 62
EDMA3_DRV_HW_CHANNEL_EVENT_63 | Channel assigned to EDMA3 Event 63

Function Documentation

EDMA3_DRV_Result EDMA3_DRV_clearErrorBits | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | channelId
 | ) |  |

Clears Event Register and Error Register for a specific DMA channel and brings back EDMA3 to its initial state.

This API clears the Event register, Event Miss register Event Enable register for a specific DMA channel. It also clears the CC Error register.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
channelId | [IN] DMA Channel needs to be cleaned.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
Note:
This function is re-entrant for unique channelId values. It is non- re-entrant for same channelId value.

References EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numEvtQueue, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::shadowRegs.

EDMA3_DRV_Result EDMA3_DRV_freeChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | channelId
 | ) |  |

Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings.

This API internally uses EDMA3_RM_freeResource () to free the desired resources.

For Link channels, this API only frees the associated PaRAM Set.

For DMA/QDMA channels, it does the following operations: a) Disable any ongoing transfer on the channel, b) Unregister the TCC Callback function and disable the interrupts, c) Remove the channel to Event Queue mapping, d) For DMA channels, clear the DCHMAP register, if available e) For QDMA channels, clear the QCHMAP register, f) Frees the DMA/QDMA channel in the end.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
channelId | [IN] Logical Channel number to be freed.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
Note:
This function disables the global interrupts while modifying the global CC registers and while modifying global data structures, to prevent simultaneous access to the global pool of resources. It internally calls EDMA3_RM_freeResource () for resource de-allocation. It is re-entrant.

References EDMA3_DRV_CHANNEL_TYPE_DMA, EDMA3_DRV_CHANNEL_TYPE_LINK, EDMA3_DRV_CHANNEL_TYPE_NONE, EDMA3_DRV_CHANNEL_TYPE_QDMA, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LINK_CH_MAX_VAL, EDMA3_DRV_LINK_CH_MIN_VAL, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_GblConfigParams::numTccs, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::resMgrInstance, and EDMA3_DRV_ChBoundResources::tcc.

Referenced by EDMA3_DRV_requestChannel().

EDMA3_DRV_Result EDMA3_DRV_linkChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh1,
 |  | unsigned int | lCh2
 | ) |  |

Link two logical channels.

This API is used to link two previously allocated logical (DMA/QDMA/Link) channels.

It sets the Link field of the PaRAM set associated with first logical channel (lCh1) to point it to the PaRAM set associated with second logical channel (lCh2).

It also sets the TCC field of PaRAM set associated with second logical channel to the same as that of the first logical channel.

After linking the channels, user should not update any PaRAM Set of the channel.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
lCh1 | [IN] Logical Channel to which particular channel will be linked.
lCh2 | [IN] Logical Channel which needs to be linked to the first channel. After the transfer based on the PaRAM set of lCh1 is over, the PaRAM set of lCh2 will be copied to the PaRAM set of lCh1 and transfer will resume. For DMA channels, another sync event is required to initiate the transfer on the Link channel.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh1 & lCh2 values. It is non-re-entrant for same lCh1 & lCh2 values.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV_OPT_TCC_GET_MASK, EDMA3_DRV_OPT_TCC_SET_MASK, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_requestChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int * | pLCh,
 |  | unsigned int * | pTcc,
 |  | EDMA3_RM_EventQueue | evtQueue,
 |  | EDMA3_RM_TccCallback | tccCb,
 |  | void * | cbData
 | ) |  |

Request a DMA/QDMA/Link channel.

Each channel (DMA/QDMA/Link) must be requested before initiating a DMA transfer on that channel.

This API is used to allocate a logical channel (DMA/QDMA/Link) along with the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are also allocated along with the requested channel. For Link channel, ONLY a PaRAM Set is allocated.

User can request a specific logical channel by passing the channel id in 'pLCh'. Note that the channel id is the same as the actual resource id in case of DMA channels. To allocate specific QDMA channels, user SHOULD use the defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above.

User can also request ANY available logical channel also by specifying the below mentioned values in '*pLCh': a) EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels b) EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and c) EDMA3_DRV_LINK_CHANNEL: For Link channels. Normally user should use this value to request link channels (PaRAM Sets used for linking purpose only), unless he wants to use some specific link channels (PaRAM Sets) which is also allowed.

This API internally uses EDMA3_RM_allocResource () to allocate the desired resources (DMA/QDMA channel, PaRAM Set and TCC).

This API also registers a specific callback function against the allocated TCC.

For DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets the event queue for the channel allocated. The event queue needs to be specified by the user.

For DMA channel, it also sets the DCHMAP register, if required.

For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and enables the QDMA channel by writing to the QEESR register.

Parameters:
hEdma [IN] Handle to the previously opened Driver Instance.
pLCh [IN/OUT] Requested logical channel id. Examples:
  • EDMA3_DRV_HW_CHANNEL_EVENT_0
  • To request a DMA Master Channel mapped to EDMA Event 0.
  • EDMA3_DRV_DMA_CHANNEL_ANY
  • For requesting any DMA Master channel with no event mapping.

  • EDMA3_DRV_QDMA_CHANNEL_ANY
  • For requesting any QDMA Master channel

  • EDMA3_DRV_QDMA_CHANNEL_0
  • For requesting the QDMA Channel 0.

  • EDMA3_DRV_LINK_CHANNEL
  • For requesting a DMA Slave Channel,
  • to be linked to some other Master
  • channel.

In case user passes a specific channel Id, pLCh value is left unchanged. In case user requests ANY available resource, the allocated channel id is returned in pLCh.

Note:
To request a PaRAM Set for the purpose of linking to another channel, call the function with
*pLCh = EDMA3_DRV_LINK_CHANNEL;

This function will update *pLCh with the allocated Link channel handle. This handle could be DIFFERENT from the actual PaRAM Set allocated by the Resource Manager internally. So user SHOULD NOT assume the handle as the PaRAM Set Id.

Parameters:
pTcc [IN/OUT] The channel number on which the completion/error interrupt is generated. Not used if user requested for a Link channel. Examples:
  • EDMA3_DRV_HW_CHANNEL_EVENT_0
  • To request TCC associated with
  • DMA Master Channel mapped to EDMA
  • event 0.
  • EDMA3_DRV_TCC_ANY
  • For requesting any TCC with no
  • channel mapping. In case user passes a specific TCC value, pTcc value is left unchanged. In case user requests ANY available TCC, the allocated one is returned in pTcc

Parameters:
evtQueue | [IN] Event Queue Number to which the channel will be mapped (valid only for the Master Channel (DMA/QDMA) request)
tccCb | [IN] TCC callback - caters to channel- specific events like "Event Miss Error" or "Transfer Complete"
cbData | [IN] Data which will be passed directly to the tccCb callback function
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error code
Note:
This function internally uses EDMA3 Resource Manager, which acquires a RM Instance specific semaphore to prevent simultaneous access to the global pool of resources. It also disables the global interrupts while modifying the global CC registers. It is re-entrant, but SHOULD NOT be called from the user callback function (ISR context).

Fill the resource id, whose associated TCC needs to be registered. For QDMA channels, pass the actual QDMA channel no instead of (*pLCh).

Map the allocated PaRAM Set to the logical DMa/QDMA channel.

First check whether the mapping feature is supported on the underlying platform. In case it is not supported, dont call this API, because this API returns error in case the feature is not there.

References EDMA3_DRV_GblConfigParams::dmaChannelPaRAMMap, EDMA3_DRV_GblConfigParams::dmaChannelTccMap, EDMA3_DRV_GblConfigParams::dmaChPaRAMMapExists, EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CHANNEL_TYPE_DMA, EDMA3_DRV_CHANNEL_TYPE_QDMA, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMA_CHANNEL_ANY, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_DMAQNUM_SET_MASK, EDMA3_DRV_E_CH_PARAM_BIND_FAIL, EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL, EDMA3_DRV_E_TCC_REGISTER_FAIL, EDMA3_DRV_E_TCC_UNAVAIL, EDMA3_DRV_freeChannel(), EDMA3_DRV_LINK_CH_MAX_VAL, EDMA3_DRV_LINK_CH_MIN_VAL, EDMA3_DRV_LINK_CHANNEL, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV_OPT_TCC_SET_MASK, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMA_CHANNEL_ANY, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_QDMAQNUM_SET_MASK, EDMA3_DRV_TCC_ANY, EDMA3_DRV_TRIG_MODE_NONE, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numDmaChannels, EDMA3_DRV_GblConfigParams::numEvtQueue, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::resMgrInstance, EDMA3_DRV_Instance::shadowRegs, EDMA3_DRV_ChBoundResources::tcc, and EDMA3_DRV_ChBoundResources::trigMode.

EDMA3_DRV_Result EDMA3_DRV_unlinkChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh
 | ) |  |

Unlink the channel from the earlier linked logical channel.

This function breaks the link between the specified channel and the earlier linked logical channel by clearing the Link Address field.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
lCh | [IN] Channel for which linking has to be removed
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

Generated on Tue Jul 7 19:18:47 2009 for EDMA3 Driver by doxygen 1.5.9


EDMA3 Driver: EDMA3 Driver Typical EDMA Transfer Setup

EDMA3 Driver Typical EDMA Transfer Setup
[EDMA3 Driver Interface Definition]

Data Structures

struct | EDMA3_DRV_ChainOptions
Structure to be used to configure interrupt generation and chaining options. More...

Enumerations

enum EDMA3_DRV_OptField {
EDMA3_DRV_OPT_FIELD_SAM = 0,
EDMA3_DRV_OPT_FIELD_DAM = 1,
EDMA3_DRV_OPT_FIELD_SYNCDIM = 2,
EDMA3_DRV_OPT_FIELD_STATIC = 3,
EDMA3_DRV_OPT_FIELD_FWID = 4,
EDMA3_DRV_OPT_FIELD_TCCMODE = 5,
EDMA3_DRV_OPT_FIELD_TCC = 6,
EDMA3_DRV_OPT_FIELD_TCINTEN = 7,
EDMA3_DRV_OPT_FIELD_ITCINTEN = 8,
EDMA3_DRV_OPT_FIELD_TCCHEN = 9,
EDMA3_DRV_OPT_FIELD_ITCCHEN = 10
}
OPT Field Offset. More...
enum EDMA3_DRV_AddrMode {
EDMA3_DRV_ADDR_MODE_INCR = 0,
EDMA3_DRV_ADDR_MODE_FIFO = 1
}
EDMA Addressing modes. More...
enum EDMA3_DRV_SyncType {
EDMA3_DRV_SYNC_A = 0,
EDMA3_DRV_SYNC_AB = 1
}
EDMA Transfer Synchronization type. More...
enum EDMA3_DRV_StaticMode {
EDMA3_DRV_STATIC_DIS = 0,
EDMA3_DRV_STATIC_EN = 1
}
True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted. More...
enum EDMA3_DRV_FifoWidth {
EDMA3_DRV_W8BIT = 0,
EDMA3_DRV_W16BIT = 1,
EDMA3_DRV_W32BIT = 2,
EDMA3_DRV_W64BIT = 3,
EDMA3_DRV_W128BIT = 4,
EDMA3_DRV_W256BIT = 5
}
EDMA3 FIFO width. More...
enum EDMA3_DRV_TccMode {
EDMA3_DRV_TCCMODE_NORMAL = 0,
EDMA3_DRV_TCCMODE_EARLY = 1
}
Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. More...
enum EDMA3_DRV_TcintEn {
EDMA3_DRV_TCINTEN_DIS = 0,
EDMA3_DRV_TCINTEN_EN = 1
}
Transfer complete interrupt enable. More...
enum EDMA3_DRV_ItcintEn {
EDMA3_DRV_ITCINTEN_DIS = 0,
EDMA3_DRV_ITCINTEN_EN = 1
}
Intermediate Transfer complete interrupt enable. More...
enum EDMA3_DRV_TcchEn {
EDMA3_DRV_TCCHEN_DIS = 0,
EDMA3_DRV_TCCHEN_EN = 1
}
Transfer complete chaining enable. More...
enum EDMA3_DRV_ItcchEn {
EDMA3_DRV_ITCCHEN_DIS = 0,
EDMA3_DRV_ITCCHEN_EN = 1
}
Intermediate Transfer complete chaining enable. More...
enum EDMA3_DRV_TrigMode {
EDMA3_DRV_TRIG_MODE_MANUAL = 0,
EDMA3_DRV_TRIG_MODE_QDMA = 1,
EDMA3_DRV_TRIG_MODE_EVENT = 2,
EDMA3_DRV_TRIG_MODE_NONE = 3
}
EDMA Trigger Mode Selection. More...

Functions

EDMA3_DRV_Result | EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int newOptFieldVal)
Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.
EDMA3_DRV_Result | EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_OptField optField, unsigned int *optFieldVal)
Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.
EDMA3_DRV_Result | EDMA3_DRV_setSrcParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int srcAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)
DMA source parameters setup.
EDMA3_DRV_Result | EDMA3_DRV_setDestParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int destAddr, EDMA3_DRV_AddrMode addrMode, EDMA3_DRV_FifoWidth fifoWidth)
DMA Destination parameters setup.
EDMA3_DRV_Result | EDMA3_DRV_setSrcIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh, int srcBIdx, int srcCIdx)
DMA source index setup.
EDMA3_DRV_Result | EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma, unsigned int lCh, int destBIdx, int destCIdx)
DMA destination index setup.
EDMA3_DRV_Result | EDMA3_DRV_setTransferParams (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int aCnt, unsigned int bCnt, unsigned int cCnt, unsigned int bCntReload, EDMA3_DRV_SyncType syncType)
DMA transfer parameters setup.
EDMA3_DRV_Result | EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh1, unsigned int lCh2, const EDMA3_DRV_ChainOptions *chainOptions)
Chain the two specified channels.
EDMA3_DRV_Result | EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh)
Unchain the two channels.
EDMA3_DRV_Result | EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
Start EDMA transfer on the specified channel.
EDMA3_DRV_Result | EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
Disable DMA transfer on the specified channel.
EDMA3_DRV_Result | EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_TrigMode trigMode)
Disable the event driven DMA channel or QDMA channel.

Detailed Description

The typical EDMA transfer related Interface of the EDMA3 Driver

Enumeration Type Documentation

enum EDMA3_DRV_AddrMode

EDMA Addressing modes.

The EDMA3 TC supports two addressing modes

  1. Increment transfer
  2. FIFO transfer

The SAM (Source Addressing Mode) and the DAM (Destination Addressing Mode) can be independently set to either of the two via the OPT register.

Enumerator:
EDMA3_DRV_ADDR_MODE_INCR | Increment (INCR) mode. Source addressing within an array increments. Source is not a FIFO.
EDMA3_DRV_ADDR_MODE_FIFO | FIFO mode. Source addressing within an array wraps around upon reaching FIFO width.

enum EDMA3_DRV_FifoWidth

EDMA3 FIFO width.

The user can set the width of the FIFO using this enum. This is done via the OPT register. This is valid only if the EDMA3_DRV_ADDR_MODE_FIFO value is used for the enum EDMA3_DRV_AddrMode.

Enumerator:
EDMA3_DRV_W8BIT | FIFO width is 8-bit.
EDMA3_DRV_W16BIT | FIFO width is 16-bit.
EDMA3_DRV_W32BIT | FIFO width is 32-bit.
EDMA3_DRV_W64BIT | FIFO width is 64-bit.
EDMA3_DRV_W128BIT | FIFO width is 128-bit.
EDMA3_DRV_W256BIT | FIFO width is 256-bit.

enum EDMA3_DRV_ItcchEn

Intermediate Transfer complete chaining enable.

Enumerator:
EDMA3_DRV_ITCCHEN_DIS | Intermediate Transfer complete chaining is disabled
EDMA3_DRV_ITCCHEN_EN | Intermediate transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on every intermediate chained transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified.

enum EDMA3_DRV_ItcintEn

Intermediate Transfer complete interrupt enable.

Enumerator:
EDMA3_DRV_ITCINTEN_DIS | Intermediate Transfer complete interrupt is disabled
EDMA3_DRV_ITCINTEN_EN | Intermediate transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on every intermediate transfer completion (upon completion of every intermediate TR in the PaRAM set, except the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1.

enum EDMA3_DRV_OptField

OPT Field Offset.

Use this enum to set or get any of the Fields within an OPT of a Parameter RAM set.

Enumerator:
EDMA3_DRV_OPT_FIELD_SAM | Source addressing mode (INCR / FIFO) (Bit 0)
EDMA3_DRV_OPT_FIELD_DAM | Destination addressing mode (INCR / FIFO) (Bit 1)
EDMA3_DRV_OPT_FIELD_SYNCDIM | Transfer synchronization dimension (A-synchronized / AB-synchronized) (Bit 2)
EDMA3_DRV_OPT_FIELD_STATIC | The STATIC field PaRAM set is static/non-static? (Bit 3)
EDMA3_DRV_OPT_FIELD_FWID | FIFO Width. Applies if either SAM or DAM is set to FIFO mode. (Bitfield 8-10)
EDMA3_DRV_OPT_FIELD_TCCMODE | Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation. (Bit 11)
EDMA3_DRV_OPT_FIELD_TCC | Transfer Complete Code (TCC). This 6-bit code is used to set the relevant bit in chaining enable register (CER[TCC]/CERH[TCC]) for chaining or in interrupt pending register (IPR[TCC]/IPRH[TCC]) for interrupts. (Bitfield 12-17)
EDMA3_DRV_OPT_FIELD_TCINTEN | Transfer complete interrupt enable/disable. (Bit 20)
EDMA3_DRV_OPT_FIELD_ITCINTEN | Intermediate transfer complete interrupt enable/disable. (Bit 21)
EDMA3_DRV_OPT_FIELD_TCCHEN | Transfer complete chaining enable/disable (Bit 22)
EDMA3_DRV_OPT_FIELD_ITCCHEN | Intermediate transfer completion chaining enable/disable (Bit 23)

enum EDMA3_DRV_StaticMode

True/False: PaRAM set is Static or not. A Static PaRAM set is updated or linked after TR is submitted.

Enumerator:
EDMA3_DRV_STATIC_DIS | PaRAM set is not Static. PaRAM set is updated or linked after TR is submitted. A value of 0 should be used for DMA channels and for nonfinal transfers in a linked list of QDMA transfers
EDMA3_DRV_STATIC_EN | PaRAM set is Static. PaRAM set is not updated or linked after TR is submitted. A value of 1 should be used for isolated QDMA transfers or for the final transfer in a linked list of QDMA transfers.

enum EDMA3_DRV_SyncType

EDMA Transfer Synchronization type.

Two types of Synchronization of transfers are possible

  1. A Synchronized
  2. AB Syncronized

A Sync

  1. Each Array is submitted as one TR
  2. (BCNT*CCNT) number of sync events are needed to completely service a PaRAM set. (Where BCNT = Num of Arrays in a Frame; CCNT = Num of Frames in a Block)
  3. (S/D)CIDX = (Addr of First array in next frame) minus (Addr of Last array in present frame) (Where CIDX is the Inter-Frame index)

  • AB Sync
    1. Each Frame is submitted as one TR
    2. Only CCNT number of sync events are needed to completely service a PaRAM set
    3. (S/D)CIDX = (Addr of First array in next frame) minus (Addr of First array of present frame)

Note:
ABC sync transfers can be achieved logically by chaining multiple AB sync transfers
Enumerator:
EDMA3_DRV_SYNC_A | A-synchronized. Each event triggers the transfer of a single array of ACNT bytes
EDMA3_DRV_SYNC_AB | AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes

enum EDMA3_DRV_TcchEn

Transfer complete chaining enable.

Enumerator:
EDMA3_DRV_TCCHEN_DIS | Transfer complete chaining is disabled
EDMA3_DRV_TCCHEN_EN | Transfer complete chaining is enabled. When enabled, the chained event register (CER/CERH) bit is set on final chained transfer completion (upon completion of the final / last TR in the PaRAM set). The bit (position) set in CER or CERH is the TCC value specified.

enum EDMA3_DRV_TccMode

Transfer complete code mode. Indicates the point at which a transfer is considered completed for chaining and interrupt generation.

Enumerator:
EDMA3_DRV_TCCMODE_NORMAL | A transfer is considered completed after transfer of data
EDMA3_DRV_TCCMODE_EARLY | A transfer is considered completed after the EDMA3CC submits a TR to the EDMA3TC. TC may still be transferring data when interrupt/chain is triggered.

enum EDMA3_DRV_TcintEn

Transfer complete interrupt enable.

Enumerator:
EDMA3_DRV_TCINTEN_DIS | Transfer complete interrupt is disabled
EDMA3_DRV_TCINTEN_EN | Transfer complete interrupt is enabled. When enabled, the interrupt pending register (IPR/IPRH) bit is set on transfer completion (upon completion of the final TR in the PaRAM set). The bit (position) set in IPR or IPRH is the TCC value specified. In order to generate a completion interrupt to the CPU, the corresponding IER [TCC] / IERH [TCC] bit must be set to 1.

enum EDMA3_DRV_TrigMode

EDMA Trigger Mode Selection.

Use this enum to select the EDMA trigger mode while enabling the EDMA transfer

Enumerator:
EDMA3_DRV_TRIG_MODE_MANUAL | Set the Trigger mode to Manual . The CPU manually triggers a transfer by writing a 1 to the corresponding bit in the event set register (ESR/ESRH).
EDMA3_DRV_TRIG_MODE_QDMA | Set the Trigger mode to QDMA. A QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel parameter set (autotriggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered).
EDMA3_DRV_TRIG_MODE_EVENT | Set the Trigger mode to Event. Allows for a peripheral, system, or externally-generated event to trigger a transfer request.
EDMA3_DRV_TRIG_MODE_NONE | Used to specify the trigger mode NONE

Function Documentation

EDMA3_DRV_Result EDMA3_DRV_chainChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh1,
 |  | unsigned int | lCh2,
 |  | const EDMA3_DRV_ChainOptions * | chainOptions
 | ) |  |

Chain the two specified channels.

This API is used to chain two previously allocated logical (DMA/QDMA) channels.

Chaining is different from Linking. The EDMA3 link feature reloads the current channel parameter set with the linked parameter set. The EDMA3 chaining feature does not modify or update any channel parameter set; it provides a synchronization event to the chained channel.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
lCh1 | [IN] Channel to which particular channel will be chained.
lCh2 | [IN] Channel which needs to be chained to the first channel.
chainOptions | [IN] Options such as intermediate interrupts are required or not, intermediate/final chaining is enabled or not etc.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh1 & lCh2 values. It is non-re-entrant for same lCh1 & lCh2 values.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_ITCCHEN_EN, EDMA3_DRV_ITCINTEN_EN, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_ITCCHEN_CLR_MASK, EDMA3_DRV_OPT_ITCCHEN_SET_MASK, EDMA3_DRV_OPT_ITCINTEN_CLR_MASK, EDMA3_DRV_OPT_ITCINTEN_SET_MASK, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV_OPT_TCC_SET_MASK, EDMA3_DRV_OPT_TCCHEN_CLR_MASK, EDMA3_DRV_OPT_TCCHEN_SET_MASK, EDMA3_DRV_OPT_TCINTEN_CLR_MASK, EDMA3_DRV_OPT_TCINTEN_SET_MASK, EDMA3_DRV_TCCHEN_EN, EDMA3_DRV_TCINTEN_EN, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_ChainOptions::itcchEn, EDMA3_DRV_ChainOptions::itcintEn, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_ChainOptions::tcchEn, EDMA3_DRV_ChainOptions::tcintEn, and EDMA3_DRV_ChBoundResources::trigMode.

EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_TrigMode | trigMode
 | ) |  |

Disable the event driven DMA channel or QDMA channel.

This API disables the DMA channel (which was previously triggered in event mode) by clearing the Event Enable Register; it disables the QDMA channel by clearing the QDMA Event Enable Register.

This API should NOT be used for DMA channels which are not mapped to any hardware events and are used for memory-to-memory copy based transfers. In case of that, this API returns error.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] DMA/QDMA Channel which needs to be disabled
trigMode | [IN] Mode of triggering start of transfer
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_TRIG_MODE_EVENT, EDMA3_DRV_TRIG_MODE_MANUAL, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::shadowRegs.

EDMA3_DRV_Result EDMA3_DRV_disableTransfer | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_TrigMode | trigMode
 | ) |  |

Disable DMA transfer on the specified channel.

There are multiple ways by which an EDMA3 transfer could be triggered. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.

To disable a channel which was previously triggered in manual mode, this API clears the Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.

To disable a channel which was previously triggered in QDMA mode, this API clears the QDMA Event Enable Register, for the specific QDMA channel.

To disable a channel which was previously triggered in event mode, this API clears the Event Enable Register, Event Register, Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Channel on which transfer has to be stopped
trigMode | [IN] Mode of triggering start of transfer
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.
There are multiple ways by which an EDMA3 transfer could be triggered. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.

To disable a channel which was previously triggered in manual mode, this API clears the Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.

To disable a channel which was previously triggered in QDMA mode, this API clears the QDMA Even Enable Register, for the specific QDMA channel.

To disable a channel which was previously triggered in event mode, this API clears the Event Enable Register, Event Register, Secondary Event Register and Event Miss Register, if set, for the specific DMA channel.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Channel on which transfer has to be stopped
trigMode | [IN] Mode of triggering start of transfer
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_TRIG_MODE_EVENT, EDMA3_DRV_TRIG_MODE_MANUAL, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::shadowRegs.

EDMA3_DRV_Result EDMA3_DRV_enableTransfer | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_TrigMode | trigMode
 | ) |  |

Start EDMA transfer on the specified channel.

There are multiple ways to trigger an EDMA3 transfer. The triggering mode option allows choosing from the available triggering modes: Event, Manual or QDMA.

In event triggered, a peripheral or an externally generated event triggers the transfer. This API clears the Event and Event Miss Register and then enables the DMA channel by writing to the EESR.

In manual triggered mode, CPU manually triggers a transfer by writing a 1 in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to start the transfer.

In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set that has been mapped to a QDMA channel (link triggered). This API enables the QDMA channel by writing to the QEESR register.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Channel on which transfer has to be started
trigMode | [IN] Mode of triggering start of transfer (Manual, QDMA or Event)
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_TRIG_MODE_EVENT, EDMA3_DRV_TRIG_MODE_MANUAL, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::shadowRegs, and EDMA3_DRV_ChBoundResources::trigMode.

EDMA3_DRV_Result EDMA3_DRV_getOptField | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_OptField | optField,
 |  | unsigned int * | optFieldVal
 | ) |  |

Get a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.

This API can be used to read various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
lCh | [IN] Logical Channel, bound to which PaRAM set OPT field is required.
optField | [IN] The particular field of OPT Word that is needed
optFieldVal | [IN/OUT] Value of the OPT field
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_DAM_GET_MASK, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_OPT_FIELD_FWID, EDMA3_DRV_OPT_FIELD_ITCCHEN, EDMA3_DRV_OPT_FIELD_ITCINTEN, EDMA3_DRV_OPT_FIELD_SAM, EDMA3_DRV_OPT_FIELD_STATIC, EDMA3_DRV_OPT_FIELD_SYNCDIM, EDMA3_DRV_OPT_FIELD_TCC, EDMA3_DRV_OPT_FIELD_TCCHEN, EDMA3_DRV_OPT_FIELD_TCCMODE, EDMA3_DRV_OPT_FIELD_TCINTEN, EDMA3_DRV_OPT_FWID_GET_MASK, EDMA3_DRV_OPT_ITCCHEN_GET_MASK, EDMA3_DRV_OPT_ITCINTEN_GET_MASK, EDMA3_DRV_OPT_SAM_GET_MASK, EDMA3_DRV_OPT_STATIC_GET_MASK, EDMA3_DRV_OPT_SYNCDIM_GET_MASK, EDMA3_DRV_OPT_TCC_GET_MASK, EDMA3_DRV_OPT_TCCHEN_GET_MASK, EDMA3_DRV_OPT_TCCMODE_GET_MASK, EDMA3_DRV_OPT_TCINTEN_GET_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setDestIndex | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | int | destBIdx,
 |  | int | destCIdx
 | ) |  |

DMA destination index setup.

It is used to program the destination B index and destination C index.

DSTBIDX is a 16-bit signed value (2s complement) used for destination address modification between each array in the 2nd dimension. Valid values for DSTBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-synchronized and AB-synchronized transfers.

DSTCIDX is a 16-bit signed value (2s complement) used for destination address modification in the 3rd dimension. Valid values are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array TR in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when DSTCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in a AB-synchronized transfer is the first array in the frame

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel for which dest indices are to be configured
destBIdx | [IN] Destination B index
destCIdx | [IN] Destination C index
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_DSTBIDX_MAX_VAL, EDMA3_DRV_DSTBIDX_MIN_VAL, EDMA3_DRV_DSTCIDX_MAX_VAL, EDMA3_DRV_DSTCIDX_MIN_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setDestParams | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | unsigned int | destAddr,
 |  | EDMA3_DRV_AddrMode | addrMode,
 |  | EDMA3_DRV_FifoWidth | fifoWidth
 | ) |  |

DMA Destination parameters setup.

It is used to program the destination address, destination side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.

In FIFO Addressing mode, memory location must be 32 bytes aligned.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel for which the destination parameters are to be configured
destAddr | [IN] Destination address
addrMode | [IN] Address mode [FIFO or Increment]
fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO)
  1. 0 - 8 bit
  2. 1 - 16 bit
  3. 2 - 32 bit
  4. 3 - 64 bit
  5. 4 - 128 bit
  6. 5 - 256 bit
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

In FIFO Addressing mode, memory location must be 32 bytes aligned

Memory is not 32 bytes aligned

If request is for FIFO mode, check whether the FIFO size is supported by the Transfer Controller which will be used for this transfer or not.

mappedEvtQ contains the event queue and hence the TC which will process this transfer request. Check whether this TC supports the FIFO size or not.

References EDMA3_DRV_ADDR_MODE_FIFO, EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_E_ADDRESS_NOT_ALIGNED, EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_DAM_CLR_MASK, EDMA3_DRV_OPT_DAM_SET_MASK, EDMA3_DRV_OPT_FWID_CLR_MASK, EDMA3_DRV_OPT_FWID_SET_MASK, EDMA3_DRV_PARAM_ENTRY_DST, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_W256BIT, EDMA3_DRV_W8BIT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, and EDMA3_DRV_GblConfigParams::tcDefaultBurstSize.

EDMA3_DRV_Result EDMA3_DRV_setOptField | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_OptField | optField,
 |  | unsigned int | newOptFieldVal
 | ) |  |

Set a particular OPT field in the PaRAM set associated with the logical channel 'lCh'.

This API can be used to set various optional parameters for an EDMA3 transfer. Like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
lCh | [IN] Logical Channel, bound to which PaRAM set OPT field needs to be set.
optField | [IN] The particular field of OPT Word that needs setting
newOptFieldVal | [IN] The new OPT field value
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_DAM_CLR_MASK, EDMA3_DRV_OPT_DAM_SET_MASK, EDMA3_DRV_OPT_FIELD_DAM, EDMA3_DRV_OPT_FIELD_FWID, EDMA3_DRV_OPT_FIELD_ITCCHEN, EDMA3_DRV_OPT_FIELD_ITCINTEN, EDMA3_DRV_OPT_FIELD_SAM, EDMA3_DRV_OPT_FIELD_STATIC, EDMA3_DRV_OPT_FIELD_SYNCDIM, EDMA3_DRV_OPT_FIELD_TCC, EDMA3_DRV_OPT_FIELD_TCCHEN, EDMA3_DRV_OPT_FIELD_TCCMODE, EDMA3_DRV_OPT_FIELD_TCINTEN, EDMA3_DRV_OPT_FWID_CLR_MASK, EDMA3_DRV_OPT_FWID_SET_MASK, EDMA3_DRV_OPT_ITCCHEN_CLR_MASK, EDMA3_DRV_OPT_ITCCHEN_SET_MASK, EDMA3_DRV_OPT_ITCINTEN_CLR_MASK, EDMA3_DRV_OPT_ITCINTEN_SET_MASK, EDMA3_DRV_OPT_SAM_CLR_MASK, EDMA3_DRV_OPT_SAM_SET_MASK, EDMA3_DRV_OPT_STATIC_CLR_MASK, EDMA3_DRV_OPT_STATIC_SET_MASK, EDMA3_DRV_OPT_SYNCDIM_CLR_MASK, EDMA3_DRV_OPT_SYNCDIM_SET_MASK, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV_OPT_TCC_SET_MASK, EDMA3_DRV_OPT_TCCHEN_CLR_MASK, EDMA3_DRV_OPT_TCCHEN_SET_MASK, EDMA3_DRV_OPT_TCCMODE_CLR_MASK, EDMA3_DRV_OPT_TCCMODE_SET_MASK, EDMA3_DRV_OPT_TCINTEN_CLR_MASK, EDMA3_DRV_OPT_TCINTEN_SET_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setSrcIndex | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | int | srcBIdx,
 |  | int | srcCIdx
 | ) |  |

DMA source index setup.

It is used to program the source B index and source C index.

SRCBIDX is a 16-bit signed value (2s complement) used for source address modification between each array in the 2nd dimension. Valid values for SRCBIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-synchronized and AB-synchronized transfers.

SRCCIDX is a 16-bit signed value (2s complement) used for source address modification in the 3rd dimension. Valid values for SRCCIDX are between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-synchronized and AB-synchronized transfers. Note that when SRCCIDX is applied, the current array in an A-synchronized transfer is the last array in the frame, while the current array in an AB-synchronized transfer is the first array in the frame.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel for which source indices are to be configured
srcBIdx | [IN] Source B index
srcCIdx | [IN] Source C index
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_SRCBIDX_MAX_VAL, EDMA3_DRV_SRCBIDX_MIN_VAL, EDMA3_DRV_SRCCIDX_MAX_VAL, EDMA3_DRV_SRCCIDX_MIN_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setSrcParams | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | unsigned int | srcAddr,
 |  | EDMA3_DRV_AddrMode | addrMode,
 |  | EDMA3_DRV_FifoWidth | fifoWidth
 | ) |  |

DMA source parameters setup.

It is used to program the source address, source side addressing mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.

In FIFO Addressing mode, memory location must be 32 bytes aligned.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel for which the source parameters are to be configured
srcAddr | [IN] Source address
addrMode | [IN] Address mode [FIFO or Increment]
fifoWidth [IN] Width of FIFO (Valid only if addrMode is FIFO)
  1. 0 - 8 bit
  2. 1 - 16 bit
  3. 2 - 32 bit
  4. 3 - 64 bit
  5. 4 - 128 bit
  6. 5 - 256 bit
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

In FIFO Addressing mode, memory location must be 32 bytes aligned

Memory is not 32 bytes aligned

If request is for FIFO mode, check whether the FIFO size is supported by the Transfer Controller which will be used for this transfer or not.

mappedEvtQ contains the event queue and hence the TC which will process this transfer request. Check whether this TC supports the FIFO size or not.

References EDMA3_DRV_ADDR_MODE_FIFO, EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_E_ADDRESS_NOT_ALIGNED, EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_FWID_CLR_MASK, EDMA3_DRV_OPT_FWID_SET_MASK, EDMA3_DRV_OPT_SAM_CLR_MASK, EDMA3_DRV_OPT_SAM_SET_MASK, EDMA3_DRV_PARAM_ENTRY_SRC, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_W256BIT, EDMA3_DRV_W8BIT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, and EDMA3_DRV_GblConfigParams::tcDefaultBurstSize.

EDMA3_DRV_Result EDMA3_DRV_setTransferParams | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | unsigned int | aCnt,
 |  | unsigned int | bCnt,
 |  | unsigned int | cCnt,
 |  | unsigned int | bCntReload,
 |  | EDMA3_DRV_SyncType | syncType
 | ) |  |

DMA transfer parameters setup.

It is used to specify the various counts (ACNT, BCNT and CCNT), B count reload and the synchronization type

ACNT represents the number of bytes within the 1st dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K - 1 bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to EDMA3 Transfer Controller. An ACNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.

BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT are between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K - 1 arrays). A BCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT.

CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT are between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K - 1 frames). A CCNT equal to 0 is considered either a null or dummy transfer. A dummy or null transfer generates a completion code depending on the settings of the completion bit fields in OPT. A CCNT value of 0 is considered either a null or dummy transfer.

BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-synchronized transfers. In this case, the EDMA3CC decrements the BCNT value by 1 on each TR submission. When BCNT (conceptually) reaches 0, the EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel for which transfer parameters are to be configured
aCnt | [IN] Count for 1st Dimension.
bCnt | [IN] Count for 2nd Dimension.
cCnt | [IN] Count for 3rd Dimension.
bCntReload | [IN] Reload value for bCnt.
syncType | [IN] Transfer synchronization dimension 0: A-synchronized. Each event triggers the transfer of a single array of ACNT bytes. 1: AB-synchronized. Each event triggers the transfer of BCNT arrays of ACNT bytes.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_ACNT_MAX_VAL, EDMA3_DRV_BCNT_MAX_VAL, EDMA3_DRV_BCNTRELD_MAX_VAL, EDMA3_DRV_CCNT_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_SYNCDIM_CLR_MASK, EDMA3_DRV_OPT_SYNCDIM_SET_MASK, EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_SYNC_A, EDMA3_DRV_SYNC_AB, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_unchainChannel | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh
 | ) |  |

Unchain the two channels.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance.
lCh | [IN] Channel whose chaining with the other channel has to be removed.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_ITCCHEN_CLR_MASK, EDMA3_DRV_OPT_TCCHEN_CLR_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.


EDMA3 Driver: EDMA3 Driver Optional Setup for EDMA

EDMA3 Driver Optional Setup for EDMA
[EDMA3 Driver Interface Definition]

Data Structures

struct | EDMA3_DRV_ParamentryRegs
EDMA3 PaRAM Set. More...
struct | EDMA3_DRV_PaRAMRegs
EDMA3 Parameter RAM Set in User Configurable format. More...
struct | EDMA3_DRV_EvtQuePriority
Event queue priorities setup. More...

Enumerations

enum EDMA3_DRV_PaRAMEntry {
EDMA3_DRV_PARAM_ENTRY_OPT = 0,
EDMA3_DRV_PARAM_ENTRY_SRC = 1,
EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2,
EDMA3_DRV_PARAM_ENTRY_DST = 3,
EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4,
EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5,
EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6,
EDMA3_DRV_PARAM_ENTRY_CCNT = 7
}
PaRAM Set Entry type. More...
enum EDMA3_DRV_PaRAMField {
EDMA3_DRV_PARAM_FIELD_OPT = 0,
EDMA3_DRV_PARAM_FIELD_SRCADDR = 1,
EDMA3_DRV_PARAM_FIELD_ACNT = 2,
EDMA3_DRV_PARAM_FIELD_BCNT = 3,
EDMA3_DRV_PARAM_FIELD_DESTADDR = 4,
EDMA3_DRV_PARAM_FIELD_SRCBIDX = 5,
EDMA3_DRV_PARAM_FIELD_DESTBIDX = 6,
EDMA3_DRV_PARAM_FIELD_LINKADDR = 7,
EDMA3_DRV_PARAM_FIELD_BCNTRELOAD = 8,
EDMA3_DRV_PARAM_FIELD_SRCCIDX = 9,
EDMA3_DRV_PARAM_FIELD_DESTCIDX = 10,
EDMA3_DRV_PARAM_FIELD_CCNT = 11
}
PaRAM Set Field type. More...
enum EDMA3_DRV_IoctlCmd {
EDMA3_DRV_IOCTL_MIN_IOCTL = 0,
EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION,
EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION,
EDMA3_DRV_IOCTL_MAX_IOCTL
}
EDMA3 Driver IOCTL commands. More...

Functions

EDMA3_DRV_Result | EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)
Assign a Trigger Word to the specified QDMA channel.
EDMA3_DRV_Result | EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle hEdma, unsigned int lCh, const EDMA3_DRV_PaRAMRegs *newPaRAM)
Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).
EDMA3_DRV_Result | EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMRegs *currPaRAM)
Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).
EDMA3_DRV_Result | EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int newPaRAMEntryVal)
Set a particular PaRAM set entry of the specified PaRAM set.
EDMA3_DRV_Result | EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int *paRAMEntryVal)
Get a particular PaRAM set entry of the specified PaRAM set.
EDMA3_DRV_Result | EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int newPaRAMFieldVal)
Set a particular PaRAM set field of the specified PaRAM set.
EDMA3_DRV_Result | EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int *currPaRAMFieldVal)
Get a particular PaRAM set field of the specified PaRAM set.
EDMA3_DRV_Result | EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma, const EDMA3_DRV_EvtQuePriority *evtQPriObj)
Sets EDMA TC priority.
EDMA3_DRV_Result | EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)
Associate Channel to Event Queue.
EDMA3_DRV_Result | EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)
Get the Event Queue mapped to the specified DMA/QDMA channel.
EDMA3_DRV_Result | EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)
Set the Channel Controller (CC) Register value.
EDMA3_DRV_Result | EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)
Get the Channel Controller (CC) Register value.
EDMA3_DRV_Result | EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma, unsigned int tccNo)
Wait for a transfer completion interrupt to occur and clear it.
EDMA3_DRV_Result | EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)
Returns the status of a previously initiated transfer.
EDMA3_DRV_Result | EDMA3_DRV_getPaRAMPhyAddr (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)
Get the PaRAM Set Physical Address associated with a logical channel.
EDMA3_DRV_Result | EDMA3_DRV_Ioctl (EDMA3_DRV_Handle hEdma, EDMA3_DRV_IoctlCmd cmd, void *cmdArg, void *param)
EDMA3 Driver IOCTL.
EDMA3_DRV_Handle | EDMA3_DRV_getInstHandle (unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)
Return the previously opened EDMA3 Driver Instance handle.

Detailed Description

Transfer.

The Optional EDMA transfer related Interface of the EDMA3 Driver

Enumeration Type Documentation

enum EDMA3_DRV_IoctlCmd

EDMA3 Driver IOCTL commands.

Enumerator:
EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION PaRAM Sets will be cleared OR will not be cleared during allocation, depending upon this option.

For e.g., To clear the PaRAM Sets during allocation, cmdArg = (void *)1;

To NOT clear the PaRAM Sets during allocation, cmdArg = (void *)0;

For all other values, it will return error.

By default, PaRAM Sets will be cleared during allocation. Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources.

EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION To check whether PaRAM Sets will be cleared or not during allocation. If the value read is '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation.

For e.g., unsigned short isParamClearingDone; cmdArg =

enum EDMA3_DRV_PaRAMEntry

PaRAM Set Entry type.

Use this enum to set or get any of the 8 DWords(unsigned int) within a Parameter RAM set

Enumerator:
EDMA3_DRV_PARAM_ENTRY_OPT | The OPT field (Offset Address 0x0 Bytes)
EDMA3_DRV_PARAM_ENTRY_SRC | The SRC field (Offset Address 0x4 Bytes)
EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT | The (ACNT+BCNT) field (Offset Address 0x8 Bytes)
EDMA3_DRV_PARAM_ENTRY_DST | The DST field (Offset Address 0xC Bytes)
EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX | The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes)
EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD | The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes)
EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX | The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes)
EDMA3_DRV_PARAM_ENTRY_CCNT | The (CCNT+RSVD) field (Offset Address 0x1C Bytes)

enum EDMA3_DRV_PaRAMField

PaRAM Set Field type.

Use this enum to set or get any of the PaRAM set fields

Enumerator:
EDMA3_DRV_PARAM_FIELD_OPT | OPT field of PaRAM Set
EDMA3_DRV_PARAM_FIELD_SRCADDR | Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
EDMA3_DRV_PARAM_FIELD_ACNT | Number of bytes in each Array (ACNT).
EDMA3_DRV_PARAM_FIELD_BCNT | Number of Arrays in each Frame (BCNT).
EDMA3_DRV_PARAM_FIELD_DESTADDR | Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address.
EDMA3_DRV_PARAM_FIELD_SRCBIDX | Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.
EDMA3_DRV_PARAM_FIELD_DESTBIDX | Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes.
EDMA3_DRV_PARAM_FIELD_LINKADDR | Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers.
EDMA3_DRV_PARAM_FIELD_BCNTRELOAD | Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers.
EDMA3_DRV_PARAM_FIELD_SRCCIDX | Index between consecutive frames of a Source Block (SRCCIDX).
EDMA3_DRV_PARAM_FIELD_DESTCIDX | Index between consecutive frames of a Dest Block (DSTCIDX).
EDMA3_DRV_PARAM_FIELD_CCNT | Number of Frames in a block (CCNT).

Function Documentation

EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | tccNo,
 |  | unsigned short * | tccStatus
 | ) |  |

Returns the status of a previously initiated transfer.

This is a non-blocking function that returns the status of a previously initiated transfer, based on the IPR/IPRH bit. This bit corresponds to the tccNo specified by the user. It clears the corresponding bit, if SET, while returning also.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
tccNo | [IN] TCC, specific to which the function checks the status of the IPR/IPRH bit.
tccStatus | [IN/OUT] Status of the transfer is returned here. Returns "TRUE" if the transfer has completed (IPR/IPRH bit SET), "FALSE" if the transfer has not completed successfully (IPR/IPRH bit NOT SET).
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for different tccNo.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numTccs, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::regionId.

EDMA3_DRV_Result EDMA3_DRV_getCCRegister | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | regOffset,
 |  | unsigned int * | regValue
 | ) |  |

Get the Channel Controller (CC) Register value.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
regOffset | [IN] CC Register offset whose value is needed
regValue | [IN/OUT] CC Register Value
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle.

EDMA3_DRV_Handle EDMA3_DRV_getInstHandle | ( | unsigned int | phyCtrllerInstId,
 |  | EDMA3_RM_RegionId | regionId,
 |  | EDMA3_DRV_Result * | errorCode
 | ) |  |

Return the previously opened EDMA3 Driver Instance handle.

This API is used to return the previously opened EDMA3 Driver's Instance Handle (region specific), which could be used to call other EDMA3 Driver APIs. Since EDMA3 Driver does not allow multiple instances, for a single shadow region, this API is provided. This API is meant for users who DO NOT want to / could not open a new Driver Instance and hence re-use the existing Driver Instance to allocate EDMA3 resources and use various other EDMA3 Driver APIs.

In case the Driver Instance is not yet opened, NULL is returned as the function return value whereas EDMA3_DRV_E_INST_NOT_OPENED is returned in the errorCode.

Parameters:
phyCtrllerInstId | [IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
regionId | [IN] Shadow Region id for which the previously opened driver's instance handle is required.
errorCode | [OUT] Error code while returning Driver Instance Handle.
Returns:
EDMA3_DRV_Handle : If successful, this API will return the driver's instance handle.
Note:
1) This API returns the previously opened EDMA3 Driver's Instance handle. The instance, if exists, could have been opened by some other user (most probably) or may be by the same user calling this API. If it was opened by some other user, then that user can very well close this instance anytime, without even knowing that the same instance handle is being used by other users as well. In that case, the handle becomes INVALID and user has to open a valid driver instance for his/her use.
2) This function is re-entrant.

References EDMA3_DRV_E_INST_NOT_OPENED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::numRegions, and EDMA3_DRV_Instance::pDrvObjectHandle.

EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | channelId,
 |  | unsigned int * | mappedEvtQ
 | ) |  |

Get the Event Queue mapped to the specified DMA/QDMA channel.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
channelId | [IN] Logical Channel whose associated Event Queue is needed
mappedEvtQ | [IN/OUT] The Event Queue which is mapped to the DMA/QDMA channel
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.

References EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle.

EDMA3_DRV_Result EDMA3_DRV_getPaRAM | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_PaRAMRegs * | currPaRAM
 | ) |  |

Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).

Parameters:
hEdma | [IN] Handle to the EDMA Instance object
lCh | [IN] Logical Channel whose PaRAM set is requested
currPaRAM | [IN/OUT] User gets the existing PaRAM here
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_PaRAMEntry | paRAMEntry,
 |  | unsigned int * | paRAMEntryVal
 | ) |  |

Get a particular PaRAM set entry of the specified PaRAM set.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel bound to the Parameter RAM set whose specified field value is needed
paRAMEntry | [IN] Specify the PaRAM set entry which needs to be obtained
paRAMEntryVal | [IN/OUT] The value of the field is returned here
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_getPaRAMField | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_PaRAMField | paRAMField,
 |  | unsigned int * | currPaRAMFieldVal
 | ) |  |

Get a particular PaRAM set field of the specified PaRAM set.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel bound to the PaRAM set whose specified field value is needed
paRAMField | [IN] Specify the PaRAM set field which needs to be obtained
currPaRAMFieldVal | [IN/OUT] The value of the field is returned here
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_DST, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_PARAM_ENTRY_SRC, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_PARAM_FIELD_ACNT, EDMA3_DRV_PARAM_FIELD_BCNT, EDMA3_DRV_PARAM_FIELD_BCNTRELOAD, EDMA3_DRV_PARAM_FIELD_CCNT, EDMA3_DRV_PARAM_FIELD_DESTADDR, EDMA3_DRV_PARAM_FIELD_DESTBIDX, EDMA3_DRV_PARAM_FIELD_DESTCIDX, EDMA3_DRV_PARAM_FIELD_LINKADDR, EDMA3_DRV_PARAM_FIELD_OPT, EDMA3_DRV_PARAM_FIELD_SRCADDR, EDMA3_DRV_PARAM_FIELD_SRCBIDX, EDMA3_DRV_PARAM_FIELD_SRCCIDX, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | unsigned int * | paramPhyAddr
 | ) |  |

Get the PaRAM Set Physical Address associated with a logical channel.

This function returns the PaRAM Set Phy Address (unsigned 32 bits). The returned address could be used by the advanced users to program the PaRAM Set directly without using any APIs.

Least significant 16 bits of this address could be used to program the LINK field in the PaRAM Set. Users which program the LINK field directly SHOULD use this API to get the associated PaRAM Set address with the LINK channel.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel for which the PaRAM set physical address is required
paramPhyAddr | [IN/OUT] PaRAM Set physical address is returned here.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_Ioctl | ( | EDMA3_DRV_Handle | hEdma,
 |  | EDMA3_DRV_IoctlCmd | cmd,
 |  | void * | cmdArg,
 |  | void * | param
 | ) |  |

EDMA3 Driver IOCTL.

This function provides IOCTL functionality for EDMA3 Driver.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
cmd | [IN] IOCTL command to be performed
cmdArg | [IN/OUT] IOCTL command argument (if any)
param | [IN/OUT] Device/Cmd specific argument
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
For 'EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant. For 'EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for different EDMA3 Driver Instances (handles).
This function provides IOCTL functionality for EDMA3 Driver.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
cmd | [IN] IOCTL command to be performed
cmdArg | [IN/OUT] IOCTL command argument (if any)
param | [IN/OUT] Device/Cmd specific argument
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION, EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION, and EDMA3_DRV_Instance::resMgrInstance.

EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | channelId,
 |  | EDMA3_RM_EventQueue | eventQ
 | ) |  |

Associate Channel to Event Queue.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
channelId | [IN] Logical Channel to which the Event Queue is to be mapped
eventQ | [IN] The Event Queue which is to be mapped to the DMA channel
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
There should not be any data transfer going on while setting the mapping. Results could be unpredictable.
This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant.

References EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_DMAQNUM_SET_MASK, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_QDMAQNUM_SET_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numEvtQueue, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setCCRegister | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | regOffset,
 |  | unsigned int | newRegValue
 | ) |  |

Set the Channel Controller (CC) Register value.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
regOffset | [IN] CC Register offset whose value needs to be set
newRegValue | [IN] New CC Register Value
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is non re-entrant for users using the same EDMA handle i.e. working on the same shadow region. Before modifying a register, it tries to acquire a semaphore (Driver instance specific), to protect simultaneous modification of the same register by two different users. After the successful change, it releases the semaphore. For users working on different shadow regions, thus different EDMA handles, this function is re-entrant.

Take the instance specific semaphore, to prevent simultaneous access to the shared resources.

References EDMA3_DRV_Instance::drvSemHandle, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle.

EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority | ( | EDMA3_DRV_Handle | hEdma,
 |  | const EDMA3_DRV_EvtQuePriority * | evtQPriObj
 | ) |  |

Sets EDMA TC priority.

User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Ctrllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc)

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
evtQPriObj | [IN] Priority of the Event Queues
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_QPRIORITY_MAX_VAL, EDMA3_DRV_EvtQuePriority::evtQPri, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setPaRAM | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | const EDMA3_DRV_PaRAMRegs * | newPaRAM
 | ) |  |

Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).

This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set associated with the logical channel. OPT field of the PaRAM Set is written first and the CCNT field is written last.

Caution: It should be used carefully when programming the QDMA channels whose trigger words are not CCNT field.

Parameters:
hEdma | [IN] Handle to the EDMA Instance object
lCh | [IN] Logical Channel for which new PaRAM set is specified
newPaRAM | [IN] Parameter RAM set to be copied onto existing PaRAM
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_PaRAMEntry | paRAMEntry,
 |  | unsigned int | newPaRAMEntryVal
 | ) |  |

Set a particular PaRAM set entry of the specified PaRAM set.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel bound to the Parameter RAM set whose specified field needs to be set
paRAMEntry | [IN] Specify the PaRAM set entry which needs to be set
newPaRAMEntryVal | [IN] The new field setting
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This API should be used while setting the PaRAM set entry for QDMA channels. If EDMA3_DRV_setPaRAMField () used, it will trigger the QDMA channel before complete PaRAM set entry is written. For DMA channels, no such constraint is there.
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setPaRAMField | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_DRV_PaRAMField | paRAMField,
 |  | unsigned int | newPaRAMFieldVal
 | ) |  |

Set a particular PaRAM set field of the specified PaRAM set.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
lCh | [IN] Logical Channel bound to the PaRAM set whose specified field needs to be set
paRAMField | [IN] Specify the PaRAM set field which needs to be set
newPaRAMFieldVal | [IN] The new field setting
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This API CANNOT be used while setting the PaRAM set field for QDMA channels. It can trigger the QDMA channel before complete PaRAM set ENTRY (4-bytes field) is written (for eg, as soon one sets the ACNT field for QDMA channel, transfer is started, before one modifies the BCNT field). For DMA channels, no such constraint is there.
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_DST, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_PARAM_ENTRY_SRC, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_PARAM_FIELD_ACNT, EDMA3_DRV_PARAM_FIELD_BCNT, EDMA3_DRV_PARAM_FIELD_BCNTRELOAD, EDMA3_DRV_PARAM_FIELD_CCNT, EDMA3_DRV_PARAM_FIELD_DESTADDR, EDMA3_DRV_PARAM_FIELD_DESTBIDX, EDMA3_DRV_PARAM_FIELD_DESTCIDX, EDMA3_DRV_PARAM_FIELD_LINKADDR, EDMA3_DRV_PARAM_FIELD_OPT, EDMA3_DRV_PARAM_FIELD_SRCADDR, EDMA3_DRV_PARAM_FIELD_SRCBIDX, EDMA3_DRV_PARAM_FIELD_SRCCIDX, EDMA3_DRV_QDMA_CHANNEL_0, EDMA3_DRV_QDMA_CHANNEL_7, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | lCh,
 |  | EDMA3_RM_QdmaTrigWord | trigWord
 | ) |  |

Assign a Trigger Word to the specified QDMA channel.

This API sets the Trigger word for the specific QDMA channel in the QCHMAP Register. Default QDMA trigger word is CCNT.

Parameters:
hEdma | [IN] Handle to the EDMA Instance object
lCh | [IN] QDMA Channel which needs to be assigned the Trigger Word
trigWord | [IN] The Trigger Word for the QDMA channel. Trigger Word is the word in the PaRAM Register Set which, when written to by CPU, will start the QDMA transfer automatically.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_QCH_TRWORD_CLR_MASK, EDMA3_DRV_QCH_TRWORD_SET_MASK, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle.

EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc | ( | EDMA3_DRV_Handle | hEdma,
 |  | unsigned int | tccNo
 | ) |  |

Wait for a transfer completion interrupt to occur and clear it.

This is a blocking function that returns when the IPR/IPRH bit corresponding to the tccNo specified, is SET. It clears the corresponding bit while returning also.

This function waits for the specific bit indefinitely in a tight loop, with out any delay in between. USE IT CAUTIOUSLY.

Parameters:
hEdma | [IN] Handle to the EDMA Driver Instance
tccNo | [IN] TCC, specific to which the function waits on a IPR/IPRH bit.
Returns:
EDMA3_DRV_SOK or EDMA3_DRV Error Code
Note:
This function is re-entrant for different tccNo.

Bit found SET, transfer is completed, clear the pending interrupt and return.

Bit found SET, transfer is completed, clear the pending interrupt and return.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numTccs, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::regionId.


EDMA3 Driver: Internal Interface Definition for EDMA3 Driver

Internal Interface Definition for EDMA3 Driver

Data Structures

struct | EDMA3_DRV_ChBoundResources
EDMA3 Channel-Bound resources. More...

Modules

Boundary Values
Object Maintenance

Defines

#define | EDMA3_DRV_OPT_SAM_CLR_MASK (~EDMA3_CCRL_OPT_SAM_MASK)
#define | EDMA3_DRV_OPT_SAM_SET_MASK(mode) (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT)
#define | EDMA3_DRV_OPT_DAM_CLR_MASK (~EDMA3_CCRL_OPT_DAM_MASK)
#define | EDMA3_DRV_OPT_DAM_SET_MASK(mode) (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT)
#define | EDMA3_DRV_OPT_SYNCDIM_CLR_MASK (~EDMA3_CCRL_OPT_SYNCDIM_MASK)
#define | EDMA3_DRV_OPT_SYNCDIM_SET_MASK(synctype) (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT)
#define | EDMA3_DRV_OPT_STATIC_CLR_MASK (~EDMA3_CCRL_OPT_STATIC_MASK)
#define | EDMA3_DRV_OPT_STATIC_SET_MASK(en) (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT)
#define | EDMA3_DRV_OPT_FWID_CLR_MASK (~EDMA3_CCRL_OPT_FWID_MASK)
#define | EDMA3_DRV_OPT_FWID_SET_MASK(width) (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT)
#define | EDMA3_DRV_OPT_TCCMODE_CLR_MASK (~EDMA3_CCRL_OPT_TCCMODE_MASK)
#define | EDMA3_DRV_OPT_TCCMODE_SET_MASK(early) (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT)
#define | EDMA3_DRV_OPT_TCC_CLR_MASK (~EDMA3_CCRL_OPT_TCC_MASK)
#define | EDMA3_DRV_OPT_TCC_SET_MASK(tcc) (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT)
#define | EDMA3_DRV_OPT_TCINTEN_CLR_MASK (~EDMA3_CCRL_OPT_TCINTEN_MASK)
#define | EDMA3_DRV_OPT_TCINTEN_SET_MASK(tcinten) (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT)
#define | EDMA3_DRV_OPT_ITCINTEN_CLR_MASK (~EDMA3_CCRL_OPT_ITCINTEN_MASK)
#define | EDMA3_DRV_OPT_ITCINTEN_SET_MASK(itcinten) (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT)
#define | EDMA3_DRV_OPT_TCCHEN_CLR_MASK (~EDMA3_CCRL_OPT_TCCHEN_MASK)
#define | EDMA3_DRV_OPT_TCCHEN_SET_MASK(tcchen) (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT)
#define | EDMA3_DRV_OPT_ITCCHEN_CLR_MASK (~EDMA3_CCRL_OPT_ITCCHEN_MASK)
#define | EDMA3_DRV_OPT_ITCCHEN_SET_MASK(itcchen) (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT)
#define | EDMA3_DRV_OPT_SAM_GET_MASK(mode) ((mode)&1u)
#define | EDMA3_DRV_OPT_DAM_GET_MASK(mode) (((mode)&(1u<<1u))>>1u)
#define | EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype) (((synctype)&(1u<<2u))>>2u)
#define | EDMA3_DRV_OPT_STATIC_GET_MASK(en) (((en)&(1u<<3u))>>3u)
#define | EDMA3_DRV_OPT_FWID_GET_MASK(width) (((width)&(0x7u<<8u))>>8u)
#define | EDMA3_DRV_OPT_TCCMODE_GET_MASK(early) (((early)&(1u<<11u))>>11u)
#define | EDMA3_DRV_OPT_TCC_GET_MASK(tcc) (((tcc)&(0x3fu<<12u))>>12u)
#define | EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten) (((tcinten)&(1u<<20u))>>20u)
#define | EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten) (((itcinten)&(1u<<21u))>>21u)
#define | EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen) (((tcchen)&(1u<<22u))>>22u)
#define | EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen) (((itcchen)&(1u<<23u))>>23u)
#define | EDMA3_DRV_DMAQNUM_CLR_MASK(chNum) (~(0x7u<<(((chNum)%8u)*4u)))
#define | EDMA3_DRV_DMAQNUM_SET_MASK(chNum, queNum) ((0x7u & (queNum)) << (((chNum)%8u)*4u))
#define | EDMA3_DRV_QDMAQNUM_CLR_MASK(chNum) (~(0x7u<<((chNum)*4u)))
#define | EDMA3_DRV_QDMAQNUM_SET_MASK(chNum, queNum) ((0x7u & (queNum)) << ((chNum)*4u))
#define | EDMA3_DRV_QCH_TRWORD_CLR_MASK (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)
#define | EDMA3_DRV_QCH_TRWORD_SET_MASK(paRAMId) (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)
#define | EDMA3_DRV_ACNT_MAX_VAL (0xFFFFu)
#define | EDMA3_DRV_BCNT_MAX_VAL (0xFFFFu)
#define | EDMA3_DRV_CCNT_MAX_VAL (0xFFFFu)
#define | EDMA3_DRV_BCNTRELD_MAX_VAL (0xFFFFu)
#define | EDMA3_DRV_SRCBIDX_MAX_VAL (0x7FFF)
#define | EDMA3_DRV_SRCBIDX_MIN_VAL (-32768)
#define | EDMA3_DRV_SRCCIDX_MAX_VAL (0x7FFF)
#define | EDMA3_DRV_SRCCIDX_MIN_VAL (-32768)
#define | EDMA3_DRV_DSTBIDX_MAX_VAL (0x7FFF)
#define | EDMA3_DRV_DSTBIDX_MIN_VAL (-32768)
#define | EDMA3_DRV_DSTCIDX_MAX_VAL (0x7FFF)
#define | EDMA3_DRV_DSTCIDX_MIN_VAL (-32768)
#define | EDMA3_DRV_QPRIORITY_MAX_VAL (7u)
#define | EDMA3_DRV_QPRIORITY_MIN_VAL (0u)

Enumerations

enum EDMA3_DRV_ChannelType {
EDMA3_DRV_CHANNEL_TYPE_NONE,
EDMA3_DRV_CHANNEL_TYPE_DMA = 1,
EDMA3_DRV_CHANNEL_TYPE_QDMA = 2,
EDMA3_DRV_CHANNEL_TYPE_LINK = 3
}
EDMA3 Channel Type. More...

Detailed Description

Include EDMA3 Driver header file

Documentation of the Internal Interface of EDMA3 Driver

Define Documentation

#define EDMA3_DRV_ACNT_MAX_VAL (0xFFFFu)

Max value of ACnt

Referenced by EDMA3_DRV_setTransferParams().

#define EDMA3_DRV_BCNT_MAX_VAL (0xFFFFu)

Max value of BCnt

Referenced by EDMA3_DRV_setTransferParams().

#define EDMA3_DRV_BCNTRELD_MAX_VAL (0xFFFFu)

Max value of BCntReld

Referenced by EDMA3_DRV_setTransferParams().

#define EDMA3_DRV_CCNT_MAX_VAL (0xFFFFu)

Max value of CCnt

Referenced by EDMA3_DRV_setTransferParams().

#define EDMA3_DRV_DMAQNUM_CLR_MASK ( chNum ) (~(0x7u<<(((chNum)%8u)*4u)))

DMAQNUM bits Clear

Referenced by EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_DMAQNUM_SET_MASK | ( | chNum,
 |  | queNum | ) | ((0x7u & (queNum)) << (((chNum)%8u)*4u))

DMAQNUM bits Set

Referenced by EDMA3_DRV_mapChToEvtQ(), and EDMA3_DRV_requestChannel().

#define EDMA3_DRV_DSTBIDX_MAX_VAL (0x7FFF)

Max value of DestBIdx

Referenced by EDMA3_DRV_setDestIndex().

#define EDMA3_DRV_DSTBIDX_MIN_VAL (-32768)

Min value of DestBIdx

Referenced by EDMA3_DRV_setDestIndex().

#define EDMA3_DRV_DSTCIDX_MAX_VAL (0x7FFF)

Max value of DestCIdx

Referenced by EDMA3_DRV_setDestIndex().

#define EDMA3_DRV_DSTCIDX_MIN_VAL (-32768)

Min value of DestCIdx

Referenced by EDMA3_DRV_setDestIndex().

#define EDMA3_DRV_OPT_DAM_CLR_MASK (~EDMA3_CCRL_OPT_DAM_MASK)

OPT-DAM bit Clear

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_DAM_GET_MASK ( mode ) (((mode)&(1u<<1u))>>1u)

OPT-DAM bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_DAM_SET_MASK ( mode ) (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT)

OPT-DAM bit Set

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_FWID_CLR_MASK (~EDMA3_CCRL_OPT_FWID_MASK)

OPT-FWID bitfield Clear

Referenced by EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_OPT_FWID_GET_MASK ( width ) (((width)&(0x7u<<8u))>>8u)

OPT-FWID bitfield Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_FWID_SET_MASK ( width ) (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT)

OPT-FWID bitfield Set

Referenced by EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_OPT_ITCCHEN_CLR_MASK (~EDMA3_CCRL_OPT_ITCCHEN_MASK)

OPT-ITCCHEN bit Clear

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_setOptField(), and EDMA3_DRV_unchainChannel().

#define EDMA3_DRV_OPT_ITCCHEN_GET_MASK ( itcchen ) (((itcchen)&(1u<<23u))>>23u)

OPT-ITCCHEN bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_ITCCHEN_SET_MASK ( itcchen ) (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT)

OPT-ITCCHEN bit Set

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_ITCINTEN_CLR_MASK (~EDMA3_CCRL_OPT_ITCINTEN_MASK)

OPT-ITCINTEN bit Clear

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_ITCINTEN_GET_MASK ( itcinten ) (((itcinten)&(1u<<21u))>>21u)

OPT-ITCINTEN bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_ITCINTEN_SET_MASK ( itcinten ) (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT)

OPT-ITCINTEN bit Set

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_SAM_CLR_MASK (~EDMA3_CCRL_OPT_SAM_MASK)

Parameter RAM Set field OPT bit-field defines OPT-SAM bit Clear

Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_OPT_SAM_GET_MASK ( mode ) ((mode)&1u)

OPT-SAM bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_SAM_SET_MASK ( mode ) (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT)

OPT-SAM bit Set

Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_OPT_STATIC_CLR_MASK (~EDMA3_CCRL_OPT_STATIC_MASK)

OPT-STATIC bit Clear

Referenced by EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_STATIC_GET_MASK ( en ) (((en)&(1u<<3u))>>3u)

OPT-STATIC bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_STATIC_SET_MASK ( en ) (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT)

OPT-STATIC bit Set

Referenced by EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_SYNCDIM_CLR_MASK (~EDMA3_CCRL_OPT_SYNCDIM_MASK)

OPT-SYNCDIM bit Clear

Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setTransferParams().

#define EDMA3_DRV_OPT_SYNCDIM_GET_MASK ( synctype ) (((synctype)&(1u<<2u))>>2u)

OPT-SYNCDIM bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_SYNCDIM_SET_MASK ( synctype ) (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT)

OPT-SYNCDIM bit Set

Referenced by EDMA3_DRV_setOptField(), and EDMA3_DRV_setTransferParams().

#define EDMA3_DRV_OPT_TCC_CLR_MASK (~EDMA3_CCRL_OPT_TCC_MASK)

OPT-TCC bitfield Clear

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_linkChannel(), EDMA3_DRV_requestChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_TCC_GET_MASK ( tcc ) (((tcc)&(0x3fu<<12u))>>12u)

OPT-TCC bitfield Get

Referenced by EDMA3_DRV_getOptField(), and EDMA3_DRV_linkChannel().

#define EDMA3_DRV_OPT_TCC_SET_MASK ( tcc ) (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT)

OPT-TCC bitfield Set

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_linkChannel(), EDMA3_DRV_requestChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_TCCHEN_CLR_MASK (~EDMA3_CCRL_OPT_TCCHEN_MASK)

OPT-TCCHEN bit Clear

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_setOptField(), and EDMA3_DRV_unchainChannel().

#define EDMA3_DRV_OPT_TCCHEN_GET_MASK ( tcchen ) (((tcchen)&(1u<<22u))>>22u)

OPT-TCCHEN bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_TCCHEN_SET_MASK ( tcchen ) (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT)

OPT-TCCHEN bit Set

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_TCCMODE_CLR_MASK (~EDMA3_CCRL_OPT_TCCMODE_MASK)

OPT-TCCMODE bit Clear

Referenced by EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_TCCMODE_GET_MASK ( early ) (((early)&(1u<<11u))>>11u)

OPT-TCCMODE bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_TCCMODE_SET_MASK ( early ) (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT)

OPT-TCCMODE bit Set

Referenced by EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_TCINTEN_CLR_MASK (~EDMA3_CCRL_OPT_TCINTEN_MASK)

OPT-TCINTEN bit Clear

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_OPT_TCINTEN_GET_MASK ( tcinten ) (((tcinten)&(1u<<20u))>>20u)

OPT-TCINTEN bit Get

Referenced by EDMA3_DRV_getOptField().

#define EDMA3_DRV_OPT_TCINTEN_SET_MASK ( tcinten ) (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT)

OPT-TCINTEN bit Set

Referenced by EDMA3_DRV_chainChannel(), and EDMA3_DRV_setOptField().

#define EDMA3_DRV_QCH_TRWORD_CLR_MASK (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)

QCHMAP-TrigWord bitfield Clear

Referenced by EDMA3_DRV_setQdmaTrigWord().

#define EDMA3_DRV_QCH_TRWORD_SET_MASK ( paRAMId ) (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)

QCHMAP-TrigWord bitfield Set

Referenced by EDMA3_DRV_setQdmaTrigWord().

#define EDMA3_DRV_QDMAQNUM_CLR_MASK ( chNum ) (~(0x7u<<((chNum)*4u)))

QDMAQNUM bits Clear

Referenced by EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_QDMAQNUM_SET_MASK | ( | chNum,
 |  | queNum | ) | ((0x7u & (queNum)) << ((chNum)*4u))

QDMAQNUM bits Set

Referenced by EDMA3_DRV_mapChToEvtQ(), and EDMA3_DRV_requestChannel().

#define EDMA3_DRV_QPRIORITY_MAX_VAL (7u)

Max value of Queue Priority

Referenced by EDMA3_DRV_setEvtQPriority().

#define EDMA3_DRV_QPRIORITY_MIN_VAL (0u)

Min value of Queue Priority

#define EDMA3_DRV_SRCBIDX_MAX_VAL (0x7FFF)

Max value of SrcBIdx

Referenced by EDMA3_DRV_setSrcIndex().

#define EDMA3_DRV_SRCBIDX_MIN_VAL (-32768)

Min value of SrcBIdx

Referenced by EDMA3_DRV_setSrcIndex().

#define EDMA3_DRV_SRCCIDX_MAX_VAL (0x7FFF)

Max value of SrcCIdx

Referenced by EDMA3_DRV_setSrcIndex().

#define EDMA3_DRV_SRCCIDX_MIN_VAL (-32768)

Min value of SrcCIdx

Referenced by EDMA3_DRV_setSrcIndex().

Enumeration Type Documentation

enum EDMA3_DRV_ChannelType

EDMA3 Channel Type.

Enumerator:
EDMA3_DRV_CHANNEL_TYPE_NONE | Invalid Channel
EDMA3_DRV_CHANNEL_TYPE_DMA | DMA Channel
EDMA3_DRV_CHANNEL_TYPE_QDMA | QDMA Channel
EDMA3_DRV_CHANNEL_TYPE_LINK | LINK Channel


EDMA3 Driver: Boundary Values

Boundary Values
[Internal Interface Definition for EDMA3 Driver]

Defines

#define | EDMA3_DRV_DMA_CH_MAX_VAL (EDMA3_MAX_DMA_CH - 1u)
#define | EDMA3_DRV_LINK_CH_MIN_VAL (EDMA3_DRV_DMA_CH_MAX_VAL + 1u)
#define | EDMA3_DRV_LINK_CH_MAX_VAL (EDMA3_DRV_LINK_CH_MIN_VAL + EDMA3_MAX_PARAM_SETS - 1u)
#define | EDMA3_DRV_QDMA_CH_MIN_VAL (EDMA3_DRV_LINK_CH_MAX_VAL + 1u)
#define | EDMA3_DRV_QDMA_CH_MAX_VAL (EDMA3_DRV_QDMA_CH_MIN_VAL + EDMA3_MAX_QDMA_CH - 1u)
#define | EDMA3_DRV_LOG_CH_MAX_VAL (EDMA3_DRV_QDMA_CH_MAX_VAL)

Detailed Description

Boundary Values for Logical Channel Ranges

Define Documentation

#define EDMA3_DRV_DMA_CH_MAX_VAL (EDMA3_MAX_DMA_CH - 1u)

Max of DMA Channels

Referenced by EDMA3_DRV_clearErrorBits(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_LINK_CH_MAX_VAL (EDMA3_DRV_LINK_CH_MIN_VAL + EDMA3_MAX_PARAM_SETS - 1u)

Max of Link Channels

Referenced by EDMA3_DRV_freeChannel(), and EDMA3_DRV_requestChannel().

#define EDMA3_DRV_LINK_CH_MIN_VAL (EDMA3_DRV_DMA_CH_MAX_VAL + 1u)

Min of Link Channels

Referenced by EDMA3_DRV_freeChannel(), and EDMA3_DRV_requestChannel().

#define EDMA3_DRV_LOG_CH_MAX_VAL (EDMA3_DRV_QDMA_CH_MAX_VAL)

Max of Logical Channels

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_disableLogicalChannel(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), and EDMA3_DRV_unlinkChannel().

#define EDMA3_DRV_QDMA_CH_MAX_VAL (EDMA3_DRV_QDMA_CH_MIN_VAL + EDMA3_MAX_QDMA_CH - 1u)

Max of QDMA Channels

Referenced by EDMA3_DRV_disableLogicalChannel(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setQdmaTrigWord(), and EDMA3_DRV_setSrcParams().

#define EDMA3_DRV_QDMA_CH_MIN_VAL (EDMA3_DRV_LINK_CH_MAX_VAL + 1u)

Min of QDMA Channels

Referenced by EDMA3_DRV_disableLogicalChannel(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setQdmaTrigWord(), and EDMA3_DRV_setSrcParams().


EDMA3 Driver: Object Maintenance

Object Maintenance
[Internal Interface Definition for EDMA3 Driver]

Data Structures

struct | EDMA3_DRV_Object
EDMA3 Driver Object (HW Specific) Maintenance structure. More...
struct | EDMA3_DRV_Instance
EDMA3 Driver Instance Configuration Structure. More...

Enumerations

enum EDMA3_DRV_ObjState {
EDMA3_DRV_DELETED = 0,
EDMA3_DRV_CREATED = 1,
EDMA3_DRV_OPENED = 2,
EDMA3_DRV_CLOSED = 3
}

Detailed Description

Maintenance of the EDMA3 Driver Object

Enumeration Type Documentation

enum EDMA3_DRV_ObjState

To maintain the state of the EDMA3 Driver object

Enumerator:
EDMA3_DRV_DELETED | Object deleted
EDMA3_DRV_CREATED | Obect Created
EDMA3_DRV_OPENED | Object Opened
EDMA3_DRV_CLOSED | Object Closed


EDMA3 Driver: Data Structures

  • Data Structures
  • Data Structure Index
  • Data Fields

Data Structures

Here are the data structures with brief descriptions:
EDMA3_DRV_ChainOptions | Structure to be used to configure interrupt generation and chaining options
EDMA3_DRV_ChBoundResources | EDMA3 Channel-Bound resources
EDMA3_DRV_EvtQuePriority | Event queue priorities setup
EDMA3_DRV_GblConfigParams | Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information
EDMA3_DRV_InitConfig | Used to Initialize the EDMA3 Driver Instance
EDMA3_DRV_Instance | EDMA3 Driver Instance Configuration Structure
EDMA3_DRV_InstanceInitConfig | Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information
EDMA3_DRV_MiscParam | Used to specify the miscellaneous options during EDMA3 Driver Initialization
EDMA3_DRV_Object | EDMA3 Driver Object (HW Specific) Maintenance structure
EDMA3_DRV_ParamentryRegs | EDMA3 PaRAM Set
EDMA3_DRV_PaRAMRegs | EDMA3 Parameter RAM Set in User Configurable format


EDMA3 Driver: EDMA3_DRV_ChainOptions Struct Reference

  • Data Fields

EDMA3_DRV_ChainOptions Struct Reference
[EDMA3 Driver Typical EDMA Transfer Setup]

Structure to be used to configure interrupt generation and chaining options. More...

#include <edma3_drv.h>

Data Fields

EDMA3_DRV_TcchEn tcchEn
EDMA3_DRV_ItcchEn itcchEn
EDMA3_DRV_TcintEn tcintEn
EDMA3_DRV_ItcintEn itcintEn

Detailed Description

Structure to be used to configure interrupt generation and chaining options.

Field Documentation

EDMA3_DRV_ItcchEn EDMA3_DRV_ChainOptions::itcchEn

Intermediate Transfer complete chaining enable

Referenced by EDMA3_DRV_chainChannel().

EDMA3_DRV_ItcintEn EDMA3_DRV_ChainOptions::itcintEn

Intermediate Transfer complete interrupt enable

Referenced by EDMA3_DRV_chainChannel().

EDMA3_DRV_TcchEn EDMA3_DRV_ChainOptions::tcchEn

Transfer complete chaining enable

Referenced by EDMA3_DRV_chainChannel().

EDMA3_DRV_TcintEn EDMA3_DRV_ChainOptions::tcintEn

Transfer complete interrupt enable

Referenced by EDMA3_DRV_chainChannel().

The documentation for this struct was generated from the following file:
  • edma3_drv.h


EDMA3 Driver: EDMA3_DRV_ChBoundResources Struct Reference

EDMA3_DRV_ChBoundResources Struct Reference
[Internal Interface Definition for EDMA3 Driver]

EDMA3 Channel-Bound resources. More...

#include <edma3.h>

Data Fields

int | paRAMId
unsigned int | tcc
EDMA3_DRV_TrigMode trigMode

Detailed Description

EDMA3 Channel-Bound resources.

Used to maintain information of the EDMA3 resources (specifically Parameter RAM set and TCC) and the mode of triggering transfer (Manual, HW event driven etc) bound to the particular channel within EDMA3_DRV_requestChannel().

Field Documentation

int EDMA3_DRV_ChBoundResources::paRAMId

PaRAM Set number associated with the particular channel

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_create(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), and EDMA3_DRV_unlinkChannel().

unsigned int EDMA3_DRV_ChBoundResources::tcc

TCC associated with the particular channel

Referenced by EDMA3_DRV_create(), EDMA3_DRV_freeChannel(), and EDMA3_DRV_requestChannel().

EDMA3_DRV_TrigMode EDMA3_DRV_ChBoundResources::trigMode

Mode of triggering transfer

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_create(), EDMA3_DRV_enableTransfer(), and EDMA3_DRV_requestChannel().

The documentation for this struct was generated from the following file:
  • edma3.h


EDMA3 Driver: EDMA3_DRV_EvtQuePriority Struct Reference

EDMA3_DRV_EvtQuePriority Struct Reference
[EDMA3 Driver Optional Setup for EDMA]

Event queue priorities setup. More...

#include <edma3_drv.h>

Data Fields

unsigned int evtQPri [EDMA3_MAX_EVT_QUE]
Event Queue Priorities.

Detailed Description

Event queue priorities setup.

It allows to change the priority of the individual queues and the priority of the transfer request (TR) associated with the events queued in the queue.

The documentation for this struct was generated from the following file:
  • edma3_drv.h


EDMA3 Driver: EDMA3_DRV_GblConfigParams Struct Reference

EDMA3_DRV_GblConfigParams Struct Reference
[EDMA3 Driver Interface Definition]

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information. More...

#include <edma3_drv.h>

Data Fields

unsigned int | numDmaChannels
unsigned int | numQdmaChannels
unsigned int | numTccs
unsigned int | numPaRAMSets
unsigned int | numEvtQueue
unsigned int | numTcs
unsigned int | numRegions
unsigned short | dmaChPaRAMMapExists
Channel mapping existence.
unsigned short | memProtectionExists
void * | globalRegs
void * | tcRegs [EDMA3_MAX_TC]
unsigned int | xferCompleteInt
unsigned int | ccError
unsigned int | tcError [EDMA3_MAX_TC]
unsigned int | evtQPri [EDMA3_MAX_EVT_QUE]
EDMA3 TC priority setting.
unsigned int | evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE]
Event Queues Watermark Levels.
unsigned int | tcDefaultBurstSize [EDMA3_MAX_TC]
Default Burst Size (DBS) of TCs.
unsigned int | dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH]
Mapping from DMA channels to PaRAM Sets.
unsigned int | dmaChannelTccMap [EDMA3_MAX_DMA_CH]
Mapping from DMA channels to TCCs.
unsigned int | dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS]
Mapping from DMA channels to Hardware Events.

Detailed Description

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.

This configuration structure is used to specify the EDMA3 Driver global settings, specific to the SoC. For e.g. number of DMA/QDMA channels, number of PaRAM sets, TCCs, event queues, transfer controllers, base addresses of CC global registers and TC registers, interrupt number for EDMA3 transfer completion, CC error, event queues' priority, watermark threshold level etc. This configuration information is SoC specific and could be provided by the user at run-time while creating the EDMA3 Driver Object, using API EDMA3_DRV_create. In case user doesn't provide it, this information could be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in case it is available.

Field Documentation

unsigned int EDMA3_DRV_GblConfigParams::ccError

EDMA3 CC error interrupt line (could be different for ARM and DSP)

unsigned int EDMA3_DRV_GblConfigParams::dmaChannelHwEvtMap[EDMA3_MAX_DMA_CHAN_DWRDS]

Mapping from DMA channels to Hardware Events.

Each bit in this array corresponds to one DMA channel and tells whether this DMA channel is tied to any peripheral. That is whether any peripheral can send the synch event on this DMA channel or not. 1 means the channel is tied to some peripheral; 0 means it is not. DMA channels which are tied to some peripheral are RESERVED for that peripheral only. They are not allocated when user asks for 'ANY' DMA channel. All channels need not be mapped, some can be free also.

Referenced by EDMA3_DRV_disableLogicalChannel(), EDMA3_DRV_disableTransfer(), and EDMA3_DRV_enableTransfer().

unsigned int EDMA3_DRV_GblConfigParams::dmaChannelPaRAMMap[EDMA3_MAX_DMA_CH]

Mapping from DMA channels to PaRAM Sets.

If channel mapping exists (DCHMAP registers are present), this array stores the respective PaRAM Set for each DMA channel. User can initialize each array member with a specific PaRAM Set or with EDMA3_DRV_CH_NO_PARAM_MAP. If channel mapping doesn't exist, it is of no use as the EDMA3 RM automatically uses the right PaRAM Set for that DMA channel. Useful only if mapping exists, otherwise of no use.

Referenced by EDMA3_DRV_requestChannel().

unsigned int EDMA3_DRV_GblConfigParams::dmaChannelTccMap[EDMA3_MAX_DMA_CH]

Mapping from DMA channels to TCCs.

This array stores the respective TCC (interrupt channel) for each DMA channel. User can initialize each array member with a specific TCC or with EDMA3_DRV_CH_NO_TCC_MAP. This specific TCC code will be returned when the transfer is completed on the mapped DMA channel.

Referenced by EDMA3_DRV_requestChannel().

unsigned short EDMA3_DRV_GblConfigParams::dmaChPaRAMMapExists

Channel mapping existence.

A value of 0 (No channel mapping) implies that there is fixed association between a DMA channel and a PaRAM Set or, in other words, DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP registers) for transfers to happen.

A value of 1 implies the presence of DCHMAP registers for the DMA channels and hence the flexibility of associating any DMA channel to any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA channel (like QDMA Channels).

Referenced by EDMA3_DRV_requestChannel().

unsigned int EDMA3_DRV_GblConfigParams::evtQPri[EDMA3_MAX_EVT_QUE]

EDMA3 TC priority setting.

User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Controllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc)

unsigned int EDMA3_DRV_GblConfigParams::evtQueueWaterMarkLvl[EDMA3_MAX_EVT_QUE]

Event Queues Watermark Levels.

To Configure the Threshold level of number of events that can be queued up in the Event queues. EDMA3CC error register (CCERR) will indicate whether or not at any instant of time the number of events queued up in any of the event queues exceeds or equals the threshold/watermark value that is set in the queue watermark threshold register (QWMTHRA).

void* EDMA3_DRV_GblConfigParams::globalRegs

Base address of EDMA3 CC memory mapped registers.

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_clearErrorBits(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_getCCRegister(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_open(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setCCRegister(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), and EDMA3_DRV_waitAndClearTcc().

unsigned short EDMA3_DRV_GblConfigParams::memProtectionExists

Existence of memory protection feature

unsigned int EDMA3_DRV_GblConfigParams::numDmaChannels

Number of DMA Channels supported by the underlying EDMA3 Controller.

Referenced by EDMA3_DRV_requestChannel().

unsigned int EDMA3_DRV_GblConfigParams::numEvtQueue

Number of Event Queues in the underlying EDMA3 Controller

Referenced by EDMA3_DRV_clearErrorBits(), EDMA3_DRV_mapChToEvtQ(), and EDMA3_DRV_requestChannel().

unsigned int EDMA3_DRV_GblConfigParams::numPaRAMSets

Number of PaRAM Sets supported by the underlying EDMA3 Controller

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), and EDMA3_DRV_unlinkChannel().

unsigned int EDMA3_DRV_GblConfigParams::numQdmaChannels

Number of QDMA Channels supported by the underlying EDMA3 Controller

unsigned int EDMA3_DRV_GblConfigParams::numRegions

Number of Regions in the underlying EDMA3 Controller

Referenced by EDMA3_DRV_create(), EDMA3_DRV_getInstHandle(), and EDMA3_DRV_open().

unsigned int EDMA3_DRV_GblConfigParams::numTccs

Number of Interrupt Channels supported by the underlying EDMA3 Controller

Referenced by EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_freeChannel(), and EDMA3_DRV_waitAndClearTcc().

unsigned int EDMA3_DRV_GblConfigParams::numTcs

Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller

unsigned int EDMA3_DRV_GblConfigParams::tcDefaultBurstSize[EDMA3_MAX_TC]

Default Burst Size (DBS) of TCs.

An optimally-sized command is defined by the transfer controller default burst size (DBS). Different TCs can have different DBS values. It is defined in Bytes.

Referenced by EDMA3_DRV_setDestParams(), and EDMA3_DRV_setSrcParams().

unsigned int EDMA3_DRV_GblConfigParams::tcError[EDMA3_MAX_TC]

EDMA3 TCs error interrupt line (could be different for ARM and DSP)

void* EDMA3_DRV_GblConfigParams::tcRegs[EDMA3_MAX_TC]

Base address of EDMA3 TCs memory mapped registers.

unsigned int EDMA3_DRV_GblConfigParams::xferCompleteInt

EDMA3 transfer completion interrupt line (could be different for ARM and DSP)

The documentation for this struct was generated from the following file:
  • edma3_drv.h


EDMA3 Driver: EDMA3_DRV_InitConfig Struct Reference

EDMA3_DRV_InitConfig Struct Reference
[EDMA3 Driver Interface Definition]

Used to Initialize the EDMA3 Driver Instance. More...

#include <edma3_drv.h>

Data Fields

EDMA3_RM_RegionId | regionId
unsigned short | isMaster
EDMA3_DRV_InstanceInitConfig * drvInstInitConfig
void * | drvSemHandle
EDMA3_RM_GblErrCallback | gblerrCb
void * | gblerrData

Detailed Description

Used to Initialize the EDMA3 Driver Instance.

This configuration structure is used to initialize the EDMA3 DRV Instance. This configuration information is passed while opening the DRV instance.

Field Documentation

EDMA3_DRV_InstanceInitConfig* EDMA3_DRV_InitConfig::drvInstInitConfig

EDMA3 resources related shadow region specific information. Which all EDMA3 resources are owned and reserved by this particular instance are told in this configuration structure. User can also pass this structure as NULL. In that case, default static configuration would be taken from the platform specific configuration files (part of the Resource Manager), if available.

Referenced by EDMA3_DRV_open().

void* EDMA3_DRV_InitConfig::drvSemHandle

EDMA3 Driver Instance specific semaphore handle. Used to share resources (DMA/QDMA channels, PaRAM Sets, TCCs etc) among different users.

Referenced by EDMA3_DRV_open().

EDMA3_RM_GblErrCallback EDMA3_DRV_InitConfig::gblerrCb

Instance wide global callback function to catch non-channel specific errors from the Channel controller. for eg, TCC error, queue threshold exceed error etc.

Referenced by EDMA3_DRV_open().

void* EDMA3_DRV_InitConfig::gblerrData

Application data to be passed back to the global error callback function

Referenced by EDMA3_DRV_open().

unsigned short EDMA3_DRV_InitConfig::isMaster

It tells whether the EDMA3 DRV instance is Master or not. Only the shadow region associated with this master instance will receive the EDMA3 interrupts (if enabled).

Referenced by EDMA3_DRV_open().

EDMA3_RM_RegionId EDMA3_DRV_InitConfig::regionId

Region Identification

Referenced by EDMA3_DRV_open().

The documentation for this struct was generated from the following file:
  • edma3_drv.h


EDMA3 Driver: EDMA3_DRV_Instance Struct Reference

EDMA3_DRV_Instance Struct Reference
[Object Maintenance]

EDMA3 Driver Instance Configuration Structure. More...

#include <edma3.h>

Data Fields

EDMA3_RM_RegionId | regionId
unsigned short | isMaster
EDMA3_DRV_InstanceInitConfig drvInstInitConfig
void * | drvSemHandle
EDMA3_RM_GblErrCallbackParams | gblerrCbParams
EDMA3_CCRL_ShadowRegs * | shadowRegs
EDMA3_DRV_Object * pDrvObjectHandle
EDMA3_RM_Handle | resMgrInstance

Detailed Description

EDMA3 Driver Instance Configuration Structure.

Used to maintain information of the EDMA3 Driver Instances. One such storage exists for each instance of the EDMA3 Driver. There could be as many Driver Instances as there are shadow regions. Multiple EDMA3 Driver instances on the same shadow region are NOT allowed.

Field Documentation

EDMA3_DRV_InstanceInitConfig EDMA3_DRV_Instance::drvInstInitConfig

EDMA3 Driver Instance (Shadow Region) specific init configuration. If NULL, static values will be taken

Referenced by EDMA3_DRV_close(), and EDMA3_DRV_open().

void* EDMA3_DRV_Instance::drvSemHandle

EDMA3 Driver Instance specific semaphore handle

Referenced by EDMA3_DRV_open(), and EDMA3_DRV_setCCRegister().

EDMA3_RM_GblErrCallbackParams EDMA3_DRV_Instance::gblerrCbParams

Instance wide Global Error callback parameters

Referenced by EDMA3_DRV_open().

unsigned short EDMA3_DRV_Instance::isMaster

Whether EDMA3 driver instance is Master or not. Only the master instance shadow region will receive the EDMA3 interrupts, if enabled.

Referenced by EDMA3_DRV_open().

EDMA3_DRV_Object* EDMA3_DRV_Instance::pDrvObjectHandle

Pointer to the EDMA3 Driver Object, for HW specific / Global Information.

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_clearErrorBits(), EDMA3_DRV_close(), EDMA3_DRV_disableLogicalChannel(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getCCRegister(), EDMA3_DRV_getInstHandle(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_open(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setCCRegister(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), and EDMA3_DRV_waitAndClearTcc().

EDMA3_RM_RegionId EDMA3_DRV_Instance::regionId

Region Identification

Referenced by EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_open(), and EDMA3_DRV_waitAndClearTcc().

EDMA3_RM_Handle EDMA3_DRV_Instance::resMgrInstance

Pointer to the Resource Manager Instance opened by the EDMA3 Driver

Referenced by EDMA3_DRV_close(), EDMA3_DRV_freeChannel(), EDMA3_DRV_Ioctl(), and EDMA3_DRV_requestChannel().

EDMA3_CCRL_ShadowRegs* EDMA3_DRV_Instance::shadowRegs

Pointer to appropriate Shadow Register region of CC Registers

Referenced by EDMA3_DRV_clearErrorBits(), EDMA3_DRV_close(), EDMA3_DRV_disableLogicalChannel(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_open(), and EDMA3_DRV_requestChannel().

The documentation for this struct was generated from the following file:
  • edma3.h


EDMA3 Driver: EDMA3_DRV_InstanceInitConfig Struct Reference

EDMA3_DRV_InstanceInitConfig Struct Reference
[EDMA3 Driver Interface Definition]

Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information. More...

#include <edma3_drv.h>

Data Fields

unsigned int | ownPaRAMSets [EDMA3_MAX_PARAM_DWRDS]
unsigned int | ownDmaChannels [EDMA3_MAX_DMA_CHAN_DWRDS]
unsigned int | ownQdmaChannels [EDMA3_MAX_QDMA_CHAN_DWRDS]
unsigned int | ownTccs [EDMA3_MAX_TCC_DWRDS]
unsigned int | resvdPaRAMSets [EDMA3_MAX_PARAM_DWRDS]
Reserved PaRAM Sets.
unsigned int | resvdDmaChannels [EDMA3_MAX_DMA_CHAN_DWRDS]
Reserved DMA channels.
unsigned int | resvdQdmaChannels [EDMA3_MAX_QDMA_CHAN_DWRDS]
Reserved QDMA channels.
unsigned int | resvdTccs [EDMA3_MAX_TCC_DWRDS]
Reserved TCCs.

Detailed Description

Init-time Region Specific Configuration structure for EDMA3 Driver, to provide region specific Information.

This configuration structure is used to specify which EDMA3 resources are owned and reserved by the EDMA3 Driver instance. This configuration structure is shadow region specific and will be provided by the user at run-time while calling EDMA3_DRV_open ().

Owned resources: ****************

EDMA3 Driver Instances are tied to different shadow regions and hence different masters. Regions could be:

a) ARM, b) DSP, c) IMCOP (Imaging Co-processor) etc.

User can assign each EDMA3 resource to a shadow region using this structure. In this way, user specifies which resources are owned by the specific EDMA3 DRV Instance. This assignment should also ensure that the same resource is not assigned to more than one shadow regions (unless desired in that way). Any assignment not following the above mentioned approach may have catastrophic consequences.

Reserved resources: *******************

During EDMA3 DRV initialization, user can reserve some of the EDMA3 resources for future use, by specifying which resources to reserve in the configuration data structure. These (critical) resources are reserved in advance so that they should not be allocated to someone else and thus could be used in future for some specific purpose.

User can request different EDMA3 resources using two methods: a) By passing the resource type and the actual resource id, b) By passing the resource type and ANY as resource id

For e.g. to request DMA channel 31, user will pass 31 as the resource id. But to request ANY available DMA channel (mainly used for memory-to-memory data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the resource id.

During initialization, user may have reserved some of the DMA channels for some specific purpose (mainly for peripherals using EDMA). These reserved DMA channels then will not be returned when user requests ANY as the resource id.

Same logic applies for QDMA channels and TCCs.

For PaRAM Set, there is one difference. If the DMA channels are one-to-one tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set for a particular DMA channel), EDMA3 Driver automatically reserves all those PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would not be returned when user requests for ANY PaRAM Set (specifically for linking purpose). This is done in order to avoid allocating the PaRAM Set, tied to a particular DMA channel, for linking purpose. If this constraint is not there, that DMA channel thus could not be used at all, because of the unavailability of the desired PaRAM Set.

Field Documentation

unsigned int EDMA3_DRV_InstanceInitConfig::ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]

DMA Channels owned by the EDMA3 Driver Instance.

unsigned int EDMA3_DRV_InstanceInitConfig::ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS]

PaRAM Sets owned by the EDMA3 Driver Instance.

unsigned int EDMA3_DRV_InstanceInitConfig::ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]

QDMA Channels owned by the EDMA3 Driver Instance.

unsigned int EDMA3_DRV_InstanceInitConfig::ownTccs[EDMA3_MAX_TCC_DWRDS]

TCCs owned by the EDMA3 Driver Instance.

unsigned int EDMA3_DRV_InstanceInitConfig::resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS]

Reserved DMA channels.

DMA channels reserved during initialization for future use. These will not be given when user requests for ANY available DMA channel using 'EDMA3_DRV_DMA_CHANNEL_ANY' as channel id.

unsigned int EDMA3_DRV_InstanceInitConfig::resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS]

Reserved PaRAM Sets.

PaRAM Sets reserved during initialization for future use. These will not be given when user requests for ANY available PaRAM Set for linking using 'EDMA3_DRV_LINK_CHANNEL' as channel id.

unsigned int EDMA3_DRV_InstanceInitConfig::resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS]

Reserved QDMA channels.

QDMA channels reserved during initialization for future use. These will not be given when user requests for ANY available QDMA channel using 'EDMA3_DRV_QDMA_CHANNEL_ANY' as channel id.

unsigned int EDMA3_DRV_InstanceInitConfig::resvdTccs[EDMA3_MAX_TCC_DWRDS]

Reserved TCCs.

TCCs reserved during initialization for future use. These will not be given when user requests for ANY available TCC using 'EDMA3_DRV_TCC_ANY' as resource id.

The documentation for this struct was generated from the following file:
  • edma3_drv.h


EDMA3 Driver: EDMA3_DRV_MiscParam Struct Reference

EDMA3_DRV_MiscParam Struct Reference
[EDMA3 Driver Interface Definition]

Used to specify the miscellaneous options during EDMA3 Driver Initialization. More...

#include <edma3_drv.h>

Data Fields

unsigned short | isSlave
unsigned short | param

Detailed Description

Used to specify the miscellaneous options during EDMA3 Driver Initialization.

This configuration structure is used to specify some misc options while creating the Driver object. New options may also be added into this structure in future.

Field Documentation

unsigned short EDMA3_DRV_MiscParam::isSlave

In a multi-master system (for e.g. ARM + DSP), this option is used to distinguish between Master and Slave. Only the Master is allowed to program the global EDMA3 registers (like Queue priority, Queue water- mark level, error registers etc).

unsigned short EDMA3_DRV_MiscParam::param

For future use

The documentation for this struct was generated from the following file:
  • edma3_drv.h


EDMA3 Driver: EDMA3_DRV_Object Struct Reference

EDMA3_DRV_Object Struct Reference
[Object Maintenance]

EDMA3 Driver Object (HW Specific) Maintenance structure. More...

#include <edma3.h>

Data Fields

unsigned int | phyCtrllerInstId
EDMA3_DRV_ObjState state
unsigned int | numOpens
EDMA3_DRV_GblConfigParams gblCfgParams
Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.

Detailed Description

EDMA3 Driver Object (HW Specific) Maintenance structure.

Used to maintain information of the EDMA3 HW configuration thoughout the lifetime of the EDMA3 Driver Object, one for each EDMA3 hardware instance.

Field Documentation

EDMA3_DRV_GblConfigParams EDMA3_DRV_Object::gblCfgParams

Init-time Configuration structure for EDMA3 controller, to provide Global SoC specific Information.

This configuration info can be provided by the user at run-time, while calling EDMA3_DRV_create(). If not provided at run-time, this info will be taken from the config file edma3Cfg.c.

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_checkAndClearTcc(), EDMA3_DRV_clearErrorBits(), EDMA3_DRV_create(), EDMA3_DRV_disableLogicalChannel(), EDMA3_DRV_disableTransfer(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getCCRegister(), EDMA3_DRV_getInstHandle(), EDMA3_DRV_getMapChToEvtQ(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_open(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setCCRegister(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setQdmaTrigWord(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), EDMA3_DRV_unlinkChannel(), and EDMA3_DRV_waitAndClearTcc().

unsigned int EDMA3_DRV_Object::numOpens

Number of EDMA3 Driver instances

Referenced by EDMA3_DRV_close(), EDMA3_DRV_create(), and EDMA3_DRV_open().

unsigned int EDMA3_DRV_Object::phyCtrllerInstId

Physical Instance ID of EDMA3 Controller

Referenced by EDMA3_DRV_chainChannel(), EDMA3_DRV_close(), EDMA3_DRV_create(), EDMA3_DRV_enableTransfer(), EDMA3_DRV_freeChannel(), EDMA3_DRV_getOptField(), EDMA3_DRV_getPaRAM(), EDMA3_DRV_getPaRAMEntry(), EDMA3_DRV_getPaRAMField(), EDMA3_DRV_getPaRAMPhyAddr(), EDMA3_DRV_linkChannel(), EDMA3_DRV_mapChToEvtQ(), EDMA3_DRV_requestChannel(), EDMA3_DRV_setDestIndex(), EDMA3_DRV_setDestParams(), EDMA3_DRV_setEvtQPriority(), EDMA3_DRV_setOptField(), EDMA3_DRV_setPaRAM(), EDMA3_DRV_setPaRAMEntry(), EDMA3_DRV_setPaRAMField(), EDMA3_DRV_setSrcIndex(), EDMA3_DRV_setSrcParams(), EDMA3_DRV_setTransferParams(), EDMA3_DRV_unchainChannel(), and EDMA3_DRV_unlinkChannel().

EDMA3_DRV_ObjState EDMA3_DRV_Object::state

State information of the EDMA3 Driver object

Referenced by EDMA3_DRV_close(), EDMA3_DRV_create(), EDMA3_DRV_delete(), and EDMA3_DRV_open().

The documentation for this struct was generated from the following file:
  • edma3.h


EDMA3 Driver: EDMA3_DRV_ParamentryRegs Struct Reference

EDMA3_DRV_ParamentryRegs Struct Reference
[EDMA3 Driver Optional Setup for EDMA]

EDMA3 PaRAM Set. More...

#include <edma3_drv.h>

Data Fields

volatile unsigned int | OPT
volatile unsigned int | SRC
Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
volatile unsigned int | A_B_CNT
volatile unsigned int | DST
Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0.
volatile unsigned int | SRC_DST_BIDX
volatile unsigned int | LINK_BCNTRLD
Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits).
volatile unsigned int | SRC_DST_CIDX
Index between consecutive frames of a Source Block (SRCCIDX) (16 bits) and Index between consecutive frames of a Dest Block (DSTCIDX) (16 bits).
volatile unsigned int | CCNT
Number of Frames in a block (CCNT) (16 bits).

Detailed Description

EDMA3 PaRAM Set.

This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual PaRAM words.

Field Documentation

volatile unsigned int EDMA3_DRV_ParamentryRegs::A_B_CNT

Number of bytes in each Array (ACNT) (16 bits) and Number of Arrays in each Frame (BCNT) (16 bits).

volatile unsigned int EDMA3_DRV_ParamentryRegs::LINK_BCNTRLD

Address for linking (AutoReloading of a PaRAM Set) (16 bits) and Reload value of the numArrInFrame (BCNT) (16 bits).

Link field must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking.

B count reload field is relevant only for A-sync transfers.

volatile unsigned int EDMA3_DRV_ParamentryRegs::OPT

OPT field of PaRAM Set

volatile unsigned int EDMA3_DRV_ParamentryRegs::SRC_DST_BIDX

Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and Index between consec. arrays of a Destination Frame (DSTBIDX) (16 bits).

If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.

If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes

The documentation for this struct was generated from the following file:
  • edma3_drv.h


EDMA3 Driver: EDMA3_DRV_PaRAMRegs Struct Reference

EDMA3_DRV_PaRAMRegs Struct Reference
[EDMA3 Driver Optional Setup for EDMA]

EDMA3 Parameter RAM Set in User Configurable format. More...

#include <edma3_drv.h>

Data Fields

volatile unsigned int | opt
volatile unsigned int | srcAddr
Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
volatile unsigned short | aCnt
Number of bytes in each Array (ACNT).
volatile unsigned short | bCnt
Number of Arrays in each Frame (BCNT).
volatile unsigned int | destAddr
Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address. i.e. 5 LSBs should be 0.
volatile short | srcBIdx
Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.
volatile short | destBIdx
Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes.
volatile unsigned short | linkAddr
Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers.
volatile unsigned short | bCntReload
Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers.
volatile short | srcCIdx
Index between consecutive frames of a Source Block (SRCCIDX).
volatile short | destCIdx
Index between consecutive frames of a Dest Block (DSTCIDX).
volatile unsigned short | cCnt
Number of Frames in a block (CCNT).

Detailed Description

EDMA3 Parameter RAM Set in User Configurable format.

This is a mapping of the EDMA3 PaRAM set provided to the user for ease of modification of the individual fields

Field Documentation

volatile unsigned int EDMA3_DRV_PaRAMRegs::opt

OPT field of PaRAM Set

The documentation for this struct was generated from the following file:
  • edma3_drv.h


EDMA3 Driver: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • g
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- a -

  • A_B_CNT : EDMA3_DRV_ParamentryRegs
  • aCnt : EDMA3_DRV_PaRAMRegs

- b -

  • bCnt : EDMA3_DRV_PaRAMRegs
  • bCntReload : EDMA3_DRV_PaRAMRegs

- c -

  • ccError : EDMA3_DRV_GblConfigParams
  • cCnt : EDMA3_DRV_PaRAMRegs
  • CCNT : EDMA3_DRV_ParamentryRegs

- d -

  • destAddr : EDMA3_DRV_PaRAMRegs
  • destBIdx : EDMA3_DRV_PaRAMRegs
  • destCIdx : EDMA3_DRV_PaRAMRegs
  • dmaChannelHwEvtMap : EDMA3_DRV_GblConfigParams
  • dmaChannelPaRAMMap : EDMA3_DRV_GblConfigParams
  • dmaChannelTccMap : EDMA3_DRV_GblConfigParams
  • dmaChPaRAMMapExists : EDMA3_DRV_GblConfigParams
  • drvInstInitConfig : EDMA3_DRV_Instance , EDMA3_DRV_InitConfig
  • drvSemHandle : EDMA3_DRV_InitConfig , EDMA3_DRV_Instance
  • DST : EDMA3_DRV_ParamentryRegs

- e -

  • evtQPri : EDMA3_DRV_GblConfigParams , EDMA3_DRV_EvtQuePriority
  • evtQueueWaterMarkLvl : EDMA3_DRV_GblConfigParams

- g -

  • gblCfgParams : EDMA3_DRV_Object
  • gblerrCb : EDMA3_DRV_InitConfig
  • gblerrCbParams : EDMA3_DRV_Instance
  • gblerrData : EDMA3_DRV_InitConfig
  • globalRegs : EDMA3_DRV_GblConfigParams

- i -

  • isMaster : EDMA3_DRV_InitConfig , EDMA3_DRV_Instance
  • isSlave : EDMA3_DRV_MiscParam
  • itcchEn : EDMA3_DRV_ChainOptions
  • itcintEn : EDMA3_DRV_ChainOptions

- l -

  • LINK_BCNTRLD : EDMA3_DRV_ParamentryRegs
  • linkAddr : EDMA3_DRV_PaRAMRegs

- m -

  • memProtectionExists : EDMA3_DRV_GblConfigParams

- n -

  • numDmaChannels : EDMA3_DRV_GblConfigParams
  • numEvtQueue : EDMA3_DRV_GblConfigParams
  • numOpens : EDMA3_DRV_Object
  • numPaRAMSets : EDMA3_DRV_GblConfigParams
  • numQdmaChannels : EDMA3_DRV_GblConfigParams
  • numRegions : EDMA3_DRV_GblConfigParams
  • numTccs : EDMA3_DRV_GblConfigParams
  • numTcs : EDMA3_DRV_GblConfigParams

- o -

  • OPT : EDMA3_DRV_ParamentryRegs
  • opt : EDMA3_DRV_PaRAMRegs
  • ownDmaChannels : EDMA3_DRV_InstanceInitConfig
  • ownPaRAMSets : EDMA3_DRV_InstanceInitConfig
  • ownQdmaChannels : EDMA3_DRV_InstanceInitConfig
  • ownTccs : EDMA3_DRV_InstanceInitConfig

- p -

  • param : EDMA3_DRV_MiscParam
  • paRAMId : EDMA3_DRV_ChBoundResources
  • pDrvObjectHandle : EDMA3_DRV_Instance
  • phyCtrllerInstId : EDMA3_DRV_Object

- r -

  • regionId : EDMA3_DRV_InitConfig , EDMA3_DRV_Instance
  • resMgrInstance : EDMA3_DRV_Instance
  • resvdDmaChannels : EDMA3_DRV_InstanceInitConfig
  • resvdPaRAMSets : EDMA3_DRV_InstanceInitConfig
  • resvdQdmaChannels : EDMA3_DRV_InstanceInitConfig
  • resvdTccs : EDMA3_DRV_InstanceInitConfig

- s -

  • shadowRegs : EDMA3_DRV_Instance
  • SRC : EDMA3_DRV_ParamentryRegs
  • SRC_DST_BIDX : EDMA3_DRV_ParamentryRegs
  • SRC_DST_CIDX : EDMA3_DRV_ParamentryRegs
  • srcAddr : EDMA3_DRV_PaRAMRegs
  • srcBIdx : EDMA3_DRV_PaRAMRegs
  • srcCIdx : EDMA3_DRV_PaRAMRegs
  • state : EDMA3_DRV_Object

- t -

  • tcc : EDMA3_DRV_ChBoundResources
  • tcchEn : EDMA3_DRV_ChainOptions
  • tcDefaultBurstSize : EDMA3_DRV_GblConfigParams
  • tcError : EDMA3_DRV_GblConfigParams
  • tcintEn : EDMA3_DRV_ChainOptions
  • tcRegs : EDMA3_DRV_GblConfigParams
  • trigMode : EDMA3_DRV_ChBoundResources

- x -

  • xferCompleteInt : EDMA3_DRV_GblConfigParams


EDMA3 Driver: File Index

  • File List

File List

Here is a list of all documented files with brief descriptions:
edma3.h [code]
edma3_drv.h [code]


EDMA3 Driver: Alphabetical List

Data Structure Index

E

E
EDMA3_DRV_EvtQuePriority EDMA3_DRV_Instance EDMA3_DRV_Object
EDMA3_DRV_ChainOptions EDMA3_DRV_GblConfigParams EDMA3_DRV_InstanceInitConfig EDMA3_DRV_ParamentryRegs
EDMA3_DRV_ChBoundResources EDMA3_DRV_InitConfig EDMA3_DRV_MiscParam EDMA3_DRV_PaRAMRegs

E


EDMA3 Driver: edma3.h Source File

  • File List

edma3.h

00001 /*
00002  * edma3.h
00003  *
00004  * EDMA3 Driver Internal header file.
00005  *
00006  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
00007  *
00008  *
00009  *  Redistribution and use in source and binary forms, with or without
00010  *  modification, are permitted provided that the following conditions
00011  *  are met:
00012  *
00013  *    Redistributions of source code must retain the above copyright
00014  *    notice, this list of conditions and the following disclaimer.
00015  *
00016  *    Redistributions in binary form must reproduce the above copyright
00017  *    notice, this list of conditions and the following disclaimer in the
00018  *    documentation and/or other materials provided with the
00019  *    distribution.
00020  *
00021  *    Neither the name of Texas Instruments Incorporated nor the names of
00022  *    its contributors may be used to endorse or promote products derived
00023  *    from this software without specific prior written permission.
00024  *
00025  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
00026  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00027  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
00028  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
00029  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
00030  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00031  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
00032  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
00033  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00034  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00035  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00036  *
00037 */
00038
00039 #ifndef _EDMA3_H_
00040 #define _EDMA3_H_
00041
00042
00044 #include <ti/sdo/edma3/drv/edma3_drv.h>
00045
00046 /* For the EDMA3 CC Register Layer functionality */
00047 #include <ti/sdo/edma3/rm/src/edma3_rl_cc.h>
00048
00049 #ifdef __cplusplus
00050 extern "C" {
00051 #endif
00052
00053
00062 /* Mask defines */
00065 #define EDMA3_DRV_OPT_SAM_CLR_MASK                  (~EDMA3_CCRL_OPT_SAM_MASK)
00066
00067 #define EDMA3_DRV_OPT_SAM_SET_MASK(mode)            (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT)
00068
00070 #define EDMA3_DRV_OPT_DAM_CLR_MASK                  (~EDMA3_CCRL_OPT_DAM_MASK)
00071
00072 #define EDMA3_DRV_OPT_DAM_SET_MASK(mode)            (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT)
00073
00075 #define EDMA3_DRV_OPT_SYNCDIM_CLR_MASK              (~EDMA3_CCRL_OPT_SYNCDIM_MASK)
00076
00077 #define EDMA3_DRV_OPT_SYNCDIM_SET_MASK(synctype)    (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT)
00078
00080 #define EDMA3_DRV_OPT_STATIC_CLR_MASK               (~EDMA3_CCRL_OPT_STATIC_MASK)
00081
00082 #define EDMA3_DRV_OPT_STATIC_SET_MASK(en)           (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT)
00083
00085 #define EDMA3_DRV_OPT_FWID_CLR_MASK                 (~EDMA3_CCRL_OPT_FWID_MASK)
00086
00087 #define EDMA3_DRV_OPT_FWID_SET_MASK(width)          (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT)
00088
00090 #define EDMA3_DRV_OPT_TCCMODE_CLR_MASK              (~EDMA3_CCRL_OPT_TCCMODE_MASK)
00091
00092 #define EDMA3_DRV_OPT_TCCMODE_SET_MASK(early)       (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT)
00093
00095 #define EDMA3_DRV_OPT_TCC_CLR_MASK                  (~EDMA3_CCRL_OPT_TCC_MASK)
00096
00097 #define EDMA3_DRV_OPT_TCC_SET_MASK(tcc)             (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT)
00098
00100 #define EDMA3_DRV_OPT_TCINTEN_CLR_MASK              (~EDMA3_CCRL_OPT_TCINTEN_MASK)
00101
00102 #define EDMA3_DRV_OPT_TCINTEN_SET_MASK(tcinten)     (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT)
00103
00105 #define EDMA3_DRV_OPT_ITCINTEN_CLR_MASK             (~EDMA3_CCRL_OPT_ITCINTEN_MASK)
00106
00107 #define EDMA3_DRV_OPT_ITCINTEN_SET_MASK(itcinten)   (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT)
00108
00110 #define EDMA3_DRV_OPT_TCCHEN_CLR_MASK               (~EDMA3_CCRL_OPT_TCCHEN_MASK)
00111
00112 #define EDMA3_DRV_OPT_TCCHEN_SET_MASK(tcchen)       (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT)
00113
00115 #define EDMA3_DRV_OPT_ITCCHEN_CLR_MASK              (~EDMA3_CCRL_OPT_ITCCHEN_MASK)
00116
00117 #define EDMA3_DRV_OPT_ITCCHEN_SET_MASK(itcchen)     (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT)
00118
00120 #define EDMA3_DRV_OPT_SAM_GET_MASK(mode)            ((mode)&1u)
00121
00122 #define EDMA3_DRV_OPT_DAM_GET_MASK(mode)            (((mode)&(1u<<1u))>>1u)
00123
00124 #define EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype)    (((synctype)&(1u<<2u))>>2u)
00125
00126 #define EDMA3_DRV_OPT_STATIC_GET_MASK(en)           (((en)&(1u<<3u))>>3u)
00127
00128 #define EDMA3_DRV_OPT_FWID_GET_MASK(width)          (((width)&(0x7u<<8u))>>8u)
00129
00130 #define EDMA3_DRV_OPT_TCCMODE_GET_MASK(early)       (((early)&(1u<<11u))>>11u)
00131
00132 #define EDMA3_DRV_OPT_TCC_GET_MASK(tcc)             (((tcc)&(0x3fu<<12u))>>12u)
00133
00134 #define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten)     (((tcinten)&(1u<<20u))>>20u)
00135
00136 #define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten)   (((itcinten)&(1u<<21u))>>21u)
00137
00138 #define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen)       (((tcchen)&(1u<<22u))>>22u)
00139
00140 #define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen)     (((itcchen)&(1u<<23u))>>23u)
00141
00143 #define EDMA3_DRV_DMAQNUM_CLR_MASK(chNum)           (~(0x7u<<(((chNum)%8u)*4u)))
00144
00145 #define EDMA3_DRV_DMAQNUM_SET_MASK(chNum,queNum)    ((0x7u & (queNum)) << (((chNum)%8u)*4u))
00146
00147 #define EDMA3_DRV_QDMAQNUM_CLR_MASK(chNum)          (~(0x7u<<((chNum)*4u)))
00148
00149 #define EDMA3_DRV_QDMAQNUM_SET_MASK(chNum,queNum)   ((0x7u & (queNum)) << ((chNum)*4u))
00150
00151
00152 /* Other Mask defines */
00154 #define EDMA3_DRV_QCH_TRWORD_CLR_MASK               (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)
00155
00156 #define EDMA3_DRV_QCH_TRWORD_SET_MASK(paRAMId)      (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)
00157
00158
00160 #define EDMA3_DRV_ACNT_MAX_VAL              (0xFFFFu)
00161
00162 #define EDMA3_DRV_BCNT_MAX_VAL              (0xFFFFu)
00163
00164 #define EDMA3_DRV_CCNT_MAX_VAL              (0xFFFFu)
00165
00166 #define EDMA3_DRV_BCNTRELD_MAX_VAL          (0xFFFFu)
00167
00168 #define EDMA3_DRV_SRCBIDX_MAX_VAL           (0x7FFF)
00169
00170 #define EDMA3_DRV_SRCBIDX_MIN_VAL           (-32768)
00171
00172 #define EDMA3_DRV_SRCCIDX_MAX_VAL           (0x7FFF)
00173
00174 #define EDMA3_DRV_SRCCIDX_MIN_VAL           (-32768)
00175
00176 #define EDMA3_DRV_DSTBIDX_MAX_VAL           (0x7FFF)
00177
00178 #define EDMA3_DRV_DSTBIDX_MIN_VAL           (-32768)
00179
00180 #define EDMA3_DRV_DSTCIDX_MAX_VAL           (0x7FFF)
00181
00182 #define EDMA3_DRV_DSTCIDX_MIN_VAL           (-32768)
00183
00184 #define EDMA3_DRV_QPRIORITY_MAX_VAL         (7u)
00185
00186 #define EDMA3_DRV_QPRIORITY_MIN_VAL         (0u)
00187
00188
00189
00190
00199 #define EDMA3_DRV_DMA_CH_MAX_VAL        (EDMA3_MAX_DMA_CH - 1u)
00200
00202 #define EDMA3_DRV_LINK_CH_MIN_VAL       (EDMA3_DRV_DMA_CH_MAX_VAL + 1u)
00203
00205 #define EDMA3_DRV_LINK_CH_MAX_VAL       (EDMA3_DRV_LINK_CH_MIN_VAL + EDMA3_MAX_PARAM_SETS - 1u)
00206
00208 #define EDMA3_DRV_QDMA_CH_MIN_VAL       (EDMA3_DRV_LINK_CH_MAX_VAL + 1u)
00209
00211 #define EDMA3_DRV_QDMA_CH_MAX_VAL       (EDMA3_DRV_QDMA_CH_MIN_VAL + EDMA3_MAX_QDMA_CH - 1u)
00212
00214 #define EDMA3_DRV_LOG_CH_MAX_VAL       (EDMA3_DRV_QDMA_CH_MAX_VAL)
00215
00216
00217 /* @} Edma3DrvIntBoundVals */
00218
00219
00228 typedef enum {
00230     EDMA3_DRV_DELETED   = 0,
00232     EDMA3_DRV_CREATED   = 1,
00234     EDMA3_DRV_OPENED    = 2,
00236     EDMA3_DRV_CLOSED    = 3
00237 } EDMA3_DRV_ObjState;
00238
00239
00248 typedef struct
00249     {
00251     unsigned int            phyCtrllerInstId;
00252
00254     EDMA3_DRV_ObjState      state;
00255
00257     unsigned int            numOpens;
00258
00267     EDMA3_DRV_GblConfigParams gblCfgParams;
00268
00269 } EDMA3_DRV_Object;
00270
00271
00281 typedef struct
00282     {
00284     EDMA3_RM_RegionId       regionId;
00285
00291     unsigned short          isMaster;
00292
00298     EDMA3_DRV_InstanceInitConfig    drvInstInitConfig;
00299
00300
00302     void                    *drvSemHandle;
00303
00305     EDMA3_RM_GblErrCallbackParams   gblerrCbParams;
00306
00308     EDMA3_CCRL_ShadowRegs           *shadowRegs;
00309
00314     EDMA3_DRV_Object                *pDrvObjectHandle;
00315
00317     EDMA3_RM_Handle                 resMgrInstance;
00318
00319     }EDMA3_DRV_Instance;
00320
00321
00322 /* @} Edma3DrvIntObjMaint */
00323
00324
00333 typedef struct {
00335     int paRAMId;
00336
00338     unsigned int tcc;
00339
00341     EDMA3_DRV_TrigMode trigMode;
00342
00343 } EDMA3_DRV_ChBoundResources;
00344
00345
00349 typedef enum
00350 {
00352     EDMA3_DRV_CHANNEL_TYPE_NONE,
00353
00355     EDMA3_DRV_CHANNEL_TYPE_DMA      = 1,
00356
00358     EDMA3_DRV_CHANNEL_TYPE_QDMA     = 2,
00359
00361     EDMA3_DRV_CHANNEL_TYPE_LINK     = 3
00362
00363 } EDMA3_DRV_ChannelType;
00364
00365 #ifdef __cplusplus
00366 }
00367 #endif /* extern "C" */
00368
00369 /* @} Edma3DrvInt */
00370 #endif         /* _EDMA3_H_ */
Generated on Tue Jul 7 19:18:47 2009 for EDMA3 Driver by doxygen 1.5.9


EDMA3 Driver: edma3_drv.h Source File

  • File List

edma3_drv.h

00001 /*
00002  * edma3_drv.h
00003  *
00004  * This file contains Application Interface for the EDMA3 Driver. EDMA3 Driver
00005  * uses the EDMA3 Resource Manager internally for resource allocation, interrupt
00006  * handling and EDMA3 registers programming.
00007  *
00008  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
00009  *
00010  *
00011  *  Redistribution and use in source and binary forms, with or without
00012  *  modification, are permitted provided that the following conditions
00013  *  are met:
00014  *
00015  *    Redistributions of source code must retain the above copyright
00016  *    notice, this list of conditions and the following disclaimer.
00017  *
00018  *    Redistributions in binary form must reproduce the above copyright
00019  *    notice, this list of conditions and the following disclaimer in the
00020  *    documentation and/or other materials provided with the
00021  *    distribution.
00022  *
00023  *    Neither the name of Texas Instruments Incorporated nor the names of
00024  *    its contributors may be used to endorse or promote products derived
00025  *    from this software without specific prior written permission.
00026  *
00027  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
00028  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00029  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
00030  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
00031  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
00032  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00033  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
00034  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
00035  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00036  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038  *
00039 */
00040
00041 #ifndef _EDMA3_DRV_H_
00042 #define _EDMA3_DRV_H_
00043
00044
00045 /* Include the Resource Manager header file */
00046 #include <ti/sdo/edma3/rm/edma3_rm.h>
00047
00048 #ifdef __cplusplus
00049 extern "C" {
00050 #endif
00051
00061 /*---------------------------------------------------------------------------*/
00062 /*------------------Usage Guidelines Start-----------------------------------*/
00063 /*---------------------------------------------------------------------------*/
00064
00403 /* @} Edma3DrvUsage */
00404
00405 /*---------------------------------------------------------------------------*/
00406 /*------------------Usage Guidelines End-------------------------------------*/
00407 /*---------------------------------------------------------------------------*/
00408
00409
00418 #define EDMA3_DRV_E_BASE                        (-128)
00419
00424 #define EDMA3_DRV_E_OBJ_NOT_DELETED             (EDMA3_DRV_E_BASE)
00425
00430 #define EDMA3_DRV_E_OBJ_NOT_CLOSED              (EDMA3_DRV_E_BASE-1)
00431
00436 #define EDMA3_DRV_E_OBJ_NOT_OPENED              (EDMA3_DRV_E_BASE-2)
00437
00442 #define EDMA3_DRV_E_RM_CLOSE_FAIL               (EDMA3_DRV_E_BASE-3)
00443
00445 #define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL         (EDMA3_DRV_E_BASE-4)
00446
00448 #define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL        (EDMA3_DRV_E_BASE-5)
00449
00451 #define EDMA3_DRV_E_PARAM_SET_UNAVAIL           (EDMA3_DRV_E_BASE-6)
00452
00454 #define EDMA3_DRV_E_TCC_UNAVAIL                 (EDMA3_DRV_E_BASE-7)
00455
00457 #define EDMA3_DRV_E_TCC_REGISTER_FAIL           (EDMA3_DRV_E_BASE-8)
00458
00460 #define EDMA3_DRV_E_CH_PARAM_BIND_FAIL          (EDMA3_DRV_E_BASE-9)
00461
00466 #define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED         (EDMA3_DRV_E_BASE-10)
00467
00469 #define EDMA3_DRV_E_INVALID_PARAM               (EDMA3_DRV_E_BASE-11)
00470
00472 #define EDMA3_DRV_E_INVALID_STATE                (EDMA3_DRV_E_BASE-12)
00473
00475 #define EDMA3_DRV_E_INST_ALREADY_EXISTS         (EDMA3_DRV_E_BASE-13)
00476
00478 #define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED        (EDMA3_DRV_E_BASE-14)
00479
00481 #define EDMA3_DRV_E_SEMAPHORE                       (EDMA3_DRV_E_BASE-15)
00482
00484 #define EDMA3_DRV_E_INST_NOT_OPENED         (EDMA3_DRV_E_BASE-16)
00485
00486 /* @} Edma3DrvErrorCode */
00487
00488
00498 #define EDMA3_DRV_CH_NO_PARAM_MAP           EDMA3_RM_CH_NO_PARAM_MAP
00499
00509 #define EDMA3_DRV_CH_NO_TCC_MAP             EDMA3_RM_CH_NO_TCC_MAP
00510
00511
00512
00529 typedef struct  {
00531     unsigned int        numDmaChannels;
00532
00534     unsigned int        numQdmaChannels;
00535
00540     unsigned int        numTccs;
00541
00543     unsigned int        numPaRAMSets;
00544
00546     unsigned int        numEvtQueue;
00547
00551     unsigned int        numTcs;
00552
00554     unsigned int        numRegions;
00555
00569     unsigned short      dmaChPaRAMMapExists;
00570
00572     unsigned short      memProtectionExists;
00573
00575     void                *globalRegs;
00576
00578     void                *tcRegs[EDMA3_MAX_TC];
00579
00584     unsigned int        xferCompleteInt;
00585
00587     unsigned int        ccError;
00588
00590     unsigned int        tcError[EDMA3_MAX_TC];
00591
00601     unsigned int        evtQPri [EDMA3_MAX_EVT_QUE];
00602
00613     unsigned int        evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE];
00614
00622     unsigned int        tcDefaultBurstSize[EDMA3_MAX_TC];
00623
00635     unsigned int        dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH];
00636
00646      unsigned int       dmaChannelTccMap [EDMA3_MAX_DMA_CH];
00647
00660     unsigned int        dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];
00661     } EDMA3_DRV_GblConfigParams;
00662
00663
00664
00728 typedef struct
00729 {
00731     unsigned int        ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
00732
00734     unsigned int        ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
00735
00737     unsigned int        ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
00738
00740     unsigned int        ownTccs[EDMA3_MAX_TCC_DWRDS];
00741
00749     unsigned int        resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
00750
00758     unsigned int        resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
00759
00767     unsigned int        resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
00768
00776     unsigned int        resvdTccs[EDMA3_MAX_TCC_DWRDS];
00777 }EDMA3_DRV_InstanceInitConfig;
00778
00779
00780
00787 typedef struct
00788 {
00790     EDMA3_RM_RegionId       regionId;
00791
00797     unsigned short          isMaster;
00798
00807     EDMA3_DRV_InstanceInitConfig    *drvInstInitConfig;
00808
00814     void                    *drvSemHandle;
00815
00821     EDMA3_RM_GblErrCallback gblerrCb;
00822
00827     void                    *gblerrData;
00828 } EDMA3_DRV_InitConfig;
00829
00830
00831
00840 typedef struct {
00847     unsigned short          isSlave;
00848
00850     unsigned short          param;
00851 }EDMA3_DRV_MiscParam;
00852
00853
00886 EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId,
00887                                 const EDMA3_DRV_GblConfigParams *gblCfgParams,
00888                                 const void *miscParam);
00889
00890
00911 EDMA3_DRV_Result EDMA3_DRV_delete (unsigned int phyCtrllerInstId,
00912                                     const void *param);
00913
00914
00915
00952 EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId,
00953                         const EDMA3_DRV_InitConfig *initCfg,
00954                         EDMA3_DRV_Result *errorCode);
00955
00956
00973 EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
00974                                 const void *param);
00975
00976
00977
00986 /* Defines for Logical Channel Values */
00987 /*---------------------------------------------------------------------------*/
00994 #define EDMA3_DRV_DMA_CHANNEL_ANY                   1002u
00995
01002 #define EDMA3_DRV_QDMA_CHANNEL_ANY                  1003u
01003
01011 #define EDMA3_DRV_TCC_ANY                           1004u
01012
01019 #define EDMA3_DRV_LINK_CHANNEL                      1005u
01020 /*---------------------------------------------------------------------------*/
01021
01022
01041 typedef enum
01042 {
01044     EDMA3_DRV_HW_CHANNEL_EVENT_0 = 0,
01046     EDMA3_DRV_HW_CHANNEL_EVENT_1,
01048     EDMA3_DRV_HW_CHANNEL_EVENT_2,
01050     EDMA3_DRV_HW_CHANNEL_EVENT_3,
01052     EDMA3_DRV_HW_CHANNEL_EVENT_4,
01054     EDMA3_DRV_HW_CHANNEL_EVENT_5,
01056     EDMA3_DRV_HW_CHANNEL_EVENT_6,
01058     EDMA3_DRV_HW_CHANNEL_EVENT_7,
01060     EDMA3_DRV_HW_CHANNEL_EVENT_8,
01062     EDMA3_DRV_HW_CHANNEL_EVENT_9,
01064     EDMA3_DRV_HW_CHANNEL_EVENT_10,
01066     EDMA3_DRV_HW_CHANNEL_EVENT_11,
01068     EDMA3_DRV_HW_CHANNEL_EVENT_12,
01070     EDMA3_DRV_HW_CHANNEL_EVENT_13,
01072     EDMA3_DRV_HW_CHANNEL_EVENT_14,
01074     EDMA3_DRV_HW_CHANNEL_EVENT_15,
01076     EDMA3_DRV_HW_CHANNEL_EVENT_16,
01078     EDMA3_DRV_HW_CHANNEL_EVENT_17,
01080     EDMA3_DRV_HW_CHANNEL_EVENT_18,
01082     EDMA3_DRV_HW_CHANNEL_EVENT_19,
01084     EDMA3_DRV_HW_CHANNEL_EVENT_20,
01086     EDMA3_DRV_HW_CHANNEL_EVENT_21,
01088     EDMA3_DRV_HW_CHANNEL_EVENT_22,
01090     EDMA3_DRV_HW_CHANNEL_EVENT_23,
01092     EDMA3_DRV_HW_CHANNEL_EVENT_24,
01094     EDMA3_DRV_HW_CHANNEL_EVENT_25,
01096     EDMA3_DRV_HW_CHANNEL_EVENT_26,
01098     EDMA3_DRV_HW_CHANNEL_EVENT_27,
01100     EDMA3_DRV_HW_CHANNEL_EVENT_28,
01102     EDMA3_DRV_HW_CHANNEL_EVENT_29,
01104     EDMA3_DRV_HW_CHANNEL_EVENT_30,
01106     EDMA3_DRV_HW_CHANNEL_EVENT_31,
01108     EDMA3_DRV_HW_CHANNEL_EVENT_32,
01110     EDMA3_DRV_HW_CHANNEL_EVENT_33,
01112     EDMA3_DRV_HW_CHANNEL_EVENT_34,
01114     EDMA3_DRV_HW_CHANNEL_EVENT_35,
01116     EDMA3_DRV_HW_CHANNEL_EVENT_36,
01118     EDMA3_DRV_HW_CHANNEL_EVENT_37,
01120     EDMA3_DRV_HW_CHANNEL_EVENT_38,
01122     EDMA3_DRV_HW_CHANNEL_EVENT_39,
01124     EDMA3_DRV_HW_CHANNEL_EVENT_40,
01126     EDMA3_DRV_HW_CHANNEL_EVENT_41,
01128     EDMA3_DRV_HW_CHANNEL_EVENT_42,
01130     EDMA3_DRV_HW_CHANNEL_EVENT_43,
01132     EDMA3_DRV_HW_CHANNEL_EVENT_44,
01134     EDMA3_DRV_HW_CHANNEL_EVENT_45,
01136     EDMA3_DRV_HW_CHANNEL_EVENT_46,
01138     EDMA3_DRV_HW_CHANNEL_EVENT_47,
01140     EDMA3_DRV_HW_CHANNEL_EVENT_48,
01142     EDMA3_DRV_HW_CHANNEL_EVENT_49,
01144     EDMA3_DRV_HW_CHANNEL_EVENT_50,
01146     EDMA3_DRV_HW_CHANNEL_EVENT_51,
01148     EDMA3_DRV_HW_CHANNEL_EVENT_52,
01150     EDMA3_DRV_HW_CHANNEL_EVENT_53,
01152     EDMA3_DRV_HW_CHANNEL_EVENT_54,
01154     EDMA3_DRV_HW_CHANNEL_EVENT_55,
01156     EDMA3_DRV_HW_CHANNEL_EVENT_56,
01158     EDMA3_DRV_HW_CHANNEL_EVENT_57,
01160     EDMA3_DRV_HW_CHANNEL_EVENT_58,
01162     EDMA3_DRV_HW_CHANNEL_EVENT_59,
01164     EDMA3_DRV_HW_CHANNEL_EVENT_60,
01166     EDMA3_DRV_HW_CHANNEL_EVENT_61,
01168     EDMA3_DRV_HW_CHANNEL_EVENT_62,
01170     EDMA3_DRV_HW_CHANNEL_EVENT_63
01171 } EDMA3_DRV_HW_CHANNEL_EVENT;
01172
01173
01179 #define EDMA3_DRV_QDMA_CHANNEL_0    (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
01180
01181 #define EDMA3_DRV_QDMA_CHANNEL_1    (EDMA3_DRV_QDMA_CHANNEL_0+1u)
01182
01183 #define EDMA3_DRV_QDMA_CHANNEL_2    (EDMA3_DRV_QDMA_CHANNEL_0+2u)
01184
01185 #define EDMA3_DRV_QDMA_CHANNEL_3    (EDMA3_DRV_QDMA_CHANNEL_0+3u)
01186
01187 #define EDMA3_DRV_QDMA_CHANNEL_4    (EDMA3_DRV_QDMA_CHANNEL_0+4u)
01188
01189 #define EDMA3_DRV_QDMA_CHANNEL_5    (EDMA3_DRV_QDMA_CHANNEL_0+5u)
01190
01191 #define EDMA3_DRV_QDMA_CHANNEL_6    (EDMA3_DRV_QDMA_CHANNEL_0+6u)
01192
01193 #define EDMA3_DRV_QDMA_CHANNEL_7    (EDMA3_DRV_QDMA_CHANNEL_0+7u)
01194
01195
01196
01316 EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
01317                                     unsigned int *pLCh,
01318                                     unsigned int *pTcc,
01319                                     EDMA3_RM_EventQueue evtQueue,
01320                                     EDMA3_RM_TccCallback tccCb,
01321                                     void *cbData);
01322
01323
01352 EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
01353                                                 unsigned int channelId);
01354
01355
01356
01372 EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
01373                                                     unsigned int channelId);
01374
01375
01410 EDMA3_DRV_Result EDMA3_DRV_linkChannel ( EDMA3_DRV_Handle hEdma,
01411                                                 unsigned int lCh1,
01412                                                 unsigned int lCh2);
01413
01414
01415
01431 EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma,
01432                                                     unsigned int lCh);
01433
01434 /* @} Edma3DrvChannelSetup */
01435
01436
01437
01452 typedef enum
01453 {
01458         EDMA3_DRV_OPT_FIELD_SAM = 0,
01459
01464         EDMA3_DRV_OPT_FIELD_DAM = 1,
01465
01470         EDMA3_DRV_OPT_FIELD_SYNCDIM = 2,
01471
01477         EDMA3_DRV_OPT_FIELD_STATIC  = 3,
01478
01483         EDMA3_DRV_OPT_FIELD_FWID = 4,
01484
01491         EDMA3_DRV_OPT_FIELD_TCCMODE = 5,
01492
01500         EDMA3_DRV_OPT_FIELD_TCC = 6,
01501
01506         EDMA3_DRV_OPT_FIELD_TCINTEN = 7,
01507
01512         EDMA3_DRV_OPT_FIELD_ITCINTEN = 8,
01513
01518         EDMA3_DRV_OPT_FIELD_TCCHEN = 9,
01519
01524         EDMA3_DRV_OPT_FIELD_ITCCHEN = 10
01525
01526 } EDMA3_DRV_OptField;
01527
01528
01540 typedef enum
01541 {
01546         EDMA3_DRV_ADDR_MODE_INCR            = 0,
01547
01552         EDMA3_DRV_ADDR_MODE_FIFO            = 1
01553
01554 } EDMA3_DRV_AddrMode;
01555
01556
01557
01584 typedef enum
01585 {
01590         EDMA3_DRV_SYNC_A = 0 ,
01591
01596     EDMA3_DRV_SYNC_AB = 1
01597
01598 } EDMA3_DRV_SyncType;
01599
01600
01601
01606 typedef enum
01607 {
01614     EDMA3_DRV_STATIC_DIS      = 0,
01615
01622     EDMA3_DRV_STATIC_EN       = 1
01623 } EDMA3_DRV_StaticMode;
01624
01625
01634 typedef enum
01635 {
01637         EDMA3_DRV_W8BIT = 0,
01638
01640         EDMA3_DRV_W16BIT = 1,
01641
01643         EDMA3_DRV_W32BIT = 2,
01644
01646         EDMA3_DRV_W64BIT = 3,
01647
01649         EDMA3_DRV_W128BIT = 4,
01650
01652         EDMA3_DRV_W256BIT = 5
01653
01654 } EDMA3_DRV_FifoWidth;
01655
01656
01657
01658
01664 typedef enum
01665 {
01667     EDMA3_DRV_TCCMODE_NORMAL      = 0,
01668
01674     EDMA3_DRV_TCCMODE_EARLY       = 1
01675 } EDMA3_DRV_TccMode;
01676
01677
01681 typedef enum
01682 {
01684     EDMA3_DRV_TCINTEN_DIS      = 0,
01685
01694     EDMA3_DRV_TCINTEN_EN       = 1
01695 } EDMA3_DRV_TcintEn;
01696
01697
01701 typedef enum
01702 {
01704     EDMA3_DRV_ITCINTEN_DIS      = 0,
01705
01715     EDMA3_DRV_ITCINTEN_EN       = 1
01716 } EDMA3_DRV_ItcintEn;
01717
01718
01722 typedef enum
01723 {
01725     EDMA3_DRV_TCCHEN_DIS      = 0,
01726
01734     EDMA3_DRV_TCCHEN_EN       = 1
01735 } EDMA3_DRV_TcchEn;
01736
01737
01741 typedef enum
01742 {
01744     EDMA3_DRV_ITCCHEN_DIS      = 0,
01745
01753     EDMA3_DRV_ITCCHEN_EN       = 1
01754 } EDMA3_DRV_ItcchEn;
01755
01756
01761 typedef struct
01762 {
01764     EDMA3_DRV_TcchEn    tcchEn;
01765
01767     EDMA3_DRV_ItcchEn   itcchEn;
01768
01770     EDMA3_DRV_TcintEn   tcintEn;
01771
01773     EDMA3_DRV_ItcintEn  itcintEn;
01774 } EDMA3_DRV_ChainOptions;
01775
01776
01777
01798 EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
01799                     unsigned int lCh,
01800                     EDMA3_DRV_OptField optField,
01801                     unsigned int newOptFieldVal);
01802
01803
01823 EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
01824                     unsigned int lCh,
01825                     EDMA3_DRV_OptField optField,
01826                     unsigned int *optFieldVal);
01827
01828
01855 EDMA3_DRV_Result EDMA3_DRV_setSrcParams ( EDMA3_DRV_Handle hEdma,
01856                     unsigned int lCh,
01857                     unsigned int srcAddr,
01858                     EDMA3_DRV_AddrMode addrMode,
01859                     EDMA3_DRV_FifoWidth fifoWidth);
01860
01861
01862
01889 EDMA3_DRV_Result EDMA3_DRV_setDestParams ( EDMA3_DRV_Handle hEdma,
01890                     unsigned int lCh,
01891                     unsigned int destAddr,
01892                     EDMA3_DRV_AddrMode addrMode,
01893                     EDMA3_DRV_FifoWidth fifoWidth );
01894
01895
01896
01929 EDMA3_DRV_Result EDMA3_DRV_setSrcIndex ( EDMA3_DRV_Handle hEdma,
01930                     unsigned int lCh,
01931                     int srcBIdx,
01932                     int srcCIdx );
01933
01934
01935
01968 EDMA3_DRV_Result  EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma,
01969                     unsigned int lCh,
01970                     int destBIdx,
01971                     int destCIdx);
01972
01973
02034 EDMA3_DRV_Result EDMA3_DRV_setTransferParams (
02035                         EDMA3_DRV_Handle hEdma,
02036                         unsigned int lCh,
02037                         unsigned int aCnt,
02038                         unsigned int bCnt,
02039                         unsigned int cCnt,
02040                         unsigned int bCntReload,
02041                         EDMA3_DRV_SyncType syncType);
02042
02043
02070 EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
02071                                     unsigned int lCh1,
02072                                     unsigned int lCh2,
02073                                     const EDMA3_DRV_ChainOptions *chainOptions);
02074
02075
02088 EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma,
02089                         unsigned int lCh);
02090
02091
02098 typedef enum
02099 {
02105         EDMA3_DRV_TRIG_MODE_MANUAL = 0,
02106
02115         EDMA3_DRV_TRIG_MODE_QDMA = 1,
02116
02122         EDMA3_DRV_TRIG_MODE_EVENT = 2,
02123
02125         EDMA3_DRV_TRIG_MODE_NONE = 3
02126 } EDMA3_DRV_TrigMode;
02127
02128
02160 EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
02161                         unsigned int lCh,
02162                         EDMA3_DRV_TrigMode trigMode);
02163
02164
02192 EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
02193                         unsigned int lCh,
02194                         EDMA3_DRV_TrigMode trigMode);
02195
02216 EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
02217                         unsigned int lCh,
02218                         EDMA3_DRV_TrigMode trigMode);
02219
02220
02221 /* @} Edma3DrvTransferSetupType */
02222
02223
02224
02239 typedef enum
02240 {
02244     EDMA3_DRV_PARAM_ENTRY_OPT                       = 0,
02245
02249     EDMA3_DRV_PARAM_ENTRY_SRC                       = 1,
02250
02254     EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT                 = 2,
02255
02259     EDMA3_DRV_PARAM_ENTRY_DST                       = 3,
02260
02264     EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX              = 4,
02265
02269     EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD              = 5,
02270
02274     EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX              = 6,
02275
02279     EDMA3_DRV_PARAM_ENTRY_CCNT                      = 7
02280
02281 } EDMA3_DRV_PaRAMEntry;
02282
02283
02289 typedef enum
02290 {
02292     EDMA3_DRV_PARAM_FIELD_OPT           = 0,
02293
02298     EDMA3_DRV_PARAM_FIELD_SRCADDR       = 1,
02299
02303     EDMA3_DRV_PARAM_FIELD_ACNT          = 2,
02304
02308     EDMA3_DRV_PARAM_FIELD_BCNT          = 3,
02309
02314     EDMA3_DRV_PARAM_FIELD_DESTADDR      = 4,
02315
02321     EDMA3_DRV_PARAM_FIELD_SRCBIDX       = 5,
02322
02328     EDMA3_DRV_PARAM_FIELD_DESTBIDX      = 6,
02329
02337     EDMA3_DRV_PARAM_FIELD_LINKADDR      = 7,
02338
02343     EDMA3_DRV_PARAM_FIELD_BCNTRELOAD    = 8,
02344
02348     EDMA3_DRV_PARAM_FIELD_SRCCIDX       = 9,
02349
02353     EDMA3_DRV_PARAM_FIELD_DESTCIDX      = 10,
02354
02358     EDMA3_DRV_PARAM_FIELD_CCNT          = 11
02359
02360 } EDMA3_DRV_PaRAMField;
02361
02362
02363
02370 typedef struct  {
02372     volatile unsigned int OPT;
02373
02378     volatile unsigned int SRC;
02379
02384     volatile unsigned int A_B_CNT;
02385
02391     volatile unsigned int DST;
02392
02403     volatile unsigned int SRC_DST_BIDX;
02404
02414     volatile unsigned int LINK_BCNTRLD;
02415
02421     volatile unsigned int SRC_DST_CIDX;
02422
02426     volatile unsigned int CCNT;
02427
02428 } EDMA3_DRV_ParamentryRegs;
02429
02430
02431
02438 typedef struct  {
02440         volatile unsigned int opt;
02441
02446         volatile unsigned int srcAddr;
02447
02451         volatile unsigned short aCnt;
02452
02456         volatile unsigned short bCnt;
02457
02463         volatile unsigned int destAddr;
02464
02470         volatile short  srcBIdx;
02471
02477         volatile short  destBIdx;
02478
02486         volatile unsigned short linkAddr;
02487
02492         volatile unsigned short bCntReload;
02493
02497         volatile short  srcCIdx;
02498
02502         volatile short  destCIdx;
02503
02507         volatile unsigned short cCnt;
02508
02509 } EDMA3_DRV_PaRAMRegs;
02510
02511
02519 typedef struct
02520 {
02524     unsigned int evtQPri[EDMA3_MAX_EVT_QUE];
02525 }EDMA3_DRV_EvtQuePriority;
02526
02527
02547 EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma,
02548                     unsigned int lCh,
02549                     EDMA3_RM_QdmaTrigWord trigWord);
02550
02551
02573 EDMA3_DRV_Result EDMA3_DRV_setPaRAM ( EDMA3_DRV_Handle hEdma,
02574                         unsigned int lCh,
02575                         const EDMA3_DRV_PaRAMRegs *newPaRAM);
02576
02577
02591 EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma,
02592                     unsigned int lCh,
02593                     EDMA3_DRV_PaRAMRegs *currPaRAM);
02594
02595
02618 EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma,
02619                     unsigned int lCh,
02620                     EDMA3_DRV_PaRAMEntry paRAMEntry,
02621                     unsigned int newPaRAMEntryVal);
02622
02623
02639 EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma,
02640                     unsigned int lCh,
02641                     EDMA3_DRV_PaRAMEntry paRAMEntry,
02642                     unsigned int *paRAMEntryVal);
02643
02644
02668 EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma,
02669                     unsigned int lCh,
02670                     EDMA3_DRV_PaRAMField paRAMField,
02671                     unsigned int newPaRAMFieldVal);
02672
02673
02689 EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma,
02690                     unsigned int lCh,
02691                     EDMA3_DRV_PaRAMField paRAMField,
02692                     unsigned int *currPaRAMFieldVal);
02693
02694
02711 EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma,
02712                     const EDMA3_DRV_EvtQuePriority *evtQPriObj);
02713
02714
02733 EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma,
02734                     unsigned int channelId,
02735                     EDMA3_RM_EventQueue eventQ);
02736
02737
02751 EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma,
02752                     unsigned int channelId,
02753                     unsigned int *mappedEvtQ);
02754
02755
02756
02775 EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
02776                     unsigned int regOffset,
02777                     unsigned int newRegValue);
02778
02779
02791 EDMA3_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma,
02792                     unsigned int regOffset,
02793                     unsigned int *regValue);
02794
02795
02796
02815 EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
02816                     unsigned int tccNo);
02817
02818
02819
02820
02842 EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,
02843                     unsigned int tccNo,
02844                     unsigned short *tccStatus);
02845
02846
02847
02871 EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma,
02872                     unsigned int lCh,
02873                     unsigned int *paramPhyAddr);
02874
02875
02879 typedef enum
02880 {
02881     /* Min IOCTL */
02882     EDMA3_DRV_IOCTL_MIN_IOCTL = 0,
02883
02904     EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION,
02905
02918     EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION,
02919
02920     /* Max IOCTLs */
02921     EDMA3_DRV_IOCTL_MAX_IOCTL
02922 } EDMA3_DRV_IoctlCmd;
02923
02924
02941 EDMA3_DRV_Result EDMA3_DRV_Ioctl(
02942                       EDMA3_DRV_Handle       hEdma,
02943                       EDMA3_DRV_IoctlCmd     cmd,
02944                       void                  *cmdArg,
02945                       void                  *param
02946                      );
02947
02948
02986 EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(unsigned int phyCtrllerInstId,
02987                                 EDMA3_RM_RegionId regionId,
02988                                 EDMA3_DRV_Result *errorCode);
02989
02990
02991 /* @} Edma3DrvTransferSetupOpt */
02992
02993
02994 /* @} Edma3DrvMain */
02995
02996 #ifdef __cplusplus
02997 }
02998 #endif /* extern "C" */
02999
03000 #endif         /* _EDMA3_DRV_H_ */
Generated on Tue Jul 7 19:18:47 2009 for EDMA3 Driver by doxygen 1.5.9


EDMA3 Driver: Data Fields - Variables

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • g
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • x

- a -

  • A_B_CNT : EDMA3_DRV_ParamentryRegs
  • aCnt : EDMA3_DRV_PaRAMRegs

- b -

  • bCnt : EDMA3_DRV_PaRAMRegs
  • bCntReload : EDMA3_DRV_PaRAMRegs

- c -

  • ccError : EDMA3_DRV_GblConfigParams
  • cCnt : EDMA3_DRV_PaRAMRegs
  • CCNT : EDMA3_DRV_ParamentryRegs

- d -

  • destAddr : EDMA3_DRV_PaRAMRegs
  • destBIdx : EDMA3_DRV_PaRAMRegs
  • destCIdx : EDMA3_DRV_PaRAMRegs
  • dmaChannelHwEvtMap : EDMA3_DRV_GblConfigParams
  • dmaChannelPaRAMMap : EDMA3_DRV_GblConfigParams
  • dmaChannelTccMap : EDMA3_DRV_GblConfigParams
  • dmaChPaRAMMapExists : EDMA3_DRV_GblConfigParams
  • drvInstInitConfig : EDMA3_DRV_Instance , EDMA3_DRV_InitConfig
  • drvSemHandle : EDMA3_DRV_InitConfig , EDMA3_DRV_Instance
  • DST : EDMA3_DRV_ParamentryRegs

- e -

  • evtQPri : EDMA3_DRV_GblConfigParams , EDMA3_DRV_EvtQuePriority
  • evtQueueWaterMarkLvl : EDMA3_DRV_GblConfigParams

- g -

  • gblCfgParams : EDMA3_DRV_Object
  • gblerrCb : EDMA3_DRV_InitConfig
  • gblerrCbParams : EDMA3_DRV_Instance
  • gblerrData : EDMA3_DRV_InitConfig
  • globalRegs : EDMA3_DRV_GblConfigParams

- i -

  • isMaster : EDMA3_DRV_InitConfig , EDMA3_DRV_Instance
  • isSlave : EDMA3_DRV_MiscParam
  • itcchEn : EDMA3_DRV_ChainOptions
  • itcintEn : EDMA3_DRV_ChainOptions

- l -

  • LINK_BCNTRLD : EDMA3_DRV_ParamentryRegs
  • linkAddr : EDMA3_DRV_PaRAMRegs

- m -

  • memProtectionExists : EDMA3_DRV_GblConfigParams

- n -

  • numDmaChannels : EDMA3_DRV_GblConfigParams
  • numEvtQueue : EDMA3_DRV_GblConfigParams
  • numOpens : EDMA3_DRV_Object
  • numPaRAMSets : EDMA3_DRV_GblConfigParams
  • numQdmaChannels : EDMA3_DRV_GblConfigParams
  • numRegions : EDMA3_DRV_GblConfigParams
  • numTccs : EDMA3_DRV_GblConfigParams
  • numTcs : EDMA3_DRV_GblConfigParams

- o -

  • OPT : EDMA3_DRV_ParamentryRegs
  • opt : EDMA3_DRV_PaRAMRegs
  • ownDmaChannels : EDMA3_DRV_InstanceInitConfig
  • ownPaRAMSets : EDMA3_DRV_InstanceInitConfig
  • ownQdmaChannels : EDMA3_DRV_InstanceInitConfig
  • ownTccs : EDMA3_DRV_InstanceInitConfig

- p -

  • param : EDMA3_DRV_MiscParam
  • paRAMId : EDMA3_DRV_ChBoundResources
  • pDrvObjectHandle : EDMA3_DRV_Instance
  • phyCtrllerInstId : EDMA3_DRV_Object

- r -

  • regionId : EDMA3_DRV_InitConfig , EDMA3_DRV_Instance
  • resMgrInstance : EDMA3_DRV_Instance
  • resvdDmaChannels : EDMA3_DRV_InstanceInitConfig
  • resvdPaRAMSets : EDMA3_DRV_InstanceInitConfig
  • resvdQdmaChannels : EDMA3_DRV_InstanceInitConfig
  • resvdTccs : EDMA3_DRV_InstanceInitConfig

- s -

  • shadowRegs : EDMA3_DRV_Instance
  • SRC : EDMA3_DRV_ParamentryRegs
  • SRC_DST_BIDX : EDMA3_DRV_ParamentryRegs
  • SRC_DST_CIDX : EDMA3_DRV_ParamentryRegs
  • srcAddr : EDMA3_DRV_PaRAMRegs
  • srcBIdx : EDMA3_DRV_PaRAMRegs
  • srcCIdx : EDMA3_DRV_PaRAMRegs
  • state : EDMA3_DRV_Object

- t -

  • tcc : EDMA3_DRV_ChBoundResources
  • tcchEn : EDMA3_DRV_ChainOptions
  • tcDefaultBurstSize : EDMA3_DRV_GblConfigParams
  • tcError : EDMA3_DRV_GblConfigParams
  • tcintEn : EDMA3_DRV_ChainOptions
  • tcRegs : EDMA3_DRV_GblConfigParams
  • trigMode : EDMA3_DRV_ChBoundResources

- x -

  • xferCompleteInt : EDMA3_DRV_GblConfigParams


EDMA3 Driver: Main Page

EDMA3 Driver Documentation

Generated on Tue Jul 7 19:18:47 2009 for EDMA3 Driver by doxygen 1.5.9