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32
33 34 35
36 package ti.uia.family.dm;
37
38 import xdc.runtime.Types;
39
40 /*!
41 * ======== TimestampDM8168Timer.xdc ========
42 * Implementation of `{@link ITimestampProvider}` using DM General purpose
43 * 32b timer. NOTE: for ARM devices, address values should be virtual
44 * addresses as seen by the CPU.
45 */
46 @ModuleStartup
47 @Gated
48 module TimestampDM816XTimer inherits ti.uia.runtime.IUIATimestampProvider {
49
50 /*!
51 * ======== TimerInstance ========
52 * Enumeration that defines the base addresses for each timer instance
53 * of the DM8168 device.
54 */
55 enum TimerBaseAdrs {
56
57
58 TimerBaseAdrs_ARM_Timer4 = 0x48044000,
59 TimerBaseAdrs_ARM_Timer5 = 0x48046000,
60 TimerBaseAdrs_ARM_Timer6 = 0x48048000,
61 TimerBaseAdrs_ARM_Timer7 = 0x4804A000,
62 TimerBaseAdrs_C6000_Timer4 = 0x08044000,
63 TimerBaseAdrs_C6000_Timer5 = 0x08046000,
64 TimerBaseAdrs_C6000_Timer6 = 0x08048000,
65 TimerBaseAdrs_C6000_Timer7 = 0x0804A000
66 };
67
68 enum TimerInstance {
69 TimerInstance_UserConfigured = 0,
70 TimerInstance_Timer4 = 4,
71 TimerInstance_Timer5 = 5,
72 TimerInstance_Timer6 = 6,
73 TimerInstance_Timer7 = 7
74 };
75
76 /*!
77 * ======== PrcmClkMuxBaseAdrs ========
78 * PRCM CM_TIMERX_CLKSEL Timer clock mux select line
79 *
80 * The following enum provides the physical
81 * addresses of the PRCM Clock Mux register
82 * used for Timers 4,5,6 and 7.
83 * If the virtual address of the register
84 * is not the same as the physical address,
85 * AND the autostart config option is true,
86 * the prcmClkMuxBaseAdrs must be configured
87 * with the virtual address of the register.
88 */
89 enum PrcmClkMuxBaseAdrs {
90 PrcmClkMuxBaseAdrs_Timer4 = 0x4818039C,
91 PrcmClkMuxBaseAdrs_Timer5 = 0x481803A0,
92 PrcmClkMuxBaseAdrs_Timer6 = 0x481803A4,
93 PrcmClkMuxBaseAdrs_Timer7 = 0x481803A8
94 }
95
96 /*! Timer OCP Configuration Register (TIOCP_CFG) - L4 interface Configuration. */
97 struct TiocpCfg {
98 Bits8 idlemode; /*! 0=force-idle;1=no-idle;2=Smart-idle;3=Smart-idle */
99 Bits8 emufree; /*! 0=counter frozen; 1=counter free-running */
100 Bits8 softreset; /*! 0=normal mode; 1=soft reset */
101 };
102
103 /*! Timer IRQENABLE CLR (IRQENABLE_CLR) */
104 struct Tier {
105 Bits8 mat_it_ena; /*! Enable match interrupt */
106 Bits8 ovf_it_ena; /*! Enable overflow interrupt */
107 Bits8 tcar_it_ena; /*! Enable capture interrupt */
108 };
109
110 /*! Timer IRQ WAKEUP ENABLE (IRQWAKEEN) */
111 struct Twer {
112 Bits8 mat_wup_ena; /*! Enable match wake-up */
113 Bits8 ovf_wup_ena; /*! Enable overflow wake-up */
114 Bits8 tcar_wup_ena; /*! Enable capture wake-up */
115 };
116
117 /*! Timer Control Register (TCLR). */
118 struct Tclr {
119
120
121 Bits32 ptv; /*! Trigger output mode */
122 Bits8 pre; /*! Prescalar enable */
123 Bits8 ce; /*! Compare enable */
124 Bits8 scpwm;/*! Pulse-width modulation */
125 Bits16 tcm; /*! Transition capture mode */
126 Bits16 trg; /*! Trigger output mode */
127 Bits8 pt; /*! Pulse or toggle select bit */
128 Bits8 captmode; /*! Capture mode select bit */
129 Bits8 gpocfg; /*! PWM output/event detection input pin */
130 };
131
132 /*! L4 Interface Synchronization Control Register (TSICR). */
133 struct Tsicr {
134 Bits8 sft; /*! Reset software functional registers */
135 Bits8 posted; /*! Posted mode selection */
136 };
137
138 /*!
139 * ======= timerNumber ========
140 * Number of the timer to use as the global timer
141 *
142 * The global timer provides a common time reference for all CPUs.
143 * This configuration parameter specifies which timer to use
144 * as the global timer. All CPUs on the device must be
145 * configured to use the same timer as the global timer.
146 * Must be a value of TimerInstance_Timer4,5,6,7 or
147 * TimerInstance_UserConfigured.
148 * If configured as TimerInstance_UserConfigured, then
149 * the module's timerBaseAdrs must be configured with
150 * the timer's virtual address and the module's
151 * prcmClkMuxBaseAdrs must be configured with the
152 * PRCM clock mux register's virtual address.
153 * Note: Timers 0-2 are reserved for Linux.
154 * Timer 3 is reserved for the DSP.
155 */
156 config TimerInstance timerNumber = TimerInstance_Timer7;
157
158 /*!
159 * ======== timerBaseAdrs ========
160 * Base address of the timer to be used as the global timer
161 *
162 * If the virtual address of the timer is not the same as the
163 * physical address, AND the autostart config option is true,
164 * the timerBaseAdrs must be configured with the virtual
165 * address of the timer. Otherwise set to null to allow
166 * module to automatically use the physical address for the
167 * specified timer.
168 */
169 config Ptr timerBaseAdrs = null;
170
171 /*!
172 * ======== prcmClkMuxBaseAdrs ========
173 * Base address of the PRCM register used to select the timer clock source
174 *
175 * If the virtual address of the register is not the same as the
176 * physical address, AND the autostart config option is true,
177 * the prcmClkMuxBaseAdrs must be configured with the virtual
178 * address of the register. Otherwise set to null to allow
179 * module to automatically use the physical address for the
180 * specified timer.
181 */
182 config Ptr prcmClkMuxBaseAdrs = null;
183
184 /*!
185 * ======== prcmClkMuxInitValue =========
186 * Value to write into the prcmClkMux register in order to configure timer clock
187 *
188 * If autoStart is TRUE and prcmClkMuxBaseAdrs is not null
189 * OR timerNumber is set to a value other than UserConfigured
190 * the module will writh the prcmClkMuxInitValue into the
191 * PRCM clock mux register upon startup.
192 *
193 * By default, the value written, sets CLKSEL to SYS_CLK (b24 = 0) and sets
194 * MODULEMODE to 2 (Module is enabled).
195 */
196 config Int prcmClkMuxInitValue = 0x0000002;
197
198 /*!
199 * ======== autoStart ========
200 * Controls whether the module initializes the timer or not
201 *
202 * Must be set to true for one and only one CPU in the device
203 */
204 config Bool autoStart = false;
205
206 /*!
207 * ======== maxTimerClockFreq =========
208 * The highest timer clock frequency.
209 *
210 * The default ticks per second rate of the timer is calculated by dividing
211 * the timer's bus clock frequency by the cyclesPerTick config parameter.
212 */
213 override config Types.FreqHz maxTimerClockFreq = {lo:27000000,hi:0};
214
215
216 /*!
217 * ======== maxBusClockFreq =========
218 * The highest bus clock frequency used to drive the timer.
219 *
220 * The default ticks per second rate of the timer is calculated by dividing
221 * the timer's bus clock frequency by the cyclesPerTick config parameter.
222 */
223 override config Types.FreqHz maxBusClockFreq = {lo:27000000,hi:0};
224
225 /*!
226 * ======== tiocpCfg ========
227 */
228 config TiocpCfg tiocpCfg = {idlemode: 0, emufree: 0, softreset: 1};
229
230 /*!
231 * ======== tier ========
232 */
233 config Tier tier = {mat_it_ena: 0, ovf_it_ena: 1, tcar_it_ena: 0};
234
235 /*!
236 * ======== twer ========
237 */
238 config Twer twer = {mat_wup_ena: 0, ovf_wup_ena: 0, tcar_wup_ena: 0};
239
240 /*!
241 * ======== tclr ========
242 */
243 config Tclr tclr = {ptv: 0, pre: 0, ce: 0, scpwm: 0, tcm: 0, trg: 0,
244 pt: 0, captmode: 0, gpocfg: 0};
245
246 /*!
247 * ======== tsicr ========
248 * Default value of tsicr to use when configuring the timer
249 *
250 * Only used if autoStart is true
251 */
252 config Tsicr tsicr = {sft: 0, posted: 1};
253
254
255 /*!
256 * ======== canFrequencyBeChanged =========
257 * Indicates whether the timer frequency can be changed or not
258 *
259 * @a(returns) true if the timer's clock frequency can be changed
260 */
261 override metaonly config Bool canFrequencyBeChanged = false;
262
263 /*!
264 * ======== cpuCyclesPerTick =========
265 * The number of CPU cycles each tick of the timestamp corresponds to
266 *
267 * A value of 0 indicates that no conversion between the timer's tick count
268 * and CPU cycles is possible.
269 */
270 override metaonly config UInt32 cpuCyclesPerTick = 0;
271
272
273 /*!
274 * ======== canCpuCyclesPerTickBeChanged =========
275 * Indicates whether the timer's cycles per tick divide down ratio can be
276 * changed or not
277 *
278 * @a(returns) true if the timer's CPU cycles per tick can be changed
279 */
280 override metaonly config Bool canCpuCyclesPerTickBeChanged = false;
281 /*!
282 * ======== get32 ========
283 * Return a 32-bit timestamp
284 *
285 * @a(returns)
286 * Returns a 32-bit timestamp value.
287 * Use `{@link #getFreq}` to convert this value into units of real time.
288 *
289 * @see #get64
290 */
291 @DirectCall
292 override Bits32 get32();
293
294 /*!
295 * ======== get64 ========
296 * Return a 64-bit timestamp
297 *
298 * @param(result) pointer to 64-bit result
299 *
300 * This parameter is a pointer to a structure representing a 64-bit
301 * wide timestamp value where the current timestamp is written.
302 *
303 * If the underlying hardware does not support 64-bit resolution, the
304 * `hi` field of `result` is always set to 0; see
305 * `{@link xdc.runtime.Types#Timestamp64}`. So, it is possible for
306 * the `lo` field to wrap around without any change to the `hi` field.
307 * Use `{@link #getFreq}` to convert this value into units of real
308 * time.
309 *
310 * @see #get32
311 */
312 @DirectCall
313 override Void get64(Types.Timestamp64 *result);
314
315 /*!
316 * ======== getFreq ========
317 * Get the timestamp timer's frequency (in Hz)
318 *
319 * @param(freq) pointer to a 64-bit result
320 *
321 * This parameter is a pointer to a structure representing a 64-bit
322 * wide frequency value where the timer's frequency (in Hz)
323 * is written; see `{@link xdc.runtime.Types#FreqHz}`.
324 * This function provides a way of converting timestamp
325 * values into units of real time.
326 *
327 * @see #get32
328 * @see #get64
329 */
330 @DirectCall
331 override Void getFreq(Types.FreqHz *freq);
332
333
334 335 336 337 338 339
340 @DirectCall
341 Void setMSW(Int value);
342 internal:
343 344 345 346 347 348 349 350 351
352 Void start();
353
354 355 356 357 358
359 Void stop();
360
361 struct Module_State {
362 Int timerMSW;
363 Ptr timerBaseAdrs;
364 };
365 }