Instance: ADI_2_REFSYS
Component: ADI_2_REFSYS
Base address: 0x40086000
ADI for REFSYS modules.
Registers Fields should be considered static unless otherwise noted (as dynamic)
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
8 |
0x00 |
0x0000 0000 |
0x4008 6000 |
|
RW |
8 |
0x00 |
0x0000 0002 |
0x4008 6002 |
|
RW |
8 |
0x00 |
0x0000 0003 |
0x4008 6003 |
|
RW |
8 |
0x00 |
0x0000 0004 |
0x4008 6004 |
|
RW |
8 |
0x00 |
0x0000 0005 |
0x4008 6005 |
|
RW |
8 |
0x00 |
0x0000 0006 |
0x4008 6006 |
|
RW |
8 |
0x00 |
0x0000 0007 |
0x4008 6007 |
|
RW |
8 |
0x00 |
0x0000 000A |
0x4008 600A |
|
RW |
8 |
0bX000 0000 |
0x0000 000B |
0x4008 600B |
|
RW |
8 |
0x00 |
0x0000 000C |
0x4008 600C |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4008 6000 | Instance | 0x4008 6000 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
7:5 | RESERVED5 | Internal. Only to be used through TI provided API. | RW | 0b000 | ||
4:0 | TRIM_IREF | Internal. Only to be used through TI provided API. | RW | 0b0 0000 |
Address Offset | 0x0000 0002 | ||
Physical Address | 0x4008 6002 | Instance | 0x4008 6002 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
7:4 | VTRIM_UDIG | Internal. Only to be used through TI provided API. | RW | 0x0 | ||
3:0 | VTRIM_BOD | Internal. Only to be used through TI provided API. | RW | 0x0 |
Address Offset | 0x0000 0003 | ||
Physical Address | 0x4008 6003 | Instance | 0x4008 6003 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
7:4 | VTRIM_COARSE | Internal. Only to be used through TI provided API. | RW | 0x0 | ||
3:0 | VTRIM_DIG | Internal. Only to be used through TI provided API. | RW | 0x0 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4008 6004 | Instance | 0x4008 6004 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
7:3 | RESERVED | Internal. Only to be used through TI provided API. | RO | 0b0 0000 | ||
2:0 | VTRIM_DELTA | Internal. Only to be used through TI provided API. | RW | 0b000 |
Address Offset | 0x0000 0005 | ||
Physical Address | 0x4008 6005 | Instance | 0x4008 6005 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
7:6 | ITRIM_DIGLDO_LOAD | Internal. Only to be used through TI provided API. | RW | 0b00 | |||||||||||||||||
5:3 | ITRIM_DIGLDO | Internal. Only to be used through TI provided API.
|
RW | 0b000 | |||||||||||||||||
2:0 | ITRIM_UDIGLDO | Internal. Only to be used through TI provided API. | RW | 0b000 |
Address Offset | 0x0000 0006 | ||
Physical Address | 0x4008 6006 | Instance | 0x4008 6006 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
7 | RESERVED7 | Internal. Only to be used through TI provided API. | RO | 0 | |||||||||||
6:5 | UDIG_ITEST_EN | Internal. Only to be used through TI provided API. | RW | 0b00 | |||||||||||
4:2 | DIG_ITEST_EN | Internal. Only to be used through TI provided API. | RW | 0b000 | |||||||||||
1 | BIAS_DIS | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||
0 | UDIG_LDO_EN | Internal. Only to be used through TI provided API.
|
RW | 0 |
Address Offset | 0x0000 0007 | ||
Physical Address | 0x4008 6007 | Instance | 0x4008 6007 |
Description | Internal. Only to be used through TI provided API. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
7:4 | RESERVED | Internal. Only to be used through TI provided API. | RO | 0x0 | |||||||||||||||||
3 | IMON_ITEST_EN | Internal. Only to be used through TI provided API. | RW | 0 | |||||||||||||||||
2:0 | TESTSEL | Internal. Only to be used through TI provided API.
|
RW | 0b000 |
Address Offset | 0x0000 000A | ||
Physical Address | 0x4008 600A | Instance | 0x4008 600A |
Description | HPOSC Control 0 Control bits for HPOSC oscillator in OSC_TOP |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
7 | FILTER_EN | Enable HPOSC Bias filter Enable 1 kHz low pass filter in the HPOSC bias. |
RW | 0 | |||||||||||||||||
6:5 | BIAS_RECHARGE_DLY | When HPOSCCTL2.BIAS_HOLD_MODE_EN = 1, low-power sample and hold mode for HPOSC bias is enabled. This field sets the recharge delay for this sample and hold mode by counting number of 48 MHz clock edges.
|
RW | 0b00 | |||||||||||||||||
4:3 | TUNE_CAP | Cap to shift HPOSC center frequency.
|
RW | 0b00 | |||||||||||||||||
2:1 | SERIES_CAP | Cap to set HPOSC into proper mode. Set 1 time in factory. 00: 1.4 pF Cs1/Cs2 01: 1.1 pF Cs1/Cs2 10: 2.1 pF Cs1/Cs2 11: 1.8 pF Cs1/Cs2 |
RW | 0b00 | |||||||||||||||||
0 | DIV3_BYPASS | Bypass for divide by 3 in divider.
|
RW | 0 |
Address Offset | 0x0000 000B | ||
Physical Address | 0x4008 600B | Instance | 0x4008 600B |
Description | HPOSC Control 1 Control bits for HPOSC oscillator in OSC_TOP |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
7:6 | SPARE6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0bX0 | ||
5 | BIAS_DIS | Disable dummy bias current. 0: Dummy bias current on (Default) 1: Dummy bias current off |
RW | 0 | ||
4 | PWRDET_EN | Enable signal for HPOSC power detector. 0: HPOSC power detector disabled. 1: HPOSC power detector enabled. When enabled, Power detector VMAX and VMIN referred to in HPOSCCTL2.ATEST_SEL can be selected. |
RW | 0 | ||
3:0 | BIAS_RES_SET | Adjust the HPOSC bias resistor to set the current in the HPOSC core. Two's complement encoding. 0x8: Highest resistance, lowest current 0x0: Default 0x7: Lowest resistance, maximum current |
RW | 0x0 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4008 600C | Instance | 0x4008 600C |
Description | HPOSC Control 2 Control bits for HPOSC oscillator in OSC_TOP |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
7 | BIAS_HOLD_MODE_EN | Enable signal for bias sample and hold mode. Should give some power savings at expense of increased phase noise or spurs. 0: Disabled hold mode 1: Enabled hold mode |
RW | 0 | ||
6 | TESTMUX_EN | Enable signal for HPOSC test mux. 0: HPOSC test mux disabled. 1: HPOSC test mux enabled. |
RW | 0 | ||
5:4 | ATEST_SEL | ATEST Selection Control 00: Output test bias current 01: Former connction for HPOSC BGAP. Not currently used. 10: Power detector VMAX 11: Power detector VMIN Must also set TESTMUX_EN high to get test outputs. |
RW | 0b00 | ||
3:0 | CURRMIRR_RATIO | Set current mirror ratio in HPOSC. Controls amount of current flowing in HPOSC oscillator core. May need to increase from nominal if nominal setting does not result in oscillation. Two's complement encoding. 0x8: Minimum current (~0 uA) 0x9: 50 uA 0x0: 400 uA 0x7: Maximum current (~750 uA) |
RW | 0x0 |
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