1 /*
2 * Copyright (c) 2014, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 /*
33 * ======== Cache.xdc ========
34 */
35
36 package ti.sysbios.family.c66;
37
38 import xdc.rov.ViewInfo;
39
40 /*!
41 * ======== Cache ========
42 * Cache Module
43 *
44 * This Cache module provides C66 family-specific implementations of the
45 * APIs defined in {@link ti.sysbios.interfaces.ICache ICache}. It also
46 * provides additional C66 specific cache functions.
47 *
48 * Unconstrained Functions
49 * All functions
50 *
51 * @p(html) 52 * <h3> Calling Context </h3>
53 * <table border="1" cellpadding="3">
54 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
55 *
56 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
57 * <!-- -->
58 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
59 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
60 * <tr><td> {@link #getMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
61 * <tr><td> {@link #getMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
62 * <tr><td> {@link #getSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
63 * <tr><td> {@link #inv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
64 * <tr><td> {@link #invL1pAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
65 * <tr><td> {@link #setMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
66 * <tr><td> {@link #setMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
67 * <tr><td> {@link #setSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
68 * <tr><td> {@link #wait} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
69 * <tr><td> {@link #wb} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
70 * <tr><td> {@link #wbAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
71 * <tr><td> {@link #wbL1dAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
72 * <tr><td> {@link #wbInv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
73 * <tr><td> {@link #wbInvAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
74 * <tr><td> {@link #wbInvL1dAll}</td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
75 * <tr><td colspan="6"> Definitions: <br />
76 * <ul>
77 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
78 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
79 * <li> <b>Task</b>: API is callable from a Task thread. </li>
80 * <li> <b>Main</b>: API is callable during any of these phases: </li>
81 * <ul>
82 * <li> In your module startup after this module is started (e.g. Mod_Module_startupDone() returns TRUE). </li>
83 * <li> During xdc.runtime.Startup.lastFxns. </li>
84 * <li> During main().</li>
85 * <li> During BIOS.startupFxns.</li>
86 * </ul>
87 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
88 * <ul>
89 * <li> During xdc.runtime.Startup.firstFxns.</li>
90 * <li> In your module startup before this module is started (e.g. Mod_Module_startupDone() returns FALSE).</li>
91 * </ul>
92 * <li> <b>*</b>: These APIs are intended to be made at initialization time, but are not restricted to this. </li>
93 * </ul>
94 * </td></tr>
95 *
96 * </table>
97 * @p 98 */
99
100 module Cache inherits ti.sysbios.interfaces.ICache
101 {
102 // -------- Module Types --------
103
104 /*!
105 * ======== ModuleView ========
106 * @_nodoc 107 */
108 metaonlystruct ModuleView {
109 String L1PCacheSize;
110 String L1PMode;
111 String L1DCacheSize;
112 String L1DMode;
113 String L2CacheSize;
114 String L2Mode;
115 };
116
117 /*!
118 * ======== MarRegisterView ========
119 * @_nodoc 120 */
121 metaonlystruct MarRegisterView {
122 UInt number;
123 Ptr addr;
124 Ptr startAddrRange;
125 Ptr endAddrRange;
126 Bool cacheable;
127 Bool prefetchable;
128 String marRegisterValue;
129 };
130
131 /*!
132 * ======== rovViewInfo ========
133 * @_nodoc 134 */
135 @Facet
136 metaonlyconfig ViewInfo.Instance rovViewInfo =
137 ViewInfo.create({
138 viewMap: [
139 ['Module',
140 {
141 type: ViewInfo.MODULE,
142 viewInitFxn: 'viewInitModule',
143 structName: 'ModuleView'
144 }
145 ],
146 ['MARs',
147 {
148 type: xdc.rov.ViewInfo.MODULE_DATA,
149 viewInitFxn: 'viewInitMarRegisters',
150 structName: 'MarRegisterView'
151 }
152 ]
153 ]
154 });
155
156 /*! Lists of cache modes for L1/L2 caches */
157 enum Mode {
158 Mode_FREEZE, /*! No new cache lines are allocated */
159 Mode_BYPASS, /*! All access result in long-distance access */
160 Mode_NORMAL /*! Normal operation of cache */
161 };
162
163 /*! Level 1 cache size type definition. Can be used for both L1D & L1P */
164 enum L1Size {
165 L1Size_0K = 0, /*! Amount of cache is 0K, Amount of SRAM is 32K */
166 L1Size_4K = 1, /*! Amount of cache is 4K, Amount of SRAM is 28K */
167 L1Size_8K = 2, /*! Amount of cache is 8K, Amount of SRAM is 24K */
168 L1Size_16K = 3, /*! Amount of cache is 16K, Amount of SRAM is 16K */
169 L1Size_32K = 4 /*! Amount of cache is 32K, Amount of SRAM is 0K */
170 };
171
172 /*! Level 2 cache size type definition. */
173 enum L2Size {
174 L2Size_0K = 0, /*! L2 is all SRAM */
175 L2Size_32K = 1, /*! Amount of cache is 32K */
176 L2Size_64K = 2, /*! Amount of cache is 64K */
177 L2Size_128K = 3, /*! Amount of cache is 128K */
178 L2Size_256K = 4, /*! Amount of cache is 256K */
179 L2Size_512K = 5, /*! Amount of cache is 512K */
180 L2Size_1024K = 6 /*! Amount of cache is 1024K */
181 };
182
183 /*! MAR register setting type definition. */
184 enum Mar {
185 Mar_DISABLE = 0, /*! The Permit Copy bit of MAR register is disabled */
186 Mar_ENABLE = 1 /*! The Permit Copy bit of MAR register is enabled */
187 };
188
189 const UInt32 PC = 1; /*! Permit Caching */
190 const UInt32 WTE = 2; /*! Write through enabled */
191 const UInt32 PCX = 4; /*! Permit caching in external cache */
192 const UInt32 PFX = 8; /*! Prefetchable by external engines */
193
194 /*! Structure for specifying all cache sizes. */
195 struct Size {
196 L1Size l1pSize; /*! L1 Program cache size */
197 L1Size l1dSize; /*! L1 Data data size */
198 L2Size l2Size; /*! L2 cache size */
199 };
200
201 /*! Default sizes of caches.
202 * @_nodoc 203 */
204 config Size initSize = {
205 l1pSize: L1Size_32K,
206 l1dSize: L1Size_32K,
207 l2Size: L2Size_0K
208 };
209
210 /*! @_nodoc 211 * MAR 00 - 31 register bitmask. (for addresses 0x00000000 - 0x1FFFFFFF)
212 *
213 * If undefined by the user, this parameter is configured to match the
214 * memory map of the platform.
215 * Each memory region defined in the platform will have all of its
216 * corresponding MAR bits set.
217 *
218 * To override the default behavior you must initialize this parameter
219 * in your configuration script:
220 *
221 * @p(code) 222 * // disable MAR bits for addresses 0x00000000 to 0x1FFFFFFF
223 * Cache.MAR0_31 = 0x00000000;
224 * @p 225 */
226 metaonlyconfig UInt32 MAR0_31;
227
228 /*! @_nodoc 229 * MAR 32 - 63 register bitmask (for addresses 0x20000000 - 0x3FFFFFFF)
230 *
231 * see {@link #MAR0_31} for more info
232 */
233 metaonlyconfig UInt32 MAR32_63;
234
235 /*! @_nodoc 236 * MAR 64 - 95 register bitmask (for addresses 0x40000000 - 0x5FFFFFFF)
237 *
238 * see {@link #MAR0_31} for more info
239 */
240 metaonlyconfig UInt32 MAR64_95;
241
242 /*! @_nodoc 243 * MAR 96 - 127 register bitmask (for addresses 0x60000000 - 0x7FFFFFFF)
244 *
245 * see {@link #MAR0_31} for more info
246 */
247 metaonlyconfig UInt32 MAR96_127;
248
249 /*! @_nodoc 250 * MAR 128 - 159 register bitmask (for addresses 0x80000000 - 0x9FFFFFFF)
251 *
252 * see {@link #MAR0_31} for more info
253 */
254 metaonlyconfig UInt32 MAR128_159;
255
256 /*! @_nodoc 257 * MAR 160 - 191 register bitmask (for addresses 0xA0000000 - 0xBFFFFFFF)
258 *
259 * see {@link #MAR0_31} for more info
260 */
261 metaonlyconfig UInt32 MAR160_191;
262
263 /*! @_nodoc 264 * MAR 192 - 223 register bitmask (for addresses 0xC0000000 - 0xDFFFFFFF)
265 *
266 * see {@link #MAR0_31} for more info
267 */
268 metaonlyconfig UInt32 MAR192_223;
269
270 /*! @_nodoc 271 * MAR 224 - 255 register bitmask (for addresses 0xE0000000 - 0xFFFFFFFF)
272 *
273 * see {@link #MAR0_31} for more info
274 */
275 metaonlyconfig UInt32 MAR224_255;
276
277 /*! @_nodoc 278 *
279 * This parameter is used to break up large blocks into multiple
280 * small blocks which are done atomically. Each block of the
281 * specified size waits for the cache operation to finish before
282 * starting the next block. Setting this size to 0, means the
283 * cache operations are not done atomically.
284 */
285 config UInt32 atomicBlockSize = 1024;
286
287 /*!
288 * ======== getMarMeta ========
289 * Gets the current MAR value for the specified base address
290 *
291 * @param(baseAddr) address for which MAR value is requested
292 *
293 * @b(returns) MAR value for specified address
294 */
295 metaonly UInt32 getMarMeta(Ptr baseAddr);
296
297 /*!
298 * ======== setMarMeta ========
299 * Set MAR register(s) that corresponds to the specified address range.
300 *
301 * The 'pc' ("Permit Caching") field is enabled for all memory regions
302 * in the device platform. Only set the fields of the Mar structure
303 * which need to be modified. Any field not set retains its reset value.
304 *
305 * @a(Note) 306 * The 'wte' (Bit 1) and 'pcx' (Bit 2) MAR bits are reserved on
307 * C66x CorePac devices.
308 *
309 * @param(baseAddr) start address for which to set MAR
310 * @param(byteSize) size (in bytes) of memory block
311 * @param(value) value for setting MAR register
312 */
313 metaonly Void setMarMeta(Ptr baseAddr, SizeT byteSize, UInt32 value);
314
315 /*!
316 * ======== disable ========
317 * Disables the 'type' cache(s)
318 *
319 * Disabling of L2 cache is currently not supported.
320 */
321 override Void disable(Bits16 type);
322
323 /*!
324 * ======== getMode ========
325 * Get mode of a cache
326 *
327 * @param(type) bit mask of cache type
328 * @b(returns) mode of specified level of cache
329 */
330 Mode getMode(Bits16 type);
331
332 /*!
333 * ======== setMode ========
334 * Set mode of a cache
335 *
336 * @param(type) bit mask of cache type
337 * @param(mode) mode of cache
338 *
339 * @b(returns) previous mode of cache
340 */
341 Mode setMode(Bits16 type, Mode mode);
342
343 /*!
344 * ======== getSize ========
345 * Get sizes of all caches
346 *
347 * @param(size) pointer to structure of type Cache_Size
348 */
349 Void getSize(Size *size);
350
351 /*!
352 * ======== setSize ========
353 * Set sizes of all caches
354 *
355 * @param(size) pointer to structure of type Cache_Size
356 */
357 Void setSize(Size *size);
358
359 /*!
360 * ======== getMar ========
361 * Gets the MAR register for the specified base address
362 *
363 * @param(baseAddr) address for which MAR is requested
364 *
365 * @b(returns) value of MAR register
366 */
367 UInt32 getMar(Ptr baseAddr);
368
369 /*!
370 * ======== setMar ========
371 * Set MAR register(s) that corresponds to the specified address range.
372 *
373 * All cached entries in L1 and L2 are written back and invalidated.
374 *
375 * @a(Note) 376 * The 'wte' (Bit 1) and 'pcx' (Bit 2) MAR bits are reserved on
377 * C66x CorePac devices.
378 *
379 * @param(baseAddr) start address for which to set MAR
380 * @param(byteSize) size (in bytes) of memory block
381 * @param(value) value for setting MAR register
382 */
383 Void setMar(Ptr baseAddr, SizeT byteSize, UInt32 value);
384
385 /*!
386 * ======== invL1pAll ========
387 * Invalidate all of L1 Program cache
388 *
389 * Performs a global invalidate of L1P cache.
390 * Polls the L1P invalidate register until done.
391 */
392 Void invL1pAll();
393
394 /*!
395 * ======== wbAll ========
396 * Write back all caches
397 *
398 * Perform a global write back. There is no effect on L1P cache.
399 * All cache lines are left valid in L1D cache and dirty lines in L1D cache
400 * are written back to L2 or external. All cache lines are left valid in
401 * L2 cache and dirty lines in L2 cache are written back to external.
402 * This function does not wait for write back operation to perculate
403 * through the whole memory system before returing. Call Cache_wait(),
404 * after this function if necessary.
405 */
406 override Void wbAll();
407
408 /*!
409 * ======== wbL1dAll ========
410 * Write back L1D cache
411 *
412 * Perform a global write back of L1D cache. There is no effect on L1P
413 * or L2 cache. All cache lines are left valid in L1D cache and the
414 * dirty lines in L1D cache are written back to L2 or external.
415 * This function does not wait for write back operation to perculate
416 * through the whole memory system before returing. Call Cache_wait(),
417 * after this function if necessary.
418 */
419 Void wbL1dAll();
420
421 /*!
422 * ======== wbInvAll ========
423 * Write back invalidate all caches
424 *
425 * Performs a global write back and invalidate. All cache lines are
426 * invalidated in L1P cache. All dirty cache lines are written back to L2
427 * or external and then invalidated in L1D cache. All dirty cache lines
428 * are written back to external and then invalidated in L2 cache.
429 * This function does not wait for write back operation to perculate
430 * through the whole memory system before returing. Call Cache_wait(),
431 * after this function if necessary.
432 */
433 override Void wbInvAll();
434
435 /*!
436 * ======== wbInvL1dAll ========
437 * Write back invalidate L1D cache
438 *
439 * Performs a global write back and invalidate of L1D cache.
440 * All dirty cache lines are written back to L2 or
441 * external and then invalidated in L1D cache.
442 * This function does not wait for write back operation to perculate
443 * through the whole memory system before returing. Call Cache_wait(),
444 * after this function if necessary.
445 */
446 Void wbInvL1dAll();
447
448 internal:
449
450 /*!
451 * ======== invPrefetchBuffer ========
452 * Invalidate the prefetch buffer
453 */
454 Void invPrefetchBuffer();
455
456 /*
457 * ======== Cache_all ========
458 */
459 Void all(volatile UInt32 *cacheReg);
460
461 /*
462 * ======== block ========
463 * This internal function used by the block cache APIs.
464 */
465 Void block(Ptr blockPtr, SizeT byteCnt, Bool wait,
466 volatile UInt32 *barReg);
467
468 /* cache configuration registers */
469 const UInt32 L2CFG = 0x01840000;
470 const UInt32 L1PCFG = 0x01840020;
471 const UInt32 L1PCC = 0x01840024;
472 const UInt32 L1DCFG = 0x01840040;
473 const UInt32 L1DCC = 0x01840044;
474 const UInt32 MAR = 0x01848000;
475
476 /* For setting the MAR registers at startup */
477 config UInt32 marvalues[256];
478
479 /*
480 * ======== startup ========
481 * startup function to enable cache early during climb-up
482 */
483 Void startup();
484 }