1 /*
2 * Copyright (c) 2014, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 /*
33 * ======== Cache.xdc ========
34 *
35 *
36 */
37
38 package ti.sysbios.family.c64p;
39
40 import xdc.rov.ViewInfo;
41
42 /*!
43 * ======== Cache ========
44 * Cache Module
45 *
46 * This Cache module provides C64+ family-specific implementations of the
47 * APIs defined in {@link ti.sysbios.interfaces.ICache ICache}. It also
48 * provides additional C64+ specific cache functions.
49 *
50 * Unconstrained Functions
51 * All functions
52 *
53 * @p(html) 54 * <h3> Calling Context </h3>
55 * <table border="1" cellpadding="3">
56 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
57 *
58 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
59 * <!-- -->
60 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
61 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
62 * <tr><td> {@link #getMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
63 * <tr><td> {@link #getMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
64 * <tr><td> {@link #getSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
65 * <tr><td> {@link #inv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
66 * <tr><td> {@link #invL1pAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
67 * <tr><td> {@link #setMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
68 * <tr><td> {@link #setMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
69 * <tr><td> {@link #setSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
70 * <tr><td> {@link #wait} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
71 * <tr><td> {@link #wb} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
72 * <tr><td> {@link #wbAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
73 * <tr><td> {@link #wbL1dAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
74 * <tr><td> {@link #wbInv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
75 * <tr><td> {@link #wbInvAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
76 * <tr><td> {@link #wbInvL1dAll}</td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
77 * <tr><td colspan="6"> Definitions: <br />
78 * <ul>
79 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
80 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
81 * <li> <b>Task</b>: API is callable from a Task thread. </li>
82 * <li> <b>Main</b>: API is callable during any of these phases: </li>
83 * <ul>
84 * <li> In your module startup after this module is started (e.g. Mod_Module_startupDone() returns TRUE). </li>
85 * <li> During xdc.runtime.Startup.lastFxns. </li>
86 * <li> During main().</li>
87 * <li> During BIOS.startupFxns.</li>
88 * </ul>
89 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
90 * <ul>
91 * <li> During xdc.runtime.Startup.firstFxns.</li>
92 * <li> In your module startup before this module is started (e.g. Mod_Module_startupDone() returns FALSE).</li>
93 * </ul>
94 * <li> <b>*</b>: These APIs are intended to be made at initialization time, but are not restricted to this. </li>
95 * </ul>
96 * </td></tr>
97 *
98 * </table>
99 * @p 100 */
101
102 @ModuleStartup
103
104 module Cache inherits ti.sysbios.interfaces.ICache
105 {
106 // -------- Module Types --------
107
108 /*!
109 * ======== ModuleView ========
110 * @_nodoc 111 */
112 metaonlystruct ModuleView {
113 String L1PCacheSize;
114 String L1PMode;
115 String L1DCacheSize;
116 String L1DMode;
117 String L2CacheSize;
118 String L2Mode;
119 };
120
121 /*!
122 * ======== MarRegisterView ========
123 * @_nodoc 124 */
125 metaonlystruct MarRegisterView {
126 UInt number;
127 Ptr addr;
128 Ptr startAddrRange;
129 Ptr endAddrRange;
130 };
131
132 /*!
133 * ======== rovViewInfo ========
134 * @_nodoc 135 */
136 @Facet
137 metaonlyconfig ViewInfo.Instance rovViewInfo =
138 ViewInfo.create({
139 viewMap: [
140 ['Module',
141 {
142 type: ViewInfo.MODULE,
143 viewInitFxn: 'viewInitModule',
144 structName: 'ModuleView'
145 }
146 ],
147 ['EnableMARs',
148 {
149 type: xdc.rov.ViewInfo.MODULE_DATA,
150 viewInitFxn: 'viewInitMarRegisters',
151 structName: 'MarRegisterView'
152 }
153 ]
154 ]
155 });
156
157 /*! Lists of cache modes for L1/L2 caches */
158 enum Mode {
159 Mode_FREEZE, /*! No new cache lines are allocated */
160 Mode_BYPASS, /*! All access result in long-distance access */
161 Mode_NORMAL /*! Normal operation of cache */
162 };
163
164 /*! Level 1 cache size type definition. Can be used for both L1D & L1P */
165 enum L1Size {
166 L1Size_0K = 0, /*! Amount of cache is 0K, Amount of SRAM is 32K */
167 L1Size_4K = 1, /*! Amount of cache is 4K, Amount of SRAM is 28K */
168 L1Size_8K = 2, /*! Amount of cache is 8K, Amount of SRAM is 24K */
169 L1Size_16K = 3, /*! Amount of cache is 16K, Amount of SRAM is 16K */
170 L1Size_32K = 4 /*! Amount of cache is 32K, Amount of SRAM is 0K */
171 };
172
173 /*! Level 2 cache size type definition. */
174 enum L2Size {
175 L2Size_0K = 0, /*! L2 is all SRAM */
176 L2Size_32K = 1, /*! Amount of cache is 32K */
177 L2Size_64K = 2, /*! Amount of cache is 64K */
178 L2Size_128K = 3, /*! Amount of cache is 128K */
179 L2Size_256K = 4, /*! Amount of cache is 256K */
180 L2Size_512K = 5, /*! Amount of cache is 512K */
181 L2Size_1024K = 6 /*! Amount of cache is 1024K */
182 };
183
184 /*! MAR register setting type definition. */
185 enum Mar {
186 Mar_DISABLE = 0, /*! The Permit Copy bit of MAR register is disabled */
187 Mar_ENABLE = 1 /*! The Permit Copy bit of MAR register is enabled */
188 };
189
190 /*! Structure for specifying all cache sizes. */
191 struct Size {
192 L1Size l1pSize; /*! L1 Program cache size */
193 L1Size l1dSize; /*! L1 Data data size */
194 L2Size l2Size; /*! L2 cache size */
195 };
196
197 /*!
198 * Cache sizes.
199 *
200 * When this parameter is set in user's cfg script, user set cache sizes
201 * override those specified by the Cache module or the platform.
202 */
203 config Size initSize = {
204 l1pSize: L1Size_32K,
205 l1dSize: L1Size_32K,
206 l2Size: L2Size_0K
207 };
208
209 /*!
210 * EMIF A configuration address.
211 *
212 * By default, this is set to the physical address. On devices with
213 * a MMU where the physical address is mapped to a virtual address,
214 * the virtual address must be specified here.
215 */
216 config UInt *EMIFA_CFG;
217
218 /*!
219 * EMIF A base register address.
220 *
221 * By default, this is set to the emif A base register physical address.
222 * On devices with a MMU where the physical address is mapped to a virtual
223 * address, the virtual address must be specified here.
224 */
225 config UInt EMIFA_BASE;
226
227 /*!
228 * EMIF A address space length.
229 */
230 config UInt EMIFA_LENGTH;
231
232 /*!
233 * EMIF B configuration address.
234 *
235 * By default, this is set to the physical address. On devices with
236 * a MMU where the physical address is mapped to a virtual address,
237 * the virtual address must be specified here.
238 */
239 config UInt *EMIFB_CFG;
240
241 /*!
242 * EMIF B base register address.
243 *
244 * By default, this is set to the emif B base register physical address.
245 * On devices with a MMU where the physical address is mapped to a virtual
246 * address, the virtual address must be specified here.
247 */
248 config UInt EMIFB_BASE;
249
250 /*!
251 * EMIF B address space length.
252 */
253 config UInt EMIFB_LENGTH;
254
255 /*!
256 * EMIF C configuration address.
257 *
258 * By default, this is set to the physical address. On devices with
259 * a MMU where the physical address is mapped to a virtual address,
260 * the virtual address must be specified here.
261 */
262 config UInt *EMIFC_CFG;
263
264 /*!
265 * EMIF C base register address.
266 *
267 * By default, this is set to the emif C base register physical address.
268 * On devices with a MMU where the physical address is mapped to a virtual
269 * address, the virtual address must be specified here.
270 */
271 config UInt EMIFC_BASE;
272
273 /*!
274 * EMIF C address space length.
275 */
276 config UInt EMIFC_LENGTH;
277
278 /*!
279 * MAR 00 - 31 register bitmask. (for addresses 0x00000000 - 0x1FFFFFFF)
280 *
281 * If undefined by the user, this parameter is configured to match the
282 * memory map of the platform.
283 * Each memory region defined in the platform will have all of its
284 * corresponding MAR bits set.
285 *
286 * To override the default behavior you must initialize this parameter
287 * in your configuration script:
288 *
289 * @p(code) 290 * // disable MAR bits for addresses 0x00000000 to 0x1FFFFFFF
291 * Cache.MAR0_31 = 0x00000000;
292 * @p 293 */
294 config UInt32 MAR0_31;
295
296 /*!
297 * MAR 32 - 63 register bitmask (for addresses 0x20000000 - 0x3FFFFFFF)
298 *
299 * see {@link #MAR0_31} for more info
300 */
301 config UInt32 MAR32_63;
302
303 /*!
304 * MAR 64 - 95 register bitmask (for addresses 0x40000000 - 0x5FFFFFFF)
305 *
306 * see {@link #MAR0_31} for more info
307 */
308 config UInt32 MAR64_95;
309
310 /*!
311 * MAR 96 - 127 register bitmask (for addresses 0x60000000 - 0x7FFFFFFF)
312 *
313 * see {@link #MAR0_31} for more info
314 */
315 config UInt32 MAR96_127;
316
317 /*!
318 * MAR 128 - 159 register bitmask (for addresses 0x80000000 - 0x9FFFFFFF)
319 *
320 * see {@link #MAR0_31} for more info
321 */
322 config UInt32 MAR128_159;
323
324 /*!
325 * MAR 160 - 191 register bitmask (for addresses 0xA0000000 - 0xBFFFFFFF)
326 *
327 * see {@link #MAR0_31} for more info
328 */
329 config UInt32 MAR160_191;
330
331 /*!
332 * MAR 192 - 223 register bitmask (for addresses 0xC0000000 - 0xDFFFFFFF)
333 *
334 * see {@link #MAR0_31} for more info
335 */
336 config UInt32 MAR192_223;
337
338 /*!
339 * MAR 224 - 255 register bitmask (for addresses 0xE0000000 - 0xFFFFFFFF)
340 *
341 * see {@link #MAR0_31} for more info
342 */
343 config UInt32 MAR224_255;
344
345 /*!
346 * ======== disable ========
347 * Disables the 'type' cache(s)
348 *
349 * Disabling of L2 cache is currently not supported.
350 */
351 override Void disable(Bits16 type);
352
353 /*!
354 * ======== setMode ========
355 * Set mode of a cache
356 *
357 * @param(type) bit mask of cache type
358 * @param(mode) mode of cache
359 *
360 * @b(returns) previous mode of cache
361 */
362 Mode setMode(Bits16 type, Mode mode);
363
364 /*!
365 * ======== getMode ========
366 * Get mode of a cache
367 *
368 * @param(type) bit mask of cache type
369 * @b(returns) mode of specified level of cache
370 */
371 Mode getMode(Bits16 type);
372
373 /*!
374 * ======== setSize ========
375 * Set sizes of all caches
376 *
377 * @param(size) pointer to structure of type Cache_Size
378 */
379 Void setSize(Size *size);
380
381 /*!
382 * ======== getSize ========
383 * Get sizes of all caches
384 *
385 * @param(size) pointer to structure of type Cache_Size
386 */
387 Void getSize(Size *size);
388
389 /*!
390 * ======== getMar ========
391 * Get the value of the MAR register defined for the specified
392 * base address
393 *
394 * @param(baseAddr) address for which MAR is requested
395 *
396 * @b(returns) value of MAR register associated with specified address
397 */
398 Mar getMar(Ptr baseAddr);
399
400 /*!
401 * ======== setMar ========
402 * Set the MAR register(s) that corresponds to the specified
403 * address range.
404 *
405 * @param(baseAddr) start address for which to set MAR
406 * @param(byteSize) size (in bytes) of memory block
407 * @param(value) enum of type Cache_Mar
408 */
409 Void setMar(Ptr baseAddr, SizeT byteSize, Mar value);
410
411 /*!
412 * ======== invL1pAll ========
413 * Invalidate all of L1 Program cache
414 *
415 * Performs a global invalidate of L1P cache.
416 * Polls the L1P invalidate register until done.
417 */
418 Void invL1pAll();
419
420 /*!
421 * ======== wbAll ========
422 * Write back all caches
423 *
424 * Perform a global write back. There is no effect on L1P cache.
425 * All cache lines are left valid in L1D cache and dirty lines in L1D cache
426 * are written back to L2 or external. All cache lines are left valid in
427 * L2 cache and dirty lines in L2 cache are written back to external.
428 * This function does not wait for write back operation to perculate
429 * through the whole memory system before returing. Call Cache_wait(),
430 * after this function if necessary.
431 */
432 override Void wbAll();
433
434 /*!
435 * ======== wbL1dAll ========
436 * Write back L1D cache
437 *
438 * Perform a global write back of L1D cache. There is no effect on L1P
439 * or L2 cache. All cache lines are left valid in L1D cache and the
440 * dirty lines in L1D cache are written back to L2 or external.
441 * This function does not wait for write back operation to perculate
442 * through the whole memory system before returing. Call Cache_wait(),
443 * after this function if necessary.
444 */
445 Void wbL1dAll();
446
447 /*!
448 * ======== wbInvAll ========
449 * Write back invalidate all caches
450 *
451 * Performs a global write back and invalidate. All cache lines are
452 * invalidated in L1P cache. All dirty cache lines are written back to L2
453 * or external and then invalidated in L1D cache. All dirty cache lines
454 * are written back to external and then invalidated in L2 cache.
455 * This function does not wait for write back operation to perculate
456 * through the whole memory system before returing. Call Cache_wait(),
457 * after this function if necessary.
458 */
459 override Void wbInvAll();
460
461 /*!
462 * ======== wbInvL1dAll ========
463 * Write back invalidate L1D cache
464 *
465 * Performs a global write back and invalidate of L1D cache.
466 * All dirty cache lines are written back to L2 or
467 * external and then invalidated in L1D cache.
468 * This function does not wait for write back operation to perculate
469 * through the whole memory system before returing. Call Cache_wait(),
470 * after this function if necessary.
471 */
472 Void wbInvL1dAll();
473
474 internal:
475
476 Void all(volatile UInt32 *cacheReg);
477
478 /*
479 * ======== block ========
480 * This internal function used by the block cache APIs.
481 */
482 Void block(Ptr blockPtr, SizeT byteCnt, Bool wait,
483 volatile UInt32 *barReg);
484
485 /*
486 * ======== marInit ========
487 * This function initializes the MAR registers
488 */
489 Void marInit(UInt32 mask, UInt32 index);
490
491 /* cache configuration registers */
492 const UInt32 L2CFG = 0x01840000;
493 const UInt32 L1PCFG = 0x01840020;
494 const UInt32 L1PCC = 0x01840024;
495 const UInt32 L1DCFG = 0x01840040;
496 const UInt32 L1DCC = 0x01840044;
497 const UInt32 MAR = 0x01848000;
498
499 struct Module_State {
500 volatile UInt32 *emifAddr; /*! Emif configuration address */
501 }
502 }