1 /*
2 * Copyright (c) 2015, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * ======== Hwi.xdc ========
35 *
36 */
37 package ti.sysbios.family.arm.m3;
38
39 import xdc.rov.ViewInfo;
40 import xdc.runtime.Diags;
41 import xdc.runtime.Log;
42 import xdc.runtime.Assert;
43 import xdc.runtime.Error;
44
45 import ti.sysbios.BIOS;
46 import ti.sysbios.interfaces.IHwi;
47
48 /*!
49 * ======== Hwi ========
50 * Cortex M3 Hardware Interrupt Manager
51 *
52 * The Cortex M3's Nested Vectored Interrupt Controller (NVIC)
53 * supports up to 256 interrupts/exceptions. In practice, most
54 * devices support much fewer (ie the Stellaris family of devices
55 * have only 80 total interrupts defined).
56 *
57 * SYS/BIOS Interrupt IDs or interrupt numbers correspond
58 * to an interrupt's position in the interrupt vector table.
59 *
60 * ID 0 corresponds to vector 0 which is used by the NVIC
61 * to hold the initial (reset) stack pointer value.
62 *
63 * ID 1 corresponds to vector 1 which is the reset vector (ie _c_int00)
64 *
65 * IDs 2-14 are hardwired to exceptions.
66 *
67 * ID 15 is the SysTick timer interrupt.
68 *
69 * ID's 16-255 are mapped to the NVIC's user interrupts 0-239
70 * which are tied to platform specific interrupt sources.
71 *
72 * @a(Zero Latency Interrupts) 73 * The M3 Hwi module supports "zero latency" interrupts.
74 * Interrupts configured with priority greater (in actual
75 * hardware priority, but lower in number) than
76 * {@link #disablePriority Hwi.disablePriority} are NOT
77 * disabled by Hwi_disable().
78 *
79 * Zero latency interrupts are distinguished from regular dispatched
80 * interrupts at create time by their priority being greater
81 * than Hwi.disablePriority.
82 *
83 * Note that since zero latency interrupts don't use the dispatcher,
84 * the {@link ti.sysbios.interfaces.IHwi#arg arg} parameter is not
85 * functional. Also note that due to the M3's native automatic
86 * stacking of saved-by-caller C context on the way to an ISR, zero
87 * latency interrupt handlers are implemented using regular C functions
88 * (ie no 'interrupt' keyword is required).
89 *
90 * @a(WARNING) 91 * Zero latency interrupts are NOT HANDLED by the SYS/BIOS
92 * interrupt dispatcher! Instead, they are vectored to directly.
93 * As such, and because they are NOT DISABLED BY Hwi_disable(),
94 * these interrupt handlers are SEVERELY RESTRICTED in terms of the
95 * SYS/BIOS APIs they can invoke and THREAD SAFETY MUST BE CAREFULLY
96 * CONSIDERED! See the descriptions of {@link #disable Hwi_disable()} and
97 * and {@link #disablePriority Hwi.disablePriority} for more details.
98 *
99 * @a(Interrupt Masking Options) 100 *
101 * The NVIC interrupt controller is designed for priority based
102 * interrupts.
103 *
104 * No support is provided for anything but {@link #MaskingOption_LOWER}.
105 *
106 * @a(Interrupt Priorities) 107 *
108 * In general, the NVIC supports priority values of 0 thru 255.
109 *
110 * In practice, the number of priorities and their values are device
111 * dependent, and their nesting behaviors depend on the
112 * {@link #priGroup Hwi.priGroup} setting.
113 *
114 * For most TI MCU devices, 8 priorities are supported. A peculiarity
115 * of ARM's NVIC is that, although the priority field is an 8 bit value,
116 * the range of supported priority values are left-justified within this
117 * 8 bit field. Consequently, the 8 priority values are not 0 thru 7 as
118 * one might expect, but rather:
119 *
120 * @p(code) 121 * 0x00 // highest priority, non dispatched, Zero Latency priority
122 * 0x20 // highest dispatched interrupt priority
123 * 0x40
124 * 0x60
125 * 0x80
126 * 0xa0
127 * 0xc0
128 * 0xe0 // lowest dispatched interrupt priority, (default)
129 * @p 130 *
131 * Priority 0 is the highest priority and by default is
132 * reserved for zero latency interrupts
133 * (see {@link #disablePriority Hwi.disablePriority}).
134 *
135 * See the Cortex M3 architecture reference manual for details
136 * on the behavior of interrupt priorities and their relationship
137 * to the {@link #priGroup Hwi.priGroup} setting.
138 *
139 * @a(Interrupt Vector Tables) 140 * Tiva devices:
141 *
142 * By default, two vector tables are created for Tiva devices:
143 *
144 * A 16 entry boot vector table is placed at address 0x00000000 in
145 * FLASH.
146 *
147 * An 80 entry vector table is placed at address 0x20000000 in RAM.
148 *
149 * The FLASH boot vector table contains the reset vector and exception
150 * handler vectors used until the RAM based vector table is initialized.
151 *
152 * The RAM vector table contains the 16 exception vectors as well as all
153 * the 64 user interrupt vectors.
154 *
155 * During system startup, the NVIC Vector Table Offset Registor is
156 * intialized to point to this vector table after the table has been
157 * initialized.
158 *
159 * @a( ) 160 * Dual M3 Core ('Ducati') devices:
161 *
162 * By default, Ducati core 0 places its runtime vector table at address
163 * 0x00000400 and core 1 places its runtime vector table at address
164 * 0x00000800.
165 *
166 * Additionally, a boot vector table is placed at address
167 * 0x00000000 which is shared by both cores.
168 *
169 * The boot reset vector function determines which core it is being
170 * executed on and jumps to the reset vector contained in its corresponding
171 * runtime vector table.
172 *
173 * The generation and placement of these vector tables is made
174 * automatically when the
175 * {@link ti.sysbios.family.arm.ducati.Core} module is used.
176 *
177 * Although STRONGLY discouraged, this default behavior can be overridden
178 * by explicitly setting the
179 * {@link #resetVectorAddress Hwi.resetVectorAddress} and
180 * {@link #vectorTableAddress Hwi.vectorTableAddress} config parameters.
181 *
182 * @a(Restrictions) 183 * When used within a dual M3 core (Ducati) arrangement, care must be
184 * taken when initializing this shared resource.
185 * The "Shared Resources" note provided
186 * in the {@link ti.sysbios.family.arm.ducati ducati} package discusses
187 * the management of the various hardware and software resources
188 * shared by the two M3 cores.
189 * @a 190 *
191 * @p(html) 192 * <h3> Calling Context </h3>
193 * <table border="1" cellpadding="3">
194 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
195 *
196 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
197 * <!-- -->
198 * <tr><td> {@link #clearInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
199 * <tr><td> {@link #create} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
200 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
201 * <tr><td> {@link #disableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
202 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> N </td><td> N </td></tr>
203 * <tr><td> {@link #enableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
204 * <tr><td> {@link #Params_init} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
205 * <tr><td> {@link #restore} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
206 * <tr><td> {@link #restoreInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
207 * <tr><td> {@link #construct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
208 * <tr><td> {@link #delete} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
209 * <tr><td> {@link #destruct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
210 * <tr><td> {@link #getHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
211 * <tr><td> {@link #setFunc} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
212 * <tr><td> {@link #setHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
213 * <tr><td colspan="6"> Definitions: <br />
214 * <ul>
215 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
216 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
217 * <li> <b>Task</b>: API is callable from a Task thread. </li>
218 * <li> <b>Main</b>: API is callable during any of these phases: </li>
219 * <ul>
220 * <li> In your module startup after this module is started (e.g. Hwi_Module_startupDone() returns TRUE). </li>
221 * <li> During xdc.runtime.Startup.lastFxns. </li>
222 * <li> During main().</li>
223 * <li> During BIOS.startupFxns.</li>
224 * </ul>
225 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
226 * <ul>
227 * <li> During xdc.runtime.Startup.firstFxns.</li>
228 * <li> In your module startup before this module is started (e.g. Hwi_Module_startupDone() returns FALSE).</li>
229 * </ul>
230 * </ul>
231 * </td></tr>
232 *
233 * </table>
234 * @p 235 */
236
237
238 @Template("./Hwi.xdt") /* generates the vector table and the dispatcher */
239 @ModuleStartup /* generate a call to startup function */
240 @InstanceInitStatic /* allow constructs in static only systems */
241
242 module Hwi inherits ti.sysbios.interfaces.IHwi
243 {
244 // -------- Module Constants --------
245
246 /*!
247 * The Cortex M3 NVIC supports up to 256 interrupts/exceptions.
248 *
249 * The actual number supported is device specific and provided by
250 * the catalog device specification.
251 */
252 config Int NUM_INTERRUPTS;
253
254 /*!
255 * The Cortex M3 NVIC supports up to 256 interrupt priorities.
256 *
257 * The actual number supported is device specific and provided by
258 * the catalog device specification.
259 */
260 config Int NUM_PRIORITIES;
261
262 // -------- Module Types --------
263
264 /*! Hwi vector function type definition. */
265 typedef Void (*VectorFuncPtr)(void);
266
267 /*! Exception hook function type definition. */
268 typedef Void (*ExceptionHookFuncPtr)(ExcContext *);
269
270 /*! NVIC Configuration Control Register (CCR). */
271 struct CCR {
272 Bits8 STKALIGN; /*! Auto stack alignment in exception */
273 Bits8 BFHFNMIGN; /*! All faults ignore BUS Faults */
274 Bits8 DIV_0_TRP; /*! Trap on divide by zero */
275 Bits8 UNALIGN_TRP; /*! Trap on all unaligned accesses */
276 Bits8 USERSETMPEND; /*! Allow user to trigger interrupts */
277 Bits8 NONEBASETHRDENA; /*! Allow entering thread mode anytime */
278 };
279
280 /*! @_nodoc 281 * Nested Vectored Interrupt Controller.
282 */
283 struct NVIC {
284 UInt32 RES_00; /*! 0xE000E000 reserved */
285 UInt32 ICTR; /*! 0xE000E004 Interrupt Control Type */
286 UInt32 RES_08; /*! 0xE000E008 reserved */
287 UInt32 RES_0C; /*! 0xE000E00C reserved */
288 UInt32 STCSR; /*! 0xE000E010 SysTick Control & Status Register */
289 UInt32 STRVR; /*! 0xE000E014 SysTick Reload Value Register */
290 UInt32 STCVR; /*! 0xE000E018 SysTick Current Value Register */
291 UInt32 STCALIB; /*! 0xE000E01C SysTick Calibration Value Register */
292 UInt32 RES_20 [56]; /*! 0xE000E020-0xE000E0FC reserved */
293 UInt32 ISER [8]; /*! 0xE000E100-0xE000E11C Interrupt Set Enable Registers */
294 UInt32 RES_120 [24]; /*! 0xE000E120-0xE000E17C reserved */
295 UInt32 ICER [8]; /*! 0xE000E180-0xE000E19C Interrupt Clear Enable Registers */
296 UInt32 RES_1A0 [24]; /*! 0xE000E1A0-0xE000E1FC reserved */
297 UInt32 ISPR [8]; /*! 0xE000E200-0xE000E21C Interrupt Set Pending Registers */
298 UInt32 RES_220 [24]; /*! 0xE000E220-0xE000E7C reserved */
299 UInt32 ICPR [8]; /*! 0xE000E280-0xE000E29C Interrupt Clear Pending Registers */
300 UInt32 RES_2A0 [24]; /*! 0xE000E2A0-0xE000E2FC reserved */
301 UInt32 IABR [8]; /*! 0xE000E300-0xE000E31C Interrupt Active Bit Registers */
302 UInt32 RES_320 [56]; /*! 0xE000E320-0xE000E3FC reserved */
303 UInt8 IPR [240]; /*! 0xE000E400-0xE000E4EF Interrupt Priority Registers */
304 UInt32 RES_4F0 [516];/*! 0xE000E4F0-0xE000ECFC reserved */
305 UInt32 CPUIDBR; /*! 0xE000ED00 CPUID Base Register */
306 UInt32 ICSR; /*! 0xE000ED04 Interrupt Control State Register */
307 UInt32 VTOR; /*! 0xE000ED08 Vector Table Offset Register */
308 UInt32 AIRCR; /*! 0xE000ED0C Application Interrupt/Reset Control Register */
309 UInt32 SCR; /*! 0xE000ED10 System Control Register */
310 UInt32 CCR; /*! 0xE000ED14 Configuration Control Register */
311 UInt8 SHPR[12]; /*! 0xE000ED18 System Handlers 4-15 Priority Registers */
312 UInt32 SHCSR; /*! 0xE000ED24 System Handler Control & State Register */
313 UInt8 MMFSR; /*! 0xE000ED28 Memory Manage Fault Status Register */
314 UInt8 BFSR; /*! 0xE000ED29 Bus Fault Status Register */
315 UInt16 UFSR; /*! 0xE000ED2A Usage Fault Status Register */
316 UInt32 HFSR; /*! 0xE000ED2C Hard Fault Status Register */
317 UInt32 DFSR; /*! 0xE000ED30 Debug Fault Status Register */
318 UInt32 MMAR; /*! 0xE000ED34 Memory Manager Address Register */
319 UInt32 BFAR; /*! 0xE000ED38 Bus Fault Address Register */
320 UInt32 AFSR; /*! 0xE000ED3C Auxiliary Fault Status Register */
321 UInt32 PFR0; /*! 0xE000ED40 Processor Feature Register */
322 UInt32 PFR1; /*! 0xE000ED44 Processor Feature Register */
323 UInt32 DFR0; /*! 0xE000ED48 Debug Feature Register */
324 UInt32 AFR0; /*! 0xE000ED4C Auxiliary Feature Register */
325 UInt32 MMFR0; /*! 0xE000ED50 Memory Model Fault Register0 */
326 UInt32 MMFR1; /*! 0xE000ED54 Memory Model Fault Register1 */
327 UInt32 MMFR2; /*! 0xE000ED58 Memory Model Fault Register2 */
328 UInt32 MMFR3; /*! 0xE000ED5C Memory Model Fault Register3 */
329 UInt32 ISAR0; /*! 0xE000ED60 ISA Feature Register0 */
330 UInt32 ISAR1; /*! 0xE000ED64 ISA Feature Register1 */
331 UInt32 ISAR2; /*! 0xE000ED68 ISA Feature Register2 */
332 UInt32 ISAR3; /*! 0xE000ED6C ISA Feature Register3 */
333 UInt32 ISAR4; /*! 0xE000ED70 ISA Feature Register4 */
334 UInt32 RES_D74[5]; /*! 0xE000ED74-0xE000ED84 reserved */
335 UInt32 CPACR; /*! 0xE000ED88 Coprocessor Access Control Register */
336 UInt32 RES_D8C[93]; /*! 0xE000ED8C-0xE000EEFC reserved */
337 UInt32 STI; /*! 0xE000EF00 Software Trigger Interrupt Register */
338 UInt32 RES_F04[12]; /*! 0xE000EF04-0xE000EF30 reserved */
339 UInt32 FPCCR; /*! 0xE000EF34 FP Context Control Register */
340 UInt32 FPCAR; /*! 0xE000EF38 FP Context Address Register */
341 UInt32 FPDSCR; /*! 0xE000EF3C FP Default Status Control Register */
342 UInt32 MVFR0; /*! 0xE000EF40 Media & FP Feature Register0 */
343 UInt32 MVFR1; /*! 0xE000EF44 Media & FP Feature Register1 */
344 UInt32 RES_F48[34]; /*! 0xE000EF48-0xE000EFCC reserved */
345 UInt32 PID4; /*! 0xE000EFD0 Peripheral ID Register4 */
346 UInt32 PID5; /*! 0xE000EFD4 Peripheral ID Register5 */
347 UInt32 PID6; /*! 0xE000EFD8 Peripheral ID Register6 */
348 UInt32 PID7; /*! 0xE000EFDC Peripheral ID Register7 */
349 UInt32 PID0; /*! 0xE000EFE0 Peripheral ID Register0 */
350 UInt32 PID1; /*! 0xE000EFE4 Peripheral ID Register1 */
351 UInt32 PID2; /*! 0xE000EFE8 Peripheral ID Register2 */
352 UInt32 PID3; /*! 0xE000EFEC Peripheral ID Register3 */
353 UInt32 CID0; /*! 0xE000EFF0 Component ID Register0 */
354 UInt32 CID1; /*! 0xE000EFF4 Component ID Register1 */
355 UInt32 CID2; /*! 0xE000EFF8 Component ID Register2 */
356 UInt32 CID3; /*! 0xE000EFFC Component ID Register3 */
357 }
358
359 /*!
360 * Physical Nested Vectored Interrupt Controller Device.
361 * Short name is "Hwi_nvic"
362 * Long name is "ti_sysbios_family_arm_m3_Hwi_nvic"
363 */
364 extern volatile NVIC nvic;
365
366 /*!
367 * Virtual Nested Vectored Interrupt Controller structure
368 * written to by both cores for SMP.
369 * Short name is "Hwi_vnvic"
370 * Long name is "ti_sysbios_family_arm_m3_Hwi_vnvic"
371 */
372 extern volatile NVIC vnvic;
373
374 /*!
375 * Exception Context - Register contents at the time of an exception.
376 */
377 struct ExcContext {
378 /* Thread Context */
379 BIOS.ThreadType threadType; /* Type of thread executing at */
380 /* the time the exception occurred */
381 Ptr threadHandle; /* Handle to thread executing at */
382 /* the time the exception occurred */
383 Ptr threadStack; /* Address of stack contents of thread */
384 /* executing at the time the exception */
385 /* occurred */
386 SizeT threadStackSize; /* size of thread stack */
387
388 /* Internal Registers */
389 Ptr r0;
390 Ptr r1;
391 Ptr r2;
392 Ptr r3;
393 Ptr r4;
394 Ptr r5;
395 Ptr r6;
396 Ptr r7;
397 Ptr r8;
398 Ptr r9;
399 Ptr r10;
400 Ptr r11;
401 Ptr r12;
402 Ptr sp;
403 Ptr lr;
404 Ptr pc;
405 Ptr psr;
406
407 /* NVIC registers */
408 Ptr ICSR;
409 Ptr MMFSR;
410 Ptr BFSR;
411 Ptr UFSR;
412 Ptr HFSR;
413 Ptr DFSR;
414 Ptr MMAR;
415 Ptr BFAR;
416 Ptr AFSR;
417 }
418
419 /*! @_nodoc */
420 metaonlystruct BasicView {
421 Ptr halHwiHandle;
422 String label;
423 String type;
424 Int intNum;
425 Int priority;
426 Int group;
427 Int subPriority;
428 String fxn;
429 UArg arg;
430 };
431
432 /*! @_nodoc */
433 metaonlystruct DetailedView {
434 Ptr halHwiHandle;
435 String label;
436 String type;
437 Int intNum;
438 Int priority;
439 Int group;
440 Int subPriority;
441 String fxn;
442 UArg arg;
443 Ptr irp;
444 String status;
445 Int coreId;
446 };
447
448 /*! @_nodoc */
449 metaonlystruct ModuleView {
450 String options[4];
451 String activeInterrupt;
452 String pendingInterrupt;
453 String exception;
454 String hwiStackPeak;
455 SizeT hwiStackSize;
456 Ptr hwiStackBase;
457 };
458
459 /*! @_nodoc */
460 @Facet
461 metaonlyconfig ViewInfo.Instance rovViewInfo =
462 ViewInfo.create({
463 viewMap: [
464 ['Basic',
465 {
466 type: ViewInfo.INSTANCE,
467 viewInitFxn: 'viewInitBasic',
468 structName: 'BasicView'
469 }
470 ],
471 ['Detailed',
472 {
473 type: ViewInfo.INSTANCE,
474 viewInitFxn: 'viewInitDetailed',
475 structName: 'DetailedView'
476 }
477 ],
478 ['Module',
479 {
480 type: ViewInfo.MODULE,
481 viewInitFxn: 'viewInitModule',
482 structName: 'ModuleView'
483 }
484 ],
485 ['Exception',
486 {
487 type: ViewInfo.TREE,
488 viewInitFxn: 'viewInitException',
489 structName: 'ExcContext'
490 }
491 ]
492 ]
493 });
494
495 // -------- Module Parameters --------
496
497 // Logs
498
499 /*!
500 * Issued just prior to Hwi function invocation (with interrupts disabled)
501 */
502 config Log.Event LM_begin = {
503 mask: Diags.USER1 | Diags.USER2,
504 msg: "LM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x"
505 };
506
507 /*!
508 * Issued just after return from Hwi function (with interrupts disabled)
509 */
510 config Log.Event LD_end = {
511 mask: Diags.USER2,
512 msg: "LD_end: hwi: 0x%x"
513 };
514
515 // Asserts
516
517 /*! Assert when bad maskSetting parameter provided */
518 config Assert.Id A_unsupportedMaskingOption = {
519 msg: "A_unsupportedMaskingOption: unsupported maskSetting."
520 };
521
522 // Errors
523
524 /*!
525 * Error raised when Hwi is already defined
526 */
527 config Error.Id E_alreadyDefined = {
528 msg: "E_alreadyDefined: Hwi already defined: intr# %d"
529 };
530
531 /*!
532 * Error raised when the number of interrupts being created
533 * exceeds the number supported.
534 */
535 config Error.Id E_hwiLimitExceeded = {
536 msg: "E_hwiLimitExceeded: Too many interrupts defined"
537 };
538
539 /*!
540 * Error raised when an exception occurs
541 */
542 config Error.Id E_exception = {
543 msg: "E_exception: id = %d, pc = %08x.\nTo see more exception detail, set ti.sysbios.family.arm.m3.Hwi.enableException = true or,\nexamine the Exception view for the ti.sysbios.family.arm.m3.Hwi module using ROV."
544 };
545
546 /*!
547 * Error raised when an uninitialized interrupt occurs
548 */
549 config Error.Id E_noIsr = {
550 msg: "E_noIsr: id = %d, pc = %08x"
551 };
552
553 /*!
554 * Error raised when NMI exception occurs
555 */
556 config Error.Id E_NMI = {
557 msg: "E_NMI: %s"
558 };
559
560 /*!
561 * Error raised when hard fault exception occurs
562 */
563 config Error.Id E_hardFault = {
564 msg: "E_hardFault: %s"
565 };
566
567 /*!
568 * Error raised when memory fault exception occurs
569 */
570 config Error.Id E_memFault = {
571 msg: "E_memFault: %s, address: %08x"
572 };
573
574 /*!
575 * Error raised when bus fault exception occurs
576 */
577 config Error.Id E_busFault = {
578 msg: "E_busFault: %s, address: %08x"
579 };
580
581 /*!
582 * Error raised when usage fault exception occurs
583 */
584 config Error.Id E_usageFault = {
585 msg: "E_usageFault: %s"
586 };
587
588 /*!
589 * Error raised when svCall exception occurs
590 */
591 config Error.Id E_svCall = {
592 msg: "E_svCall: svNum = %d"
593 };
594
595 /*!
596 * Error raised when debugMon exception occurs
597 */
598 config Error.Id E_debugMon = {
599 msg: "E_debugMon: %s"
600 };
601
602 /*!
603 * Error raised when reserved exception occurs
604 */
605 config Error.Id E_reserved = {
606 msg: "E_reserved: %s %d"
607 };
608
609 // configs
610
611 /*!
612 * Size (in number of interrupts) of the table used by the interrupt
613 * dispatcher to locate the corresponding Hwi object. By default,
614 * Hwi.dispatchTableSize will be internally set
615 * to the number of interrupts supported by the device.
616 *
617 * When the Hwi dispatch table size is equal to the number of interrupts
618 * supported {@link #NUM_INTERRUPTS} by the device, a linear-indexed
619 * dispatch table mechanism is used that will consume 4 bytes of RAM
620 * for each interrupt supported.
621 *
622 * If the dispatch table size is set to a number less than the number
623 * of interrupts supported by the device, then a non linear-indexed
624 * dispatch table mechanism is employed that uses 12 bytes of RAM for
625 * each interrupt supported.
626 *
627 * Consequently, for applications that use less than 1/3 of the total
628 * number of interrupts supported by the device, setting this parameter
629 * to the number of interrupts ACTUALLY USED will result in less RAM
630 * memory being used than otherwise.
631 *
632 * For applications that use very few interrupts, this can be a significant RAM memory savings.</p>
633 */
634 metaonlyconfig UInt dispatchTableSize;
635
636 /*!
637 * Location of the Runtime Interrupt Vector Table.
638 * Default is device dependent.
639 *
640 * This parameter allows the user to override the default placement
641 * of the runtime interrupt vector table.
642 * The NVIC's Vector Table Offset
643 * Register (VTOR) is also programmed to this value.
644 *
645 * Some systems require the runtime vector table to be placed at
646 * an address
647 * other than 0 but still need a copy of the two M3 boot vectors
648 * (SP and reset PC), located there. To achieve this, a separate
649 * parameter {@link #resetVectorAdress} is provided. If the
650 * resetVectorAddress has a different value then the vectorTableAddress
651 * then a separate vector table is generated and placed at that
652 * address.
653 *
654 * The vector table must be placed at an address at or lower than
655 * 0x3FFFFC00 and must be aligned on an even 64 word boundary.
656 */
657 metaonlyconfig Ptr vectorTableAddress = 0x00000000;
658
659 /*!
660 * Reset vector table address. Default is 0x00000000.
661 *
662 * This parameter is the address of the vector table used
663 * at system reset time. Typically this is placed at 0x00000000.
664 *
665 * If the Hwi.resetVectorAddress has a different value than
666 * the {@link #vectorTableAddress Hwi.vectorTableAddress}
667 * then two vector tables are generated, one at the Hwi.resetVectorAddress
668 * and another at the {@link #vectorTableAddress Hwi.vectorTableAddress}.
669 *
670 * After the initial boot code has been executed at startup, the NVIC's
671 * Vector Table Offset Register will be programmed to point to the
672 * vector table at the {@link #vectorTableAddress Hwi.vectorTableAddress}.
673 *
674 * is created and placed in the ".resetVecs" section.
675 */
676 metaonlyconfig Ptr resetVectorAddress = 0x00000000;
677
678 /*! Reset Handler. Default is c_int00 */
679 metaonlyconfig VectorFuncPtr resetFunc;
680
681 /*! NMI Handler. Default is set to an internal exception handler */
682 metaonlyconfig VectorFuncPtr nmiFunc;
683
684 /*! Hard Fault Handler. Default is set to an internal exception handler */
685 metaonlyconfig VectorFuncPtr hardFaultFunc;
686
687 /*! Hard Mem Handler. Default is set to an internal exception handler */
688 metaonlyconfig VectorFuncPtr memFaultFunc;
689
690 /*! Bus Fault Handler. Default is set to an internal exception handler */
691 metaonlyconfig VectorFuncPtr busFaultFunc;
692
693 /*! Usage Fault Handler. Default is set to an internal exception handler */
694 metaonlyconfig VectorFuncPtr usageFaultFunc;
695
696 /*! SVCall Handler. Default is set to an internal exception handler */
697 metaonlyconfig VectorFuncPtr svCallFunc;
698
699 /*! Debug Mon Handler. Default is set to an internal exception handler */
700 metaonlyconfig VectorFuncPtr debugMonFunc;
701
702 /*! Reserved Exception Handler. Default is set to an internal exception handler */
703 metaonlyconfig VectorFuncPtr reservedFunc;
704
705 /*! Uninitialized ISR Handler. Default is set to an internal exception handler */
706 config VectorFuncPtr nullIsrFunc;
707
708 /*! Hwi exception handler function type definition. */
709 typedef Void (*ExcHandlerFuncPtr)(UInt *, UInt);
710
711 /*!
712 * Exception handler function pointer.
713 *
714 * The default is determined by the value of Hwi.enableException.
715 *
716 * If the user does NOT set this parameter, then the following default
717 * behavior is followed:
718 *
719 * If Hwi.enableException is true, then the internal 'Hwi_excHandlerMax'
720 * function is used. This exception handler saves the exception context
721 * then does a complete exception decode and dump to the console, then
722 * raises an Error. The exception context can be viewed within CCS
723 * in the ROV Hwi module's Exception view.
724 *
725 * If Hwi.enableException is false, then the internal 'Hwi_excHandlerMin'
726 * function is used. This exception handler saves the exception context
727 * then raises an Error. The exception context can be viewed within CCS
728 * in the ROV Hwi module's Exception view.
729 *
730 * If the user sets this parameter to their own function, then the user's
731 * function will be invoked with the following arguments:
732 *
733 * Void myExceptionHandler(UInt *excStack, UInt lr);
734 *
735 * Where 'excStack' is the address of the stack containing the
736 * register context at the time of the exception, and 'lr' is the
737 * link register value when the low-level-assembly-coded exception
738 * handler was vectored to.
739 *
740 * If this parameter is set to 'null', then an infinite while loop is
741 * entered when an exception occurs. This setting minimizes code and
742 * data footprint but provides no automatic exception decoding.
743 */
744 config ExcHandlerFuncPtr excHandlerFunc = excHandlerMax;
745
746 /*
747 * SMP Interrupt affinity mappings
748 *
749 * In SMP mode, this array maps an interrupt number to the
750 * coreId it is to be tied to. By default, all ints are mapped to
751 * core 0.
752 *
753 * For example, to make Timer 1 from the
754 * ti.sysbios.family.arm.ducati.Timer
755 * module interrupt on core 1 rather than core 0, add the following to
756 * your config file:
757 *
758 * @p(code)
759 * var m3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
760 * m3Hwi.intAffinity[22] = 1;
761 * @p
762 *
763 * @a(constraints)
764 * Valid core Ids are 0 and 1 for Ducati/Benelli SMP applications.
765 *
766 * Interrupt numbers below 16 are ignored.
767 * Only interrupt numbers greater than or equal to #16 can be routed to
768 * either Ducati/Benelli core.
769 *
770 * Interrupt #19, the Ducati inter-core interrupt, is reserved for
771 * exclusive use within the SMP kernel.
772 */
773 metaonlyconfig UInt8 intAffinity[];
774
775 /*!
776 * Enable full exception decoding
777 *
778 * When this is enabled, the exception handler will fully
779 * decode an exception and dump the registers to the
780 * system console.
781 */
782 metaonlyconfig Bool enableException = true;
783
784 /*!
785 * User Exception Context Buffer Address
786 *
787 * By default, when an exception occurs, an {@link #ExcContext}
788 * structure is allocated on the ISR stack and filled in within the
789 * exception handler.
790 *
791 * If {@link #excContextBuffer} is initialized by the user, the
792 * {@link #ExcContext} structure will be placed at that address instead.
793 *
794 * The buffer must be large enough to contain an {@link #ExcContext}
795 * structure.
796 */
797 metaonlyconfig Ptr excContextBuffer;
798 metaonlyconfig Ptr excContextBuffers[];
799
800 /*!
801 * User Exception Stack Buffer Address
802 *
803 * By default, when an exception occurs, a pointer to the base address
804 * of the stack being used by the thread causing the exception is placed
805 *
806 * If {@link #excStackBuffer} is initialized by the user, the
807 * stack contents of the thread causing the exception will be
808 * copied to that address instead.
809 *
810 * The buffer must be large enough to contain the largest task stack
811 * or ISR stack defined in the application.
812 */
813 metaonlyconfig Ptr excStackBuffer;
814 metaonlyconfig Ptr excStackBuffers[];
815
816
817 /*!
818 * User Exception hook function.
819 *
820 * Called just after the exception context has been initialized.
821 *
822 * This function will be run on the ISR stack.
823 *
824 * This function must run to completion.
825 *
826 * It is called without any Task or Swi scheduling protection
827 * and therefore can not call any functions that may cause a Swi or Task
828 * scheduling operation (Swi_post(), Semaphore_post(), Event_post(), etc).
829 */
830 config ExceptionHookFuncPtr excHookFunc = null;
831 config ExceptionHookFuncPtr excHookFuncs[];
832
833 /*!
834 * NVIC CCR register settings
835 *
836 * These setting are written to Hwi_nvic.CCR at startup time.
837 *
838 * See the Cortex M3 architecture reference manual for details
839 * on the meanings of these parameters.
840 */
841 metaonlyconfig CCR nvicCCR = {
842 STKALIGN: 1,
843 BFHFNMIGN: 0,
844 DIV_0_TRP: 0,
845 UNALIGN_TRP: 0,
846 USERSETMPEND: 0,
847 NONEBASETHRDENA: 0
848 };
849
850 /*!
851 * The priority that BASEPRI is set to by Hwi_disable().
852 *
853 * All interrupts configured with equal or less priority (equal or
854 * higher number) than disablePriority are disabled by
855 * {@link #disable Hwi_disable}.
856 * Interrupts configured with higher priority (smaller number) than
857 * Hwi.disablePriority are non-maskable (ie zero-latency).
858 *
859 * The default setting is the second highest interrupt priority
860 * defined for the device (typically '0x20' for devices
861 * which support 8 priority values).
862 * This results in priority 0 (and all
863 * other values in the same priority group, ie 0x00 thru 0x1f)
864 * being the zero-latency, non-maskable interrupt priority.
865 * All other priorities are disabled with Hwi_disable().
866 */
867 config UInt disablePriority;
868
869 /*!
870 * The PRIGROUP setting. Default is 0.
871 *
872 * This value will be written to the PRIGROUP field
873 * within the NVIC's Application Interrupt and Reset Control
874 * Register (Hwi_nvic.AIRCR). It defines how the 8 bit priority
875 * values are interpreted by the hardware.
876 *
877 * Valid settings are 0-7.
878 *
879 * The default setting of 0 causes bits 7-1 of an interrupt's
880 * priority value to be used as pre-emption priority, while bit 0
881 * is used to determine which of two simultaneous interrupts with
882 * the same pre-emption priority will be serviced first.
883 *
884 * For most TI MCU devices, this means that each of the 8 supported
885 * priority values are unique pre-emption priorities and are not
886 * subdivided into priority groups.
887 */
888 config UInt priGroup = 0;
889
890 // -------- Module Functions --------
891
892 /*!
893 * ======== disable ========
894 * Disable all non zero-latency interrupts
895 *
896 * Hwi_disable disables all non zero-latency hardware interrupts and
897 * returns an
898 * opaque key indicating whether interrupts were globally enabled or
899 * disabled on entry to Hwi_disable().
900 * The actual value of the key is target/device specific and is meant
901 * to be passed to Hwi_restore().
902 *
903 * Call Hwi_disable before a portion of a function that needs
904 * to run without interruption. When critical processing is complete, call
905 * Hwi_restore or Hwi_enable to reenable hardware interrupts.
906 *
907 * Servicing of interrupts that occur while interrupts are disabled is
908 * postponed until interrupts are reenabled. However, if the same type
909 * of interrupt occurs several times while interrupts are disabled,
910 * the interrupt's function is executed only once when interrupts are
911 * reenabled.
912 *
913 * A context switch can occur when calling Hwi_enable or Hwi_restore if
914 * an enabled interrupt occurred while interrupts are disabled.
915 *
916 * Hwi_disable may be called from main(). However, since Hwi interrupts
917 * are already disabled in main(), such a call has no effect.
918 *
919 * @a(Implementation Note) 920 * In order to support zero latency interrupts, rather
921 * than setting PRIMASK (which would globally disable all NVIC
922 * interrupts), Hwi_disable() instead writes the value of
923 * {@link #disablePriority Hwi.disablePriority}
924 * to the BASEPRI register. In doing so, all interrupts of equal or
925 * lower priority than Hwi.disablePriority are disabled.
926 *
927 * @a(constraints) 928 * If a Task switching API such as
929 * {@link ti.sysbios.knl.Semaphore#pend Semaphore_pend()},
930 * {@link ti.sysbios.knl.Semaphore#post Semaphore_post()},
931 * {@link ti.sysbios.knl.Task#sleep Task_sleep()}, or
932 * {@link ti.sysbios.knl.Task#yield Task_yield()}
933 * is invoked which results in a context switch while
934 * interrupts are disabled, an embedded call to
935 * {@link #enable Hwi_enable} occurs
936 * on the way to the new thread context which unconditionally re-enables
937 * interrupts. Interrupts will remain enabled until a subsequent
938 * {@link #disable Hwi_disable}
939 * invocation.
940 *
941 * Swis always run with interrupts enabled.
942 * See {@link ti.sysbios.knl.Swi#post Swi_post()} for a discussion Swis and
943 * interrupts.
944 *
945 * @b(returns) opaque key for use by Hwi_restore()
946 */
947 @Macro
948 override UInt disable();
949
950 /*!
951 * ======== enable ========
952 */
953 @Macro
954 override UInt enable();
955
956 /*!
957 * ======== restore ========
958 */
959 @Macro
960 override Void restore(UInt key);
961
962 /*!
963 * @_nodoc 964 * ======== disableFxn ========
965 * function call implementation
966 */
967 UInt disableFxn();
968
969 /*!
970 * @_nodoc 971 * ======== enableFxn ========
972 * function call implementation
973 */
974 UInt enableFxn();
975
976 /*!
977 * @_nodoc 978 * ======== restoreFxn ========
979 * function call implementation
980 */
981 Void restoreFxn(UInt key);
982
983 /*!
984 * ======== inUseMeta ========
985 * @_nodoc 986 * Check for Hwi already in use.
987 * For internal SYS/BIOS use only.
988 * Should be called prior to any internal Hwi.create().
989 *
990 * @param(intNum) interrupt number
991 */
992 metaonly Bool inUseMeta(UInt intNum);
993
994 /*!
995 * @_nodoc 996 * ======== plug ========
997 * Plug a non dispatched interrupt vector with an ISR address.
998 *
999 * @param(intNum) interrupt number
1000 * @param(fxn) pointer to ISR function
1001 */
1002 Void plug(UInt intNum, Void *fxn);
1003
1004 /*!
1005 * ======== getHandle ========
1006 * Returns Hwi_handle associated with intNum
1007 *
1008 * @param(intNum) interrupt number
1009 */
1010 Handle getHandle(UInt intNum);
1011
1012 /*!
1013 * ======== setPriority ========
1014 * Set an interrupt's relative priority.
1015 *
1016 * Valid priorities are 0 - 255. 0 is highest priority.
1017 *
1018 * @a(WARNING) 1019 * Setting the priority of a dispatched Hwi to a value higher
1020 * than {@link #disablePriority Hwi.disablePriority} will make
1021 * it become non-maskable by {@link #disable Hwi_disable()}.
1022 * The behavior of your application after that will be
1023 * unpredictable and will likely yield catastrophic results!
1024 *
1025 * @param(intNum) ID of interrupt
1026 * @param(priority) priority
1027 */
1028 Void setPriority(UInt intNum, UInt priority);
1029
1030 /*!
1031 * ======== excSetBuffers ========
1032 * Set the exception context and stack buffer pointers
1033 *
1034 * @param(excContextBuffer) Address to place ExcContext
1035 * @param(excStackBuffer) Address to place ExcStack
1036 */
1037 Void excSetBuffers(Ptr excContextBuffer, Ptr excStackBuffer);
1038
1039 /*!
1040 * @_nodoc 1041 * ======== initNVIC ========
1042 * initialize everything but leave ints disabled
1043 */
1044 Void initNVIC();
1045
1046 /*!
1047 * @_nodoc 1048 * ======== initStacks ========
1049 * set up M3 split stacks
1050 */
1051 Void initStacks(Ptr hwiStack);
1052
1053 /*!
1054 * @_nodoc 1055 * ======== flushVnvic ========
1056 * Reconfigure a dispatched interrupt.
1057 *
1058 * Called by the internal function "Hwi_updateNvic()".
1059 *
1060 * This is a public API because it is also called by "Core_hwiFunc()".
1061 */
1062 Void flushVnvic();
1063
1064 instance:
1065
1066 /*!
1067 * Interrupt priority.
1068 * The default is 255 which is the lowest priority.
1069 *
1070 * Priority 0 is the highest priority and by default is
1071 * reserved for zero latency interrupts
1072 * (see {@link #disablePriority}).
1073 *
1074 * Valid priorities values are device dependent and their
1075 * nesting behaviors depend on the {@link #priGroup} setting.
1076 *
1077 * See the Cortex M3 architecture reference manual for details
1078 * on the meanings of these parameters.
1079 */
1080 overrideconfig Int priority = 255;
1081
1082 /*!
1083 * Interrupt Masking Option. Only MaskingOption_LOWER is supported.
1084 *
1085 * The NVIC interrupt controller is designed for priority based
1086 * interrupts. No support is provided for anything but
1087 * Hwi.MaskingOption_LOWER.
1088 */
1089 overrideconfig IHwi.MaskingOption maskSetting = IHwi.MaskingOption_LOWER;
1090
1091 /*!
1092 * Use the interrupt dispatcher with this interrupt. Default is true.
1093 *
1094 * If set to false, the interrupt dispatcher is NOT used. Instead,
1095 * the configured Hwi function address is placed directly in the
1096 * vector table, which results in the dispatcher being bypassed.
1097 *
1098 * @a(Warning) 1099 * Interrupts configured to bupass the dispatcher are not allowed
1100 * to call ANY SYS/BIOS APIs that effect thread scheduling. Examples
1101 * of API that should no be invoked are:
1102 *
1103 * @p(dlist) 1104 * - Swi_post(),
1105 * - Semaphore_post(),
1106 * - Event_post(),
1107 * - Task_yield()
1108 * @p 1109 *
1110 * Additionally, although the signature for a non-dispatched interrupt
1111 * function is the same as that for a dispatched interrupt
1112 * (see {@link #FuncPtr}), no argument is actually passed
1113 * to the non-dispatched ISR handler.
1114 */
1115 config Bool useDispatcher = true;
1116
1117 /*!
1118 * ======== reconfig ========
1119 * Reconfigure a dispatched interrupt.
1120 */
1121 Void reconfig(FuncPtr fxn, const Params *params);
1122
1123 internal: /* not for client use */
1124
1125 /*!
1126 * If Hwi.dispatchTableSize is initialized by the user then
1127 * Hwi.numSparseInterrupts is set to the value of Hwi.dispatchTableSize
1128 *
1129 * If Hwi.dispatchTableSize is NOT set by the user, the normal
1130 * intNum-indexed Hwi dispatchTable mechanism is used by
1131 * the dispatcher to find the corresponding Hwi object.
1132 *
1133 * If Hwi.dispatchTableSize is set by the user, then a
1134 * RAM-based fixed sized interrupt jump table is generated
1135 * that contains a repeating pattern of the following 3 word
1136 * assembly code snippets:
1137 *
1138 * hwiX: ldr r3, hwiObjectX
1139 * ldr pc, ti_sysbios_family_arm_m3_Hwi_dispatch__I
1140 * hwiObjectX: .word 0
1141 * hwiY: ldr r3, hwiObjectY
1142 * ldr pc, ti_sysbios_family_arm_m3_Hwi_dispatch__I
1143 * hwiObjectY: .word 0
1144 * ...
1145 *
1146 * Each dispatched interrupt vector is then initialized to point
1147 * to one of these tuples, and the address of the corresponding Hwi
1148 * object is written into the hwiObjectX field.
1149 *
1150 * The low level assembly code in Hwi_dispatch__I preserves the
1151 * value of r3 when it calls Hwi_dispatchC(), which results in
1152 * the Hwi object being passed as the arg3.
1153 *
1154 * Depending on the boolean value of Hwi_numSparseInterrupts, the
1155 * dispatcher either uses the value passed in arg3 as the
1156 * Hwi object, or uses intNum to index into the standard
1157 * dispatchTable to fetch the Hwi object.
1158 */
1159 config UInt numSparseInterrupts = 0;
1160
1161 /*
1162 * Boolean to indicate whether the current target is being
1163 * built using tiva platform.
1164 */
1165 metaonlyconfig Bool isTiva = false;
1166
1167 /*
1168 * The omap4430 ES1 devices have a nasty bug in the unicache
1169 * that locks the bus up when an interrupt occurs at a specific
1170 * time during an internal cache operation.
1171 * The flag below, when set to true, activates special
1172 * code in the Hwi module to work around this bug.
1173 * "WA1_1" comes from "WorkAround 1.1" from a list of potential
1174 * solutions to the problem developed by the design team.
1175 */
1176 metaonlyconfig Bool enableWA1_1 = false;
1177
1178 /*
1179 * Swi and Task module function pointers.
1180 * Used to decouple Hwi from Swi and Task when
1181 * dispatcherSwiSupport or
1182 * dispatcherTaskSupport is false.
1183 */
1184 config UInt (*swiDisable)();
1185 config Void (*swiRestoreHwi)(UInt);
1186 config UInt (*taskDisable)();
1187 config Void (*taskRestoreHwi)(UInt);
1188
1189 /* initial Hwi_nvic.CCR value */
1190 config UInt32 ccr;
1191
1192 /*!
1193 * const array to hold all HookSet objects.
1194 */
1195 config HookSet hooks[length] = [];
1196
1197 /*
1198 * ======== postInit ========
1199 * finish initializing static and dynamic Hwis
1200 */
1201 Int postInit(Object *hwi, Error.Block *eb);
1202
1203 /*!
1204 * ======== updateNvic ========
1205 * Internal SMP function to cause the virtual NVIC to be flushed to the
1206 * actual NVIC.
1207 *
1208 * This function is called by the various user APIs that manipulate
1209 * individual NVIC register bits
1210 * (ie Hwi_enable/disable/restore/clearInterrupt())
1211 *
1212 * If the current core is the owner of "intNum", flushVnvic() is called
1213 * immediately.
1214 *
1215 * Otherwise an intercore interrupt is generated to force the other core
1216 * to perform the flushVnvic().
1217 *
1218 */
1219 Void updateNvic(UInt intNum);
1220
1221 /*!
1222 * ======== excHandlerAsm ========
1223 * asm code exception handler
1224 */
1225 Void excHandlerAsm();
1226
1227 /*!
1228 * ======== excHandler ========
1229 * exception Handler routes to
1230 * either min, max, or spin exception handler
1231 */
1232 Void excHandler(UInt *excStack, UInt lr);
1233
1234 /*!
1235 * ======== excHandlerMin ========
1236 * Minimal Exception Handler
1237 */
1238 Void excHandlerMin(UInt *excStack, UInt lr);
1239
1240 /*!
1241 * ======== excHandlerMax ========
1242 * Full Featured Exception Handler
1243 */
1244 Void excHandlerMax(UInt *excStack, UInt lr);
1245
1246 /*!
1247 * ======== excFillContext ========
1248 */
1249 Void excFillContext(UInt *excStack);
1250
1251 /*!
1252 * ======== excNmi ========
1253 */
1254 Void excNmi(UInt *excStack);
1255
1256 /*!
1257 * ======== excHardFault ========
1258 */
1259 Void excHardFault(UInt *excStack);
1260
1261 /*!
1262 * ======== excMemFault ========
1263 */
1264 Void excMemFault(UInt *excStack);
1265
1266 /*!
1267 * ======== excBusFault ========
1268 */
1269 Void excBusFault(UInt *excStack);
1270
1271 /*!
1272 * ======== excUsageFault ========
1273 */
1274 Void excUsageFault(UInt *excStack);
1275
1276 /*!
1277 * ======== excSvCall ========
1278 */
1279 Void excSvCall(UInt *excStack);
1280
1281 /*!
1282 * ======== excDebugMon ========
1283 */
1284 Void excDebugMon(UInt *excStack);
1285
1286 /*!
1287 * ======== excReserved ========
1288 */
1289 Void excReserved(UInt *excStack, UInt excNum);
1290
1291 /*!
1292 * ======== excNoIsr ========
1293 */
1294 Void excNoIsr(UInt *excStack, UInt excNum);
1295
1296 /*!
1297 * ======== excDumpRegs ========
1298 */
1299 Void excDumpRegs(UInt lr);
1300
1301 /*!
1302 * ======== pendSV ========
1303 * Used by dispatcher
1304 */
1305 Void pendSV();
1306
1307 /*! Hwi vector function type definition. */
1308 typedef Void (*HandlerFuncPtr)(Handle, UInt);
1309
1310 /* Low Level Interrupt Dispatcher Wrapper */
1311 Void dispatch();
1312
1313 /*
1314 * ======== cc26xxRomInitNVIC ========
1315 * Fix for SDOCM00114681: broken Hwi_initNVIC() function.
1316 * Installed rather than Hwi.initNVIC for CC26xx ROM build
1317 * when Hwi.resetVectorAddress is not 0x00000000.
1318 */
1319 Void cc26xxRomInitNVIC();
1320
1321 /*
1322 * "Top Half" of Interrupt Dispatcher
1323 * Does not include Swi_restore() and Task_restore()
1324 */
1325 UInt dispatchC(Irp irp, UInt32 dummy1, UInt32 dummy2, Object *hwi);
1326
1327 /* "Bottom half", run swi scheduler */
1328 Void doSwiRestore(UInt tskKey);
1329
1330 /* "Bottom half", run task scheduler */
1331 Void doTaskRestore(UInt tskKey);
1332
1333 /*! Meta World Only Hwi Configuration Object. */
1334 metaonlystruct InterruptObj {
1335 String name; /* symbol used for vector table entry */
1336 Bool used; /* Interrupt already defined? */
1337 Bool useDispatcher; /* Should dispatcher handle this Int? */
1338 UInt priority; /* priority */
1339 FuncPtr fxn; /* Dispatched ISR function */
1340 Handle hwi; /* Hwi object address */
1341 };
1342
1343 /*!
1344 * Meta-only array of interrupt objects.
1345 * This meta-only array of Hwi config objects is initialized
1346 * in Hwi.xs:module$meta$init().
1347 */
1348 metaonlyconfig InterruptObj interrupt[];
1349
1350 struct Instance_State {
1351 UArg arg; // Argument to Hwi function.
1352 FuncPtr fxn; // Hwi function.
1353 Irp irp; // current IRP/enabled flag
1354 // for static Hwis
1355 UInt8 priority; // Interrupt priorty
1356 Int16 intNum; // Interrupt number. 16 bits used to
1357 // encode non-dispatched interrupt
1358 // as negative intNum
1359 Ptr hookEnv[];
1360 };
1361
1362 struct Module_State {
1363 Char *taskSP; // Temporary storage of interrupted
1364 // Task's SP during ISR execution
1365 Bool excActive[]; // TRUE if an exception has occurred
1366 ExcContext *excContext[]; // Exception context
1367 Ptr excStack[]; // Exception thread stack
1368 Ptr isrStack; // Points to isrStack address
1369 Ptr isrStackBase; // = __TI_STACK_BASE
1370 SizeT isrStackSize; // = Program.stack
1371 Ptr vectorTableBase; // Points to base of vector table
1372 UInt swiTaskKeys; // dispatcher Swi and Task key storage
1373 Ptr dispatchTable; // Ptr to dispatchTable or sparseInterruptTable
1374 volatile Bool vnvicFlushRequired; // if TRUE, Hwi_vnvicFlush will copy
1375 // changed vnvic regs to nvic
1376 UInt8 intAffinity[]; // smp int-to-coreId mappings
1377 UInt32 intAffinityMasks[][]; // smp per-core NVIC register masks
1378 };
1379 }