Instance: GPT0
Component: GPT
Base address: 0x40010000
General Purpose Timer.
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x4001 0000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0004 |
0x4001 0004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0008 |
0x4001 0008 |
|
RW |
32 |
0bXXXX XXX0 0000 0000 00X0 0000 0000 0000 |
0x0000 000C |
0x4001 000C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x4001 0010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x4001 0018 |
|
RO |
32 |
0x0000 0000 |
0x0000 001C |
0x4001 001C |
|
RO |
32 |
0x0000 0000 |
0x0000 0020 |
0x4001 0020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x4001 0024 |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0028 |
0x4001 0028 |
|
RW |
32 |
0x0000 FFFF |
0x0000 002C |
0x4001 002C |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0030 |
0x4001 0030 |
|
RW |
32 |
0x0000 FFFF |
0x0000 0034 |
0x4001 0034 |
|
RW |
32 |
0x0000 0000 |
0x0000 0038 |
0x4001 0038 |
|
RW |
32 |
0x0000 0000 |
0x0000 003C |
0x4001 003C |
|
RW |
32 |
0x0000 0000 |
0x0000 0040 |
0x4001 0040 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x4001 0044 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0048 |
0x4001 0048 |
|
RO |
32 |
0x0000 FFFF |
0x0000 004C |
0x4001 004C |
|
RW |
32 |
0xFFFF FFFF |
0x0000 0050 |
0x4001 0050 |
|
RW |
32 |
0x0000 FFFF |
0x0000 0054 |
0x4001 0054 |
|
RO |
32 |
0x0000 7FFF |
0x0000 0058 |
0x4001 0058 |
|
RO |
32 |
0x0000 0000 |
0x0000 005C |
0x4001 005C |
|
RO |
32 |
0x0000 0000 |
0x0000 0060 |
0x4001 0060 |
|
RO |
32 |
0x0000 0000 |
0x0000 0064 |
0x4001 0064 |
|
RO |
32 |
0x0000 0000 |
0x0000 0068 |
0x4001 0068 |
|
RW |
32 |
0x0000 0000 |
0x0000 006C |
0x4001 006C |
|
RO |
32 |
0x0000 0400 |
0x0000 0FB0 |
0x4001 0FB0 |
|
RW |
32 |
0x0000 0000 |
0x0000 0FB4 |
0x4001 0FB4 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4001 0000 | Instance | 0x4001 0000 |
Description | Configuration | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 0000 | ||||||||||||||
2:0 | CFG | GPT Configuration 0x2- 0x3 - Reserved 0x5- 0x7 - Reserved
|
RW | 0b000 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4001 0004 | Instance | 0x4001 0004 |
Description | Timer A Mode | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | |||||||||||||||||||||||||||||
15:13 | TCACT | Timer Compare Action Select
|
RW | 0b000 | |||||||||||||||||||||||||||||
12 | TACINTD | One-Shot/Periodic Interrupt Disable
|
RW | 0 | |||||||||||||||||||||||||||||
11 | TAPLO | Legacy PWM operation
|
RW | 0 | |||||||||||||||||||||||||||||
10 | TAMRSU | Timer A Match Register Update mode This bit defines when the TAMATCHR and TAPR registers are updated. If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and TAPR are updated when the timer is enabled. If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and TAPR are updated according to the configuration of this bit.
|
RW | 0 | |||||||||||||||||||||||||||||
9 | TAPWMIE | GPT Timer A PWM Interrupt Enable. This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output.
|
RW | 0 | |||||||||||||||||||||||||||||
8 | TAILD | GPT Timer A PWM Interval Load Write
|
RW | 0 | |||||||||||||||||||||||||||||
7 | TASNAPS | GPT Timer A Snap-Shot Mode
|
RW | 0 | |||||||||||||||||||||||||||||
6 | TAWOT | GPT Timer A Wait-On-Trigger
|
RW | 0 | |||||||||||||||||||||||||||||
5 | TAMIE | GPT Timer A Match Interrupt Enable
|
RW | 0 | |||||||||||||||||||||||||||||
4 | TACDIR | GPT Timer A Count Direction
|
RW | 0 | |||||||||||||||||||||||||||||
3 | TAAMS | GPT Timer A Alternate Mode Note: To enable PWM mode, you must also clear TACM and then configure TAMR field to 0x2.
|
RW | 0 | |||||||||||||||||||||||||||||
2 | TACM | GPT Timer A Capture Mode
|
RW | 0 | |||||||||||||||||||||||||||||
1:0 | TAMR | GPT Timer A Mode The Timer mode is based on the timer configuration defined by CFG
|
RW | 0b00 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4001 0008 | Instance | 0x4001 0008 |
Description | Timer B Mode | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | |||||||||||||||||||||||||||||
15:13 | TCACT | Timer Compare Action Select
|
RW | 0b000 | |||||||||||||||||||||||||||||
12 | TBCINTD | One-Shot/Periodic Interrupt Mode
|
RW | 0 | |||||||||||||||||||||||||||||
11 | TBPLO | Legacy PWM operation
|
RW | 0 | |||||||||||||||||||||||||||||
10 | TBMRSU | Timer B Match Register Update mode This bit defines when the TBMATCHR and TBPR registers are updated If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR and TBPR are updated when the timer is enabled. If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR and TBPR are updated according to the configuration of this bit.
|
RW | 0 | |||||||||||||||||||||||||||||
9 | TBPWMIE | GPT Timer B PWM Interrupt Enable. This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output
|
RW | 0 | |||||||||||||||||||||||||||||
8 | TBILD | GPT Timer B PWM Interval Load Write
|
RW | 0 | |||||||||||||||||||||||||||||
7 | TBSNAPS | GPT Timer B Snap-Shot Mode
|
RW | 0 | |||||||||||||||||||||||||||||
6 | TBWOT | GPT Timer B Wait-On-Trigger
|
RW | 0 | |||||||||||||||||||||||||||||
5 | TBMIE | GPT Timer B Match Interrupt Enable.
|
RW | 0 | |||||||||||||||||||||||||||||
4 | TBCDIR | grep
|
RW | 0 | |||||||||||||||||||||||||||||
3 | TBAMS | GPT Timer B Alternate Mode Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR field to 0x2.
|
RW | 0 | |||||||||||||||||||||||||||||
2 | TBCM | GPT Timer B Capture Mode
|
RW | 0 | |||||||||||||||||||||||||||||
1:0 | TBMR | GPT Timer B Mode The Timer mode is based on the timer configuration defined by CFG.CFG
|
RW | 0b00 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4001 000C | Instance | 0x4001 000C |
Description | Control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:15 | RESERVED15 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 | ||||||||||||||
14 | TBPWML | GPT Timer B PWM Output Level 0: Output is unaffected. 1: Output is inverted.
|
RW | 0 | ||||||||||||||
13:12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0bX0 | ||||||||||||||
11:10 | TBEVENT | GPT Timer B Event Mode
|
RW | 0b00 | ||||||||||||||
9 | TBSTALL | GPT Timer B Stall Enable
|
RW | 0 | ||||||||||||||
8 | TBEN | GPT Timer B Enable
|
RW | 0 | ||||||||||||||
7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||||||||||||||
6 | TAPWML | GPT Timer A PWM Output Level
|
RW | 0 | ||||||||||||||
5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | ||||||||||||||
4 | RTCEN | GPT RTC Enable
|
RW | 0 | ||||||||||||||
3:2 | TAEVENT | GPT Timer A Event Mode
|
RW | 0b00 | ||||||||||||||
1 | TASTALL | GPT Timer A Stall Enable
|
RW | 0 | ||||||||||||||
0 | TAEN | GPT Timer A Enable
|
RW | 0 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4001 0010 | Instance | 0x4001 0010 |
Description | Synch Register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||||||||
7:6 | SYNC3 | Synchronize GPT Timer 3.
|
WO | 0b00 | |||||||||||||||||
5:4 | SYNC2 | Synchronize GPT Timer 2.
|
WO | 0b00 | |||||||||||||||||
3:2 | SYNC1 | Synchronize GPT Timer 1
|
WO | 0b00 | |||||||||||||||||
1:0 | SYNC0 | Synchronize GPT Timer 0
|
WO | 0b00 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x4001 0018 | Instance | 0x4001 0018 |
Description | Interrupt Mask This register is used to enable the interrupts. Associated registers: RIS, MIS, ICLR |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 | |||||||||||
16 | WUMIS | Enabling this bit will make the RIS.WURIS interrupt propagate to MIS.WUMIS
|
RW | 0 | |||||||||||
15:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||
13 | DMABIM | Enabling this bit will make the RIS.DMABRIS interrupt propagate to MIS.DMABMIS
|
RW | 0 | |||||||||||
12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
11 | TBMIM | Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS
|
RW | 0 | |||||||||||
10 | CBEIM | Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS
|
RW | 0 | |||||||||||
9 | CBMIM | Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS
|
RW | 0 | |||||||||||
8 | TBTOIM | Enabling this bit will make the RIS.TBTORIS interrupt propagate to MIS.TBTOMIS
|
RW | 0 | |||||||||||
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||
5 | DMAAIM | Enabling this bit will make the RIS.DMAARIS interrupt propagate to MIS.DMAAMIS
|
RW | 0 | |||||||||||
4 | TAMIM | Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS
|
RW | 0 | |||||||||||
3 | RTCIM | Enabling this bit will make the RIS.RTCRIS interrupt propagate to MIS.RTCMIS
|
RW | 0 | |||||||||||
2 | CAEIM | Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS
|
RW | 0 | |||||||||||
1 | CAMIM | Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS
|
RW | 0 | |||||||||||
0 | TATOIM | Enabling this bit will make the RIS.TATORIS interrupt propagate to MIS.TATOMIS
|
RW | 0 |
Address Offset | 0x0000 001C | ||
Physical Address | 0x4001 001C | Instance | 0x4001 001C |
Description | Raw Interrupt Status Associated registers: IMR, MIS, ICLR |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 | ||
16 | WURIS | GPT Write Update Error Raw Interrupt 0: No error. 1: Either Timer A or B was written twice in a Row or Timer A was written before the corresponding Timer B was written. |
RO | 0 | ||
15:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
13 | DMABRIS | GPT Timer B DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed |
RO | 0 | ||
12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
11 | TBMRIS | GPT Timer B Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode. |
RO | 0 | ||
10 | CBERIS | GPT Timer B Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode |
RO | 0 | ||
9 | CBMRIS | GPT Timer B Capture Mode Match Raw Interrupt 0: Match for Timer B has not occured 1: Match for Timer B has occurred. This interrupt asserts when the values in the TBR and TBPR match values in the TBMATCHR and TBPMR, and when configured in Input Edge-Time mode (reg-ref instead!!) |
RO | 0 | ||
8 | TBTORIS | GPT Timer B Time-out Raw Interrupt 0: Timer B has not timed out 1: Timer B has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TBILR, depending on the count direction. |
RO | 0 | ||
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
5 | DMAARIS | GPT Timer A DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed |
RO | 0 | ||
4 | TAMRIS | **GPT **Timer A Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode. |
RO | 0 | ||
3 | RTCRIS | GPT RTC Raw Interrupt 0: The RTC event has not occured 1: The RTC event has occured |
RO | 0 | ||
2 | CAERIS | GPT Timer A Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode |
RO | 0 | ||
1 | CAMRIS | GPT Timer A Capture Mode Match Raw Interrupt 0: Match for Timer A has not occured 1: Match for Timer A has occurred This interrupt asserts when the values in the TAR and TAPR match values in the TAMATCHR and TAPMR, and when configured in Input Edge-Time mode (reg-ref instead!!) |
RO | 0 | ||
0 | TATORIS | GPT Timer A Time-out Raw Interrupt 0: Timer A has not timed out 1: Timer A has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TAILR, depending on the count direction. |
RO | 0 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4001 0020 | Instance | 0x4001 0020 |
Description | Masked Interrupt Status Values are result of bitwise AND operation between RIS and IMR Assosciated clear register: ICLR |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 | ||
16 | WUMIS | 0: No interrupt or interrupt not enabled 1: RIS.WURIS = 1 && IMR.WUMIS = 1 |
RO | 0 | ||
15:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
13 | DMABMIS | 0: No interrupt or interrupt not enabled 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 |
RO | 0 | ||
12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | ||
11 | TBMMIS | 0: No interrupt or interrupt not enabled 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 |
RO | 0 | ||
10 | CBEMIS | 0: No interrupt or interrupt not enabled 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 |
RO | 0 | ||
9 | CBMMIS | 0: No interrupt or interrupt not enabled 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 |
RO | 0 | ||
8 | TBTOMIS | 0: No interrupt or interrupt not enabled 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 |
RO | 0 | ||
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
5 | DMAAMIS | 0: No interrupt or interrupt not enabled 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 |
RO | 0 | ||
4 | TAMMIS | 0: No interrupt or interrupt not enabled 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 |
RO | 0 | ||
3 | RTCMIS | 0: No interrupt or interrupt not enabled 1: RIS.RTCRIS = 1 && IMR.RTCIM = 1 |
RO | 0 | ||
2 | CAEMIS | 0: No interrupt or interrupt not enabled 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 |
RO | 0 | ||
1 | CAMMIS | 0: No interrupt or interrupt not enabled 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 |
RO | 0 | ||
0 | TATOMIS | 0: No interrupt or interrupt not enabled 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 |
RO | 0 |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x4001 0024 | Instance | 0x4001 0024 |
Description | Interrupt Clear This register is used to clear status bits in the RIS and MIS registers |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 | ||
16 | WUECINT | 0: Do nothing. 1: Clear RIS.WURIS and MIS.WUMIS |
RW | 0 | ||
15:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
13 | DMABINT | 0: Do nothing. 1: Clear RIS.DMABRIS and MIS.DMABMIS |
RW | 0 | ||
12 | RESERVED12 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0 | ||
11 | TBMCINT | 0: Do nothing. 1: Clear RIS.TBMRIS and MIS.TBMMIS |
RW | 0 | ||
10 | CBECINT | 0: Do nothing. 1: Clear RIS.CBERIS and MIS.CBEMIS |
RW | 0 | ||
9 | CBMCINT | 0: Do nothing. 1: Clear RIS.CBMRIS and MIS.CBMMIS |
RW | 0 | ||
8 | TBTOCINT | 0: Do nothing. 1: Clear RIS.TBTORIS and MIS.TBTOMIS |
RW | 0 | ||
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
5 | DMAAINT | 0: Do nothing. 1: Clear RIS.DMAARIS and MIS.DMAAMIS |
RW | 0 | ||
4 | TAMCINT | 0: Do nothing. 1: Clear RIS.TAMRIS and MIS.TAMMIS |
RW | 0 | ||
3 | RTCCINT | 0: Do nothing. 1: Clear RIS.RTCRIS and MIS.RTCMIS |
RW | 0 | ||
2 | CAECINT | 0: Do nothing. 1: Clear RIS.CAERIS and MIS.CAEMIS |
RW | 0 | ||
1 | CAMCINT | 0: Do nothing. 1: Clear RIS.CAMRIS and MIS.CAMMIS |
RW | 0 | ||
0 | TATOCINT | 0: Do nothing. 1: Clear RIS.TATORIS and MIS.TATOMIS |
RW | 0 |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4001 0028 | Instance | 0x4001 0028 |
Description | Timer A Interval Load Register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TAILR | GPT Timer A Interval Load Register | RW | 0xFFFF FFFF |
Address Offset | 0x0000 002C | ||
Physical Address | 0x4001 002C | Instance | 0x4001 002C |
Description | Timer B Interval Load Register | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TBILR | GPT Timer B Interval Load Register | RW | 0x0000 FFFF |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4001 0030 | Instance | 0x4001 0030 |
Description | Timer A Match Register Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with TAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in TAILR minus this value. Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and TAMATCHR. In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal. When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond to the contents TBMATCHR). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR. Note : This register is updated internally (takes effect) based on TAMR.TAMRSU |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TAMATCHR | GPT Timer A Match Register | RW | 0xFFFF FFFF |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x4001 0034 | Instance | 0x4001 0034 |
Description | Timer B Match Register When a GPT is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of TAMATCHR. Reads from this register return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases. Note : This register is updated internally (takes effect) based on TBMR.TBMRSU |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | TBMATCHR | GPT Timer B Match Register | RW | 0xFFFF |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x4001 0038 | Instance | 0x4001 0038 |
Description | Timer A Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TAR and TAV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | TAPSR | Timer A Pre-scale. Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 |
RW | 0x00 |
Address Offset | 0x0000 003C | ||
Physical Address | 0x4001 003C | Instance | 0x4001 003C |
Description | Timer B Pre-scale This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in TBR and TBV registers are incremented. In all other individual/split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPT. |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | TBPSR | Timer B Pre-scale. Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 |
RW | 0x00 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x4001 0040 | Instance | 0x4001 0040 |
Description | Timer A Pre-scale Match This register allows software to extend the range of the TAMATCHR when used individually. |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | TAPSMR | GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. | RW | 0x00 |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x4001 0044 | Instance | 0x4001 0044 |
Description | Timer B Pre-scale Match This register allows software to extend the range of the TBMATCHR when used individually. |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||
7:0 | TBPSMR | GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits 23 to 16. | RW | 0x00 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4001 0048 | Instance | 0x4001 0048 |
Description | Timer A Register | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TAR | GPT Timer A Register Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer A Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. |
RO | 0xFFFF FFFF |
Address Offset | 0x0000 004C | ||
Physical Address | 0x4001 004C | Instance | 0x4001 004C |
Description | Timer B Register | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TBR | GPT Timer B Register Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer B Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. |
RO | 0x0000 FFFF |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x4001 0050 | Instance | 0x4001 0050 |
Description | Timer A Value This register shows the current value of the free running 16-bit Timer A. In the 32-bit mode |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TAV | GPT Timer A Register | RW | 0xFFFF FFFF |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x4001 0054 | Instance | 0x4001 0054 |
Description | Timer B Value This register shows the current value of the free running 16-bit Timer B. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count 1. |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | TBV | GPT Timer B Register | RW | 0x0000 FFFF |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x4001 0058 | Instance | 0x4001 0058 |
Description | RTC Pre-divide Value This register shows the current value of the RTC pre-divider in RTC mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count -1. |
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Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | RTCPD | GPT RTC Pre-divider | RO | 0x7FFF |
Address Offset | 0x0000 005C | ||
Physical Address | 0x4001 005C | Instance | 0x4001 005C |
Description | Timer A Pre-scale Snap-shot Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer A pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled a read of a timer value will return the current count -1. |
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Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | PSS | GPT Timer A Pre-scaler | RO | 0x0000 |
Address Offset | 0x0000 0060 | ||
Physical Address | 0x4001 0060 | Instance | 0x4001 0060 |
Description | Timer B Pre-scale Snap-shot Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBPR register either on the next cycle or on the next timeout. This register shows the current value of the Timer B pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled a read of a timer value will return the current count -1. |
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Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | PSS | GPT Timer B Pre-scaler | RO | 0x0000 |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x4001 0064 | Instance | 0x4001 0064 |
Description | Timer A Pre-scale Value This register shows the current value of the Timer A free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count 1. |
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Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | PSV | GPT Timer A Pre-scaler Value | RO | 0x0000 |
Address Offset | 0x0000 0068 | ||
Physical Address | 0x4001 0068 | Instance | 0x4001 0068 |
Description | Timer B Pre-scale Value This register shows the current value of the Timer B free running pre-scaler in the 16-bit mode. Note: When the alternate timer clock (TIMCLK) is enabled, a read of a timer value will return the current count-1. |
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Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | PSV | GPT Timer B Pre-scaler Value | RO | 0x0000 |
Address Offset | 0x0000 006C | ||
Physical Address | 0x4001 006C | Instance | 0x4001 006C |
Description | DMA Event This register allows software to enable/disable GPT DMA trigger events. |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:12 | RESERVED12 | Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. | RO | 0x0 0000 | ||
11 | TBMDMAEN | GPT Timer B Match DMA Trigger Enable | RW | 0 | ||
10 | CBEDMAEN | GPT Timer B Capture Event DMA Trigger Enable | RW | 0 | ||
9 | CBMDMAEN | GPT Timer B Capture Match DMA Trigger Enable | RW | 0 | ||
8 | TBTODMAEN | GPT Timer B Time-Out DMA Trigger Enable | RW | 0 | ||
7:5 | RESERVED5 | Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. | RW | 0b000 | ||
4 | TAMDMAEN | GPT Timer A Match DMA Trigger Enable | RW | 0 | ||
3 | RTCDMAEN | GPT RTC Match DMA Trigger Enable | RW | 0 | ||
2 | CAEDMAEN | GPT Timer A Capture Event DMA Trigger Enable | RW | 0 | ||
1 | CAMDMAEN | GPT Timer A Capture Match DMA Trigger Enable | RW | 0 | ||
0 | TATODMAEN | GPT Timer A Time-Out DMA Trigger Enable | RW | 0 |
Address Offset | 0x0000 0FB0 | ||
Physical Address | 0x4001 0FB0 | Instance | 0x4001 0FB0 |
Description | Peripheral Version This register provides information regarding the GPT version |
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Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VERSION | Timer Revision. | RO | 0x0000 0400 |
Address Offset | 0x0000 0FB4 | ||
Physical Address | 0x4001 0FB4 | Instance | 0x4001 0FB4 |
Description | Combined CCP Output This register is used to logically AND CCP output pairs for each timer |
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Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | CCP_AND_EN | Enables AND operation of the CCP outputs for timers A and B. 0 : PWM outputs of Timer A and Timer B are the internal generated PWM signals of the respective timers. 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM signals and Timer B PWM ouput is Timer B PWM signal only. |
RW | 0 |
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