TI Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3220SF:1

Tool Chain Version: 20.2.0

BIOS Version: bios_6_83_00_16_eng

XDCTools Version: xdctools_3_61_04_30_core_eng

Benchmark	Cycles
Interrupt Latency	177
Hwi_restore()	19
Hwi_disable()	26
Hwi dispatcher prolog	146
Hwi dispatcher epilog	333
Hwi dispatcher	474
Hardware Interrupt to Blocked Task	763
Hardware Interrupt to Software Interrupt	515
Swi_enable()	112
Swi_disable()	26
Post Software Interrupt Again	51
Post Software Interrupt without Context Switch	138
Post Software Interrupt with Context Switch	271
Create a New Task without Context Switch	4022
Set a Task Priority without a Context Switch	264
Task_yield()	271
Post Semaphore No Waiting Task	143
Post Semaphore No Task Switch	266
Post Semaphore with Task Switch	347
Pend on Semaphore No Context Switch	111
Pend on Semaphore with Task Switch	412
Clock_getTicks()	24
POSIX Create a New Task without Context Switch	7592
POSIX Set a Task Priority without a Context Switch	340
POSIX Post Semaphore No Waiting Task	168
POSIX Post Semaphore No Task Switch	295
POSIX Post Semaphore with Task Switch	378
POSIX Pend on Semaphore No Context Switch	128
POSIX Pend on Semaphore with Task Switch	441

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.