IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3220SF:1

Tool Chain Version: 8.50.1.245

BIOS Version: bios_6_83_00_16_eng

XDCTools Version: xdctools_3_61_04_30_core_eng

Benchmark	Cycles
Interrupt Latency	231
Hwi_restore()	23
Hwi_disable()	25
Hwi dispatcher prolog	189
Hwi dispatcher epilog	371
Hwi dispatcher	545
Hardware Interrupt to Blocked Task	838
Hardware Interrupt to Software Interrupt	577
Swi_enable()	125
Swi_disable()	37
Post Software Interrupt Again	32
Post Software Interrupt without Context Switch	131
Post Software Interrupt with Context Switch	266
Create a New Task without Context Switch	3793
Set a Task Priority without a Context Switch	276
Task_yield()	316
Post Semaphore No Waiting Task	127
Post Semaphore No Task Switch	277
Post Semaphore with Task Switch	372
Pend on Semaphore No Context Switch	89
Pend on Semaphore with Task Switch	418
Clock_getTicks()	28
POSIX Create a New Task without Context Switch	6892
POSIX Set a Task Priority without a Context Switch	356
POSIX Post Semaphore No Waiting Task	156
POSIX Post Semaphore No Task Switch	309
POSIX Post Semaphore with Task Switch	391
POSIX Pend on Semaphore No Context Switch	72
POSIX Pend on Semaphore with Task Switch	429

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.