IAR Cortex-M4 Timing Benchmarks
Target Platform: ti.platforms.simplelink:CC3200:1
Tool Chain Version: 8.11.1.47
BIOS Version: bios_6_52_00_11_eng
XDCTools Version: xdctools_3_50_03_33_core
Benchmark | Cycles |
---|---|
Interrupt Latency | 149 |
Hwi_restore() | 13 |
Hwi_disable() | 15 |
Hwi dispatcher prolog | 117 |
Hwi dispatcher epilog | 244 |
Hwi dispatcher | 351 |
Hardware Interrupt to Blocked Task | 575 |
Hardware Interrupt to Software Interrupt | 389 |
Swi_enable() | 73 |
Swi_disable() | 17 |
Post Software Interrupt Again | 23 |
Post Software Interrupt without Context Switch | 101 |
Post Software Interrupt with Context Switch | 209 |
Create a New Task without Context Switch | 1902 |
Set a Task Priority without a Context Switch | 193 |
Task_yield() | 235 |
Post Semaphore No Waiting Task | 52 |
Post Semaphore No Task Switch | 200 |
Post Semaphore with Task Switch | 275 |
Pend on Semaphore No Context Switch | 77 |
Pend on Semaphore with Task Switch | 308 |
Clock_getTicks() | 14 |
POSIX Create a New Task without Context Switch | 3712 |
POSIX Set a Task Priority without a Context Switch | 248 |
POSIX Post Semaphore No Waiting Task | 71 |
POSIX Post Semaphore No Task Switch | 221 |
POSIX Post Semaphore with Task Switch | 284 |
POSIX Pend on Semaphore No Context Switch | 60 |
POSIX Pend on Semaphore with Task Switch | 308 |
The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.
See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.