var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');

    // descriptor attribute structure
    var attrs = new Mmu.DescriptorAttrs();

    // Note: If running in SMP mode, all page table entries for memory
    //       shared between the SMP cores should mark the memory as
    //       inner-shareable. This is to ensure that the cached copy of
    //       the memory region is kept coherent accross cores.

    Mmu.initDescAttrsMeta(attrs);
    attrs.type = Mmu.DescriptorType_BLOCK;    // BLOCK descriptor
    attrs.shareable = 3;                      // inner-sharerable
    attrs.attrIndx = 2;                       // MAIR0 Byte2 describes
                                              // memory attributes for
                                              // this level2 entry

    // write memory region attribute in mairRegAttr[2] i.e. MAIR0 Reg Byte2
    Mmu.setMAIRMeta(2, 0xFF);              // Mark mem regions as cacheable

    // Set the descriptor for each entry in the address range
    for (var i=0x80000000; i < 0x90000000; i = i + 0x00200000) {
        // Each 'BLOCK' descriptor entry spans a 2MB address range
        Mmu.setSecondLevelDescMeta(i, i, attrs);
    }

    var memmap = Program.cpu.memoryMap;
    var DDR = null;

    // Find DDR in memory map
    for (var i=0; i < memmap.length; i++) {
        if (memmap[i].name == "DDR") {
            DDR = memmap[i];
        }
    }

    // Place the MMU table in the DDR memory segment if it exists
    if (DDR != null) {
        var sectionName =
                  "ti.sysbios.family.arm.a15.mmuSecondLevelTableSection2";
        Program.sectMap[sectionName] = new Program.SectionSpec();
        Program.sectMap[sectionName].type = "NOLOAD";
        Program.sectMap[sectionName].loadSegment = "DDR";
    }
    else {
        print("No DDR memory segment was found");
    }

    var Cache = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
    var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');

    // Enable the cache
    Cache.enableCache = true;

    // Enable the MMU (Required for L1/L2 data caching)
    Mmu.enableMMU = true;

    // descriptor attribute structure
    var peripheralAttrs = new Mmu.DescriptorAttrs();

    Mmu.initDescAttrsMeta(peripheralAttrs);

    peripheralAttrs.type = Mmu.DescriptorType_BLOCK;  // BLOCK descriptor
    peripheralAttrs.noExecute = true;                 // not executable
    peripheralAttrs.accPerm = 0;                      // read/write at PL1
    peripheralAttrs.attrIndx = 1;                     // MAIR0 Byte1 describes
                                                      // memory attributes for
                                                      // each BLOCK MMU entry

    // write memory region attribute in mairRegAttr[1] i.e. MAIR0 Reg Byte1
    Mmu.setMAIRMeta(1, 0x0);    // Mark mem regions as strongly ordered memory

    // Define the base address of the 2 MB page
    // the peripheral resides in.
    var peripheralBaseAddr = 0xa0400000;

    // Configure the corresponding MMU page descriptor accordingly
    Mmu.setSecondLevelDescMeta(peripheralBaseAddr,
                               peripheralBaseAddr,
                               peripheralAttrs);

  ...

  Void main(Int argc, Char * argv[])
  {
      Mmu_DescriptorAttrs attrs;
      Mmu_initDescAttrs(&attrs);

     // Note: If running in SMP mode, all page table entries for memory
     //       shared between the SMP cores should mark the memory as
     //       inner-shareable. This is to ensure that the cached copy of
     //       the memory region is kept coherent accross cores.

      attrs.type = Mmu_DescriptorType_BLOCK;
      attrs.shareable = 3;            // inner-shareable
      attrs.accPerm = 1;              // read/write at any privelege level
      attrs.attrIndx = 3;             // Use MAIR0 Register Byte 3 for
                                      // determining the memory attributes
                                      // for each MMU entry

      // Note: If running in SMP mode, Mmu_setMAIR() and
      //       Mmu_setFirstLevelDesc() should not be called with Hwi, Swi
      //       or Tasking disabled.

      // attrIndx[2] = 0b0 selects MAIR0
      // attrIndx[1:0] = 0b11 selects Byte 3 in MAIR0
      //
      // A value of 0x4F is written to Byte 3 of MAIR0. This marks the memory
      // as Normal Memory that is outer non-cacheable and inner write-back
      // cacheable for both reads and writes.

      Mmu_setMAIR(3, 0x4F);

      // Update the first level table's MMU entry for 0x80000000 with the
      // new attributes.
      Mmu_setFirstLevelDesc((Ptr)0x80000000, (UInt64)0x80000000, &attrs);
  }

  ...

  Void main(Int argc, Char * argv[])
  {
      Mmu_DescriptorAttrs attrs;
      Mmu_initDescAttrs(&attrs);

      attrs.type = Mmu_DescriptorType_BLOCK;
      attrs.shareable = 0;            // non-shareable
      attrs.accPerm = 1;              // read/write at any privelege level
      attrs.attrIndx = 4;             // Use MAIR1 Register Byte 0 for
                                      // determining the memory attributes
                                      // for each MMU entry

      // Note: If running in SMP mode, Mmu_setMAIR() and
      //       Mmu_setSecondLevelDesc() should not be called with Hwi, Swi
      //       or Tasking disabled.

      // attrIndx[2] = 0b1 selects MAIR1
      // attrIndx[1:0] = 0b00 selects Byte 0 in MAIR1
      //
      // A value of 0x4F is written to Byte 0 of MAIR1. This marks the memory
      // as Normal Memory that is outer non-cacheable and inner write-back
      // cacheable for both reads and writes.

      Mmu_setMAIR(4, 0x4F);

      // Update the MMU entry for 0x80000000 with the new attributes.
      Mmu_setSecondLevelDesc((Ptr)0x80000000, (UInt64)0x80000000, &attrs);
  }

  ...

  Void main(Int argc, Char * argv[])
  {
      UInt32 peripheralBaseAddr;
      Mmu_DescriptorAttrs attrs;
      Mmu_initDescAttrs(&attrs);

      attrs.type = Mmu_DescriptorType_TABLE;

      // Note: If running in SMP mode, Mmu_setMAIR(), Mmu_setFirstLevelDesc()
      //       and Mmu_setSecondLevelDesc() should not be called with Hwi, Swi
      //       or Tasking disabled.

      // This example assumes that the first level descriptor table does
      // not have a valid entry for virtual address 0x40000000-0x7FFFFFFF.
      // The below call will map this virtual address range in the first
      // level table to the correponding second level descriptor table.
      Mmu_setFirstLevelDesc((Ptr)0x40000000, (UInt64)0x0, &attrs);

      // Note: Second argument to Mmu_setFirstLevelDesc() is ignored
      //       when attrs.type is DescriptorType_TABLE.


      attrs.type = Mmu.DescriptorType_BLOCK;  // BLOCK descriptor
      attrs.noExecute = true;                 // not executable
      attrs.accPerm = 0;                      // read/write at PL1
      attrs.attrIndx = 1;                     // MAIR0 Byte1 describes
                                              // memory attributes for
                                              // each BLOCK MMU entry

      // write memory region attribute in mairRegAttr[1] i.e. MAIR0 Reg Byte1
      Mmu_setMAIRMeta(1, 0x0); // Mark mem regions as strongly ordered memory

      // Define the base address of the 2 MB page
      // the peripheral resides in.
      peripheralBaseAddr = 0x40400000;

      // Now that there is a first level entry for virtual addresses
      // 0x40000000-0x7FFFFFFF that maps these addresses to a second
      // level descriptor table, we can add a second level entry that
      // maps the peripheral base address to a physical address.
      Mmu_setSecondLevelDesc(peripheralBaseAddr, peripheralBaseAddr, &attrs);
  }

• There are size and alignment requirements on the third level descriptor tables depending on the page size.
• See the ARM v7AR Architecture Reference Manual for more info.