module ti.catalog.arm.cortexm3.concertoInit.Boot

Concerto M3 Boot Support

The Boot module supports boot initialization for the Concerto M3 core. A special boot init function is created based on the configuration settings for this module. This function is hooked into the xdc.runtime.Reset.fxns[] array and called very early at boot time (prior to cinit processing). [ more ... ]
C synopsis target-domain sourced in ti/catalog/arm/cortexm3/concertoInit/Boot.xdc
#include <ti/catalog/arm/cortexm3/concertoInit/Boot.h>
Constants
extern const Bool 
extern const Bits32 
extern const Bits32 
extern const Bits32 
 
DETAILS
The Boot module supports boot initialization for the Concerto M3 core. A special boot init function is created based on the configuration settings for this module. This function is hooked into the xdc.runtime.Reset.fxns[] array and called very early at boot time (prior to cinit processing).
The code to support the boot module is placed in a separate section named ".text:.bootCodeSection" to allow placement of this section in the linker .cmd file if necessary. This section is a subsection of the ".text" section so this code will be placed into the .text section unless explicitly placed, either through Program.sectMap or through a linker command file.
 
config Boot_configureClocks  // module-wide

Clock configuration flag, default is false

C synopsis target-domain
extern const Bool Boot_configureClocks;
 
DETAILS
Set to true to configure the PLL and system and M3 subsystem clock dividers.
 
config Boot_sharedMemoryAccess  // module-wide

Shared RAM M3 write access

C synopsis target-domain
extern const Bits32 Boot_sharedMemoryAccess[8];
 
DETAILS
This parameter is used for writing the MSxSRCR registers. It determines the M3 write access for each shared RAM segment only when the M3 is the owner of the shared RAM segment. By default, the M3 is allowed to CPU fetch, DMA write, and CPU write.
Bit 0 is for CPU fetch. 0 - fetch allowed, 1 - fetch not allowed Bit 1 is for DMA write. 0 - write allowed, 1 - write not allowed Bit 2 is for CPU write. 0 - write allowed, 1 - write not allowed
 
config Boot_sharedMemoryEnable  // module-wide

Shared RAM memory enable mask

C synopsis target-domain
extern const Bits32 Boot_sharedMemoryEnable;
 
DETAILS
This parameter is used for writing the MEMCNF register. By default, all shared RAM segments will be enabled at runtime. To disable a shared RAM segment, set the corresponding bit to 0. If any data is loaded to a shared RAM segment, the segment must be enabled prior to loading the program through other means.
 
config Boot_sharedMemoryOwnerMask  // module-wide

Shared RAM owner select mask

C synopsis target-domain
extern const Bits32 Boot_sharedMemoryOwnerMask;
 
DETAILS
This parameter is used for writing the MSxMSEL register. By default, each value of each shared RAM select bit is '0'. This means the M3 is the owner and has write access based upon the sharedMemoryAccess bits. Setting a '1' in any bit position makes the C28 the owner of that shared RAM segment.
 
Configuration settings sourced in ti/catalog/arm/cortexm3/concertoInit/Boot.xdc
var Boot = xdc.useModule('ti.catalog.arm.cortexm3.concertoInit.Boot');
module-wide constants & types
 
        const Boot.M3Div_1// Divide by 1;
        const Boot.M3Div_2// Divide by 2;
        const Boot.M3Div_4// Divide by 4;
 
        const Boot.Div_1// Divide by 1;
        const Boot.Div_2// Divide by 2;
        const Boot.Div_4// Divide by 4;
        const Boot.Div_8// Divide by 8;
 
    var obj = new Boot.ModuleView// ;
        obj.configureClocks = Bool  ...
        obj.OSCCLK = UInt  ...
        obj.SPLLIMULT = UInt  ...
        obj.SPLLFMULT = String  ...
        obj.SYSDIVSEL = String  ...
        obj.M3SSDIVSEL = String  ...
        obj.bootC28 = Bool  ...
module-wide config parameters
 
 
 
metaonly enum Boot.FractMult

System PLL Fractional Multiplier (SPLLFMULT) value

Configuration settings
values of type Boot.FractMult
    const Boot.Fract_0;
    // Fractional multiplier is 0
    const Boot.Fract_25;
    // Fractional multiplier is 0.25
    const Boot.Fract_50;
    // Fractional multiplier is 0.5
    const Boot.Fract_75;
    // Fractional multiplier is 0.75
 
 
metaonly enum Boot.M3Div

M3 Subsystem Clock Divider (M3SSDIVSEL) value

Configuration settings
values of type Boot.M3Div
    const Boot.M3Div_1;
    // Divide by 1
    const Boot.M3Div_2;
    // Divide by 2
    const Boot.M3Div_4;
    // Divide by 4
 
 
metaonly enum Boot.SysDiv

System Clock Divider (SYSDIVSEL) value

Configuration settings
values of type Boot.SysDiv
    const Boot.Div_1;
    // Divide by 1
    const Boot.Div_2;
    // Divide by 2
    const Boot.Div_4;
    // Divide by 4
    const Boot.Div_8;
    // Divide by 8
 
 
metaonly struct Boot.ModuleView
Configuration settings
var obj = new Boot.ModuleView;
 
    obj.configureClocks = Bool  ...
    obj.OSCCLK = UInt  ...
    obj.SPLLIMULT = UInt  ...
    obj.SPLLFMULT = String  ...
    obj.SYSDIVSEL = String  ...
    obj.M3SSDIVSEL = String  ...
    obj.bootC28 = Bool  ...
 
 
config Boot.configureClocks  // module-wide

Clock configuration flag, default is false

Configuration settings
Boot.configureClocks = Bool false;
 
DETAILS
Set to true to configure the PLL and system and M3 subsystem clock dividers.
C SYNOPSIS
 
config Boot.sharedMemoryAccess  // module-wide

Shared RAM M3 write access

Configuration settings
Boot.sharedMemoryAccess = Bits32[8] undefined;
 
DETAILS
This parameter is used for writing the MSxSRCR registers. It determines the M3 write access for each shared RAM segment only when the M3 is the owner of the shared RAM segment. By default, the M3 is allowed to CPU fetch, DMA write, and CPU write.
Bit 0 is for CPU fetch. 0 - fetch allowed, 1 - fetch not allowed Bit 1 is for DMA write. 0 - write allowed, 1 - write not allowed Bit 2 is for CPU write. 0 - write allowed, 1 - write not allowed
C SYNOPSIS
 
config Boot.sharedMemoryEnable  // module-wide

Shared RAM memory enable mask

Configuration settings
Boot.sharedMemoryEnable = Bits32 0xffffffff;
 
DETAILS
This parameter is used for writing the MEMCNF register. By default, all shared RAM segments will be enabled at runtime. To disable a shared RAM segment, set the corresponding bit to 0. If any data is loaded to a shared RAM segment, the segment must be enabled prior to loading the program through other means.
C SYNOPSIS
 
config Boot.sharedMemoryOwnerMask  // module-wide

Shared RAM owner select mask

Configuration settings
Boot.sharedMemoryOwnerMask = Bits32 0;
 
DETAILS
This parameter is used for writing the MSxMSEL register. By default, each value of each shared RAM select bit is '0'. This means the M3 is the owner and has write access based upon the sharedMemoryAccess bits. Setting a '1' in any bit position makes the C28 the owner of that shared RAM segment.
C SYNOPSIS
 
metaonly config Boot.M3SSDIVSEL  // module-wide

M3 Subsystem Clock Divider (M3SSDIVSEL) value

Configuration settings
Boot.M3SSDIVSEL = Boot.M3Div Boot.M3Div_4;
 
 
metaonly config Boot.OSCCLK  // module-wide

OSCCLK input frequency to PLL, in MHz. Default is 20 MHz

Configuration settings
Boot.OSCCLK = UInt 20;
 
DETAILS
This is the frequency of the oscillator clock (OSCCLK) input to the PLL.
 
metaonly config Boot.SPLLFMULT  // module-wide

System PLL Fractional Multiplier (SPLLFMULT) value

Configuration settings
Boot.SPLLFMULT = Boot.FractMult Boot.Fract_0;
 
 
metaonly config Boot.SPLLIMULT  // module-wide

System PLL Integer Multiplier (SPLLIMULT) value

Configuration settings
Boot.SPLLIMULT = UInt 1;
 
 
metaonly config Boot.SYSDIVSEL  // module-wide

System Clock Divider (SYSDIVSEL) value

Configuration settings
Boot.SYSDIVSEL = Boot.SysDiv Boot.Div_8;
 
 
metaonly config Boot.bootC28  // module-wide

Initiate booting of the C28 processor. Default is false

Configuration settings
Boot.bootC28 = Bool false;
 
DETAILS
Set to true to enable the M3 to initiate boot of the C28.
If enabled, this will occur after the optional clock configuration step, enabled by configureClocks.
 
metaonly config Boot.bootFromFlash  // module-wide

Boot from Flash flag. Default is true

Configuration settings
Boot.bootFromFlash = Bool true;
 
DETAILS
Set to true to enable booting the M3 from Flash.
 
metaonly config Boot.configSharedRAMs  // module-wide

Configure Shared RAM regions before booting the C28 processor. Default is true

Configuration settings
Boot.configSharedRAMs = Bool true;
 
DETAILS
Set to true to enable Shared RAM regions S0-S7, to set the owner of each region and the write access permissions for the onwer.
 
metaonly config Boot.configureFlashController  // module-wide

Flash controller configuration flag, default is true

Configuration settings
Boot.configureFlashController = Bool true;
 
DETAILS
Set to true to enable the configuration of the Flash controller wait states, program and data cache.
 
metaonly config Boot.configureFlashWaitStates  // module-wide

Flash controller wait states configuration flag, default is true

Configuration settings
Boot.configureFlashWaitStates = Bool true;
 
DETAILS
Set to true to configure the Flash controller wait states. The number of wait states is computed based upon the CPU frequency.
 
metaonly config Boot.enableFlashDataCache  // module-wide

Flash controller data cache enable flag, default is true

Configuration settings
Boot.enableFlashDataCache = Bool true;
 
DETAILS
Set to true to enable the Flash controller's data cache.
 
metaonly config Boot.enableFlashProgramCache  // module-wide

Flash controller program cache enable flag, default is true

Configuration settings
Boot.enableFlashProgramCache = Bool true;
 
DETAILS
Set to true to enable the Flash controller's program cache.
 
metaonly config Boot.initC28RAMs  // module-wide

Initialize C28 RAM regions before booting the C28 processor. Default is true

Configuration settings
Boot.initC28RAMs = Bool true;
 
DETAILS
Set to true to enable initialization of these C28 RAM regions: M1, CtoM, LO, L1, L2, and L3. RAM locations will be zeroed, and the ECC or parity bits will be initialized.
 
metaonly config Boot.limpAbortFunction  // module-wide

Function to be called when Limp mode is detected

Configuration settings
Boot.limpAbortFunction = Fxn undefined;
 
DETAILS
This function is called when the Boot module is about to configure the PLL, but finds the device operating in Limp mode (i.e., the mode when a missing OSCCLK input has been detected).
If this function is not specified by the application, a default function will be used, which spins in an infinite loop.
 
metaonly config Boot.loadSegment  // module-wide

Specifies where to load the flash function

Configuration settings
Boot.loadSegment = String undefined;
 
DETAILS
If 'configureFlashWaitStates' is true, then this parameter determines where the ".ti_catalog_c2800_initF2837x_flashfuncs" section gets loaded.
 
metaonly config Boot.rovViewInfo  // module-wide
Configuration settings
Boot.rovViewInfo = ViewInfo.Instance ViewInfo.create;
 
 
metaonly config Boot.runSegment  // module-wide

Specifies where to run the flash function

Configuration settings
Boot.runSegment = String undefined;
 
DETAILS
If 'configureFlashWaitStates' is true then this parameter determines where the ".ti_catalog_c2800_initF2837x_flashfuncs" section gets executed at runtime.
generated on Fri, 10 Jun 2016 23:30:28 GMT