1 /*
2 * Copyright (c) 2012, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * */
32 /*
33 * ======== Cache.xdc ========
34 *
35 *
36 */
37
38 package ti.sysbios.family.c66;
39
40 import xdc.rov.ViewInfo;
41
42 /*!
43 * ======== Cache ========
44 * Cache Module
45 *
46 * This Cache module provides C66 family-specific implementations of the
47 * APIs defined in {@link ti.sysbios.interfaces.ICache ICache}. It also
48 * provides additional C66 specific cache functions.
49 *
50 * Unconstrained Functions
51 * All functions
52 *
53 * @p(html) 54 * <h3> Calling Context </h3>
55 * <table border="1" cellpadding="3">
56 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
57 *
58 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
59 * <!-- -->
60 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
61 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
62 * <tr><td> {@link #getMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
63 * <tr><td> {@link #getMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
64 * <tr><td> {@link #getSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
65 * <tr><td> {@link #inv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
66 * <tr><td> {@link #invL1pAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
67 * <tr><td> {@link #setMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
68 * <tr><td> {@link #setMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
69 * <tr><td> {@link #setSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
70 * <tr><td> {@link #wait} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
71 * <tr><td> {@link #wb} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
72 * <tr><td> {@link #wbAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
73 * <tr><td> {@link #wbInv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
74 * <tr><td> {@link #wbInvAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
75 * <tr><td colspan="6"> Definitions: <br />
76 * <ul>
77 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
78 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
79 * <li> <b>Task</b>: API is callable from a Task thread. </li>
80 * <li> <b>Main</b>: API is callable during any of these phases: </li>
81 * <ul>
82 * <li> In your module startup after this module is started (e.g. Mod_Module_startupDone() returns TRUE). </li>
83 * <li> During xdc.runtime.Startup.lastFxns. </li>
84 * <li> During main().</li>
85 * <li> During BIOS.startupFxns.</li>
86 * </ul>
87 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
88 * <ul>
89 * <li> During xdc.runtime.Startup.firstFxns.</li>
90 * <li> In your module startup before this module is started (e.g. Mod_Module_startupDone() returns FALSE).</li>
91 * </ul>
92 * <li> <b>*</b>: These APIs are intended to be made at initialization time, but are not restricted to this. </li>
93 * </ul>
94 * </td></tr>
95 *
96 * </table>
97 * @p 98 */
99
100 @ModuleStartup
101
102 module Cache inherits ti.sysbios.interfaces.ICache
103 {
104 // -------- Module Types --------
105
106 /*!
107 * ======== ModuleView ========
108 * @_nodoc 109 */
110 metaonlystruct ModuleView {
111 String L1PCacheSize;
112 String L1PMode;
113 String L1DCacheSize;
114 String L1DMode;
115 String L2CacheSize;
116 String L2Mode;
117 };
118
119 /*!
120 * ======== MarRegisterView ========
121 * @_nodoc 122 */
123 metaonlystruct MarRegisterView {
124 UInt number;
125 Ptr addr;
126 Ptr startAddrRange;
127 Ptr endAddrRange;
128 Bool cacheable;
129 Bool writeThrough;
130 Bool externalCacheable;
131 Bool prefetchable;
132 };
133
134 /*!
135 * ======== rovViewInfo ========
136 * @_nodoc 137 */
138 @Facet
139 metaonlyconfig ViewInfo.Instance rovViewInfo =
140 ViewInfo.create({
141 viewMap: [
142 ['Module',
143 {
144 type: ViewInfo.MODULE,
145 viewInitFxn: 'viewInitModule',
146 structName: 'ModuleView'
147 }
148 ],
149 ['EnableMARs',
150 {
151 type: xdc.rov.ViewInfo.MODULE_DATA,
152 viewInitFxn: 'viewInitMarRegisters',
153 structName: 'MarRegisterView'
154 }
155 ]
156 ]
157 });
158
159 /*! Lists of cache modes for L1/L2 caches */
160 enum Mode {
161 Mode_FREEZE, /*! No new cache lines are allocated */
162 Mode_BYPASS, /*! All access result in long-distance access */
163 Mode_NORMAL /*! Normal operation of cache */
164 };
165
166 /*! Level 1 cache size type definition. Can be used for both L1D & L1P */
167 enum L1Size {
168 L1Size_0K = 0, /*! Amount of cache is 0K, Amount of SRAM is 32K */
169 L1Size_4K = 1, /*! Amount of cache is 4K, Amount of SRAM is 28K */
170 L1Size_8K = 2, /*! Amount of cache is 8K, Amount of SRAM is 24K */
171 L1Size_16K = 3, /*! Amount of cache is 16K, Amount of SRAM is 16K */
172 L1Size_32K = 4 /*! Amount of cache is 32K, Amount of SRAM is 0K */
173 };
174
175 /*! Level 2 cache size type definition. */
176 enum L2Size {
177 L2Size_0K = 0, /*! L2 is all SRAM */
178 L2Size_32K = 1, /*! Amount of cache is 32K */
179 L2Size_64K = 2, /*! Amount of cache is 64K */
180 L2Size_128K = 3, /*! Amount of cache is 128K */
181 L2Size_256K = 4, /*! Amount of cache is 256K */
182 L2Size_512K = 5, /*! Amount of cache is 512K */
183 L2Size_1024K = 6 /*! Amount of cache is 1024K */
184 };
185
186 /*! MAR register setting type definition. */
187 enum Mar {
188 Mar_DISABLE = 0, /*! The Permit Copy bit of MAR register is disabled */
189 Mar_ENABLE = 1 /*! The Permit Copy bit of MAR register is enabled */
190 };
191
192 const UInt32 PC = 1; /*! Permit Caching */
193 const UInt32 WTE = 2; /*! Write through enabled */
194 const UInt32 PCX = 4; /*! Permit caching in external cache */
195 const UInt32 PFX = 8; /*! Prefetchable by external engines */
196
197 /*! Structure for specifying all cache sizes. */
198 struct Size {
199 L1Size l1pSize; /*! L1 Program cache size */
200 L1Size l1dSize; /*! L1 Data data size */
201 L2Size l2Size; /*! L2 cache size */
202 };
203
204 /*! Default sizes of caches.
205 * @_nodoc 206 */
207 config Size initSize = {
208 l1pSize: L1Size_32K,
209 l1dSize: L1Size_32K,
210 l2Size: L2Size_0K
211 };
212
213 /*! @_nodoc 214 * MAR 00 - 31 register bitmask. (for addresses 0x00000000 - 0x1FFFFFFF)
215 *
216 * If undefined by the user, this parameter is configured to match the
217 * memory map of the platform.
218 * Each memory region defined in the platform will have all of its
219 * corresponding MAR bits set.
220 *
221 * To override the default behavior you must initialize this parameter
222 * in your configuration script:
223 *
224 * @p(code) 225 * // disable MAR bits for addresses 0x00000000 to 0x1FFFFFFF
226 * Cache.MAR0_31 = 0x00000000;
227 * @p 228 */
229 metaonlyconfig UInt32 MAR0_31;
230
231 /*! @_nodoc 232 * MAR 32 - 63 register bitmask (for addresses 0x20000000 - 0x3FFFFFFF)
233 *
234 * see {@link #MAR0_31} for more info
235 */
236 metaonlyconfig UInt32 MAR32_63;
237
238 /*! @_nodoc 239 * MAR 64 - 95 register bitmask (for addresses 0x40000000 - 0x5FFFFFFF)
240 *
241 * see {@link #MAR0_31} for more info
242 */
243 metaonlyconfig UInt32 MAR64_95;
244
245 /*! @_nodoc 246 * MAR 96 - 127 register bitmask (for addresses 0x60000000 - 0x7FFFFFFF)
247 *
248 * see {@link #MAR0_31} for more info
249 */
250 metaonlyconfig UInt32 MAR96_127;
251
252 /*! @_nodoc 253 * MAR 128 - 159 register bitmask (for addresses 0x80000000 - 0x9FFFFFFF)
254 *
255 * see {@link #MAR0_31} for more info
256 */
257 metaonlyconfig UInt32 MAR128_159;
258
259 /*! @_nodoc 260 * MAR 160 - 191 register bitmask (for addresses 0xA0000000 - 0xBFFFFFFF)
261 *
262 * see {@link #MAR0_31} for more info
263 */
264 metaonlyconfig UInt32 MAR160_191;
265
266 /*! @_nodoc 267 * MAR 192 - 223 register bitmask (for addresses 0xC0000000 - 0xDFFFFFFF)
268 *
269 * see {@link #MAR0_31} for more info
270 */
271 metaonlyconfig UInt32 MAR192_223;
272
273 /*! @_nodoc 274 * MAR 224 - 255 register bitmask (for addresses 0xE0000000 - 0xFFFFFFFF)
275 *
276 * see {@link #MAR0_31} for more info
277 */
278 metaonlyconfig UInt32 MAR224_255;
279
280 /*! @_nodoc 281 *
282 * This parameter is used to break up large blocks into multiple
283 * small blocks which are done atomically. Each block of the
284 * specified size waits for the cache operation to finish before
285 * starting the next block. Setting this size to 0, means the
286 * cache operations are not done atomically.
287 */
288 config UInt32 atomicBlockSize = 1024;
289
290 /*!
291 * ======== getMarMeta ========
292 * Gets the current MAR value for the specified base address
293 *
294 * @param(baseAddr) address for which MAR value is requested
295 *
296 * @b(returns) MAR value for specified address
297 */
298 metaonly UInt32 getMarMeta(Ptr baseAddr);
299
300 /*!
301 * ======== setMarMeta ========
302 * Set MAR register(s) that corresponds to the specified address range.
303 *
304 * The 'pc' ("Permit Caching") field is enabled for all memory regions
305 * in the device platform. Only set the fields of the Mar structure
306 * which need to be modified. Any field not set retains its reset value.
307 *
308 * @param(baseAddr) start address for which to set MAR
309 * @param(byteSize) size (in bytes) of memory block
310 * @param(value) value for setting MAR register
311 */
312 metaonly Void setMarMeta(Ptr baseAddr, SizeT byteSize, UInt32 value);
313
314 /*!
315 * ======== disable ========
316 * Disables the 'type' cache(s)
317 *
318 * Disabling of L2 cache is currently not supported.
319 */
320 @DirectCall
321 override Void disable(Bits16 type);
322
323 /*!
324 * ======== getMode ========
325 * Get mode of a cache
326 *
327 * @param(type) bit mask of cache type
328 * @b(returns) mode of specified level of cache
329 */
330 @DirectCall
331 Mode getMode(Bits16 type);
332
333 /*!
334 * ======== setMode ========
335 * Set mode of a cache
336 *
337 * @param(type) bit mask of cache type
338 * @param(mode) mode of cache
339 *
340 * @b(returns) previous mode of cache
341 */
342 @DirectCall
343 Mode setMode(Bits16 type, Mode mode);
344
345 /*!
346 * ======== getSize ========
347 * Get sizes of all caches
348 *
349 * @param(size) pointer to structure of type Cache_Size
350 */
351 @DirectCall
352 Void getSize(Size *size);
353
354 /*!
355 * ======== setSize ========
356 * Set sizes of all caches
357 *
358 * @param(size) pointer to structure of type Cache_Size
359 */
360 @DirectCall
361 Void setSize(Size *size);
362
363 /*!
364 * ======== getMar ========
365 * Gets the MAR register for the specified base address
366 *
367 * @param(baseAddr) address for which MAR is requested
368 *
369 * @b(returns) value of MAR register
370 */
371 @DirectCall
372 UInt32 getMar(Ptr baseAddr);
373
374 /*!
375 * ======== setMar ========
376 * Set MAR register(s) that corresponds to the specified address range.
377 *
378 * All cached entries in L1 and L2 are written back and invalidated.
379 *
380 * @param(baseAddr) start address for which to set MAR
381 * @param(byteSize) size (in bytes) of memory block
382 * @param(value) value for setting MAR register
383 */
384 @DirectCall
385 Void setMar(Ptr baseAddr, SizeT byteSize, UInt32 value);
386
387 /*!
388 * ======== invL1pAll ========
389 * Invalidate all of L1 Program cache
390 *
391 * Performs a global invalidate of L1P cache.
392 * Polls the L1P invalidate register until done.
393 */
394 @DirectCall
395 Void invL1pAll();
396
397 /*!
398 * ======== wbAll ========
399 * Write back all caches
400 *
401 * Perform a global write back. There is no effect on L1P cache.
402 * All cache lines are left valid in L1D cache and the data in L1D cache
403 * is written back to L2 or external. All cache lines are left valid in
404 * L2 cache and the data in L2 cache is written back to external.
405 */
406 @DirectCall
407 override Void wbAll();
408
409 /*!
410 * ======== wbInvAll ========
411 * Write back invalidate all caches
412 *
413 * Performs a global write back and invalidate. All cache lines are
414 * invalidated in L1P cache. All cache lines are written back to L2 or
415 * external and then invalidated in L1D cache. All cache lines are
416 * written back to external and then invalidated in L2 cache.
417 */
418 @DirectCall
419 override Void wbInvAll();
420
421
422 internal:
423
424 /*!
425 * ======== invPrefetchBuffer ========
426 * Invalidate the prefetch buffer
427 */
428 Void invPrefetchBuffer();
429
430 /* cache configuration registers */
431 const UInt32 L2CFG = 0x01840000;
432 const UInt32 L1PCFG = 0x01840020;
433 const UInt32 L1PCC = 0x01840024;
434 const UInt32 L1DCFG = 0x01840040;
435 const UInt32 L1DCC = 0x01840044;
436 const UInt32 MAR = 0x01848000;
437
438 /* For setting the MAR registers at startup */
439 config UInt32 marvalues[256];
440 }
441 /*
442 * @(#) ti.sysbios.family.c66; 2, 0, 0, 0,188; 9-7-2012 12:10:40; /db/vtree/library/trees/avala/avala-r15x/src/ xlibrary
443 444 */
445