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37
38 package ti.sysbios.family.c66.tci66xx;
39
40 import xdc.runtime.Error;
41
42 /*!
43 * ======== CpIntc ========
44 * Common Platform Interrupt Controller Manager
45 *
46 * This module manages the CP_INTC hardware. This module supports enabling
47 * and disabling of both system and host interrupts. This module also
48 * supports mapping system interrupts to host interrupts and host interrupts
49 * to Hwis or to the EventCombiner. These functionality are supported
50 * statically and during runtime for CP_INTCs connected to the GEM interrupt
51 * controller but only during runtime for other CP_INTCs. There is a dispatch
52 * function for handling GEM hardware interrupts triggered by a system
53 * interrupt. The Global Enable Register is enabled by default in the module
54 * startup function.
55 *
56 * System interrupts are those interrupts generated by a hardware module
57 * in the system. These interrupts are inputs into CP_INTC.
58 * Host interrupts are the output interrupts of CP_INTC.
59 * There is a one-to-one mapping between channels and host interrupts
60 * therefore, the term "host interrupt" is also used for channels.
61 *
62 * This modules does not support prioritization, nesting, and vectorization.
63 */
64
65 @ModuleStartup
66
67 module CpIntc
68 {
69 /*!
70 * ======== SysIntsView ========
71 * @_nodoc
72 */
73 metaonly struct SysIntsView {
74 UInt systemInt ;
75 UInt8 hostInt;
76 String fxn;
77 String arg;
78 Bool enabled;
79 };
80
81 /*!
82 * ======== rovViewInfo ========
83 * @_nodoc
84 */
85 @Facet
86 metaonly config xdc.rov.ViewInfo.Instance rovViewInfo =
87 xdc.rov.ViewInfo.create({
88 viewMap: [
89 ['SysInts',
90 {
91 type: xdc.rov.ViewInfo.MODULE_DATA,
92 viewInitFxn: 'viewInitSystemInts',
93 structName: 'SysIntsView'
94 }
95 ]
96 ]
97 });
98
99 /*! CpIntc dispatcher function type definition. */
100 typedef Void (*FuncPtr)(UArg);
101
102 /*!
103 * Common Platform Interrupt Controller.
104 */
105 struct RegisterMap {
106 UInt32 REV; /*! 0x00 Revision Register */
107 UInt32 CR; /*! 0x04 Control Register */
108 UInt32 RES_08; /*! 0x08 reserved */
109 UInt32 HCR; /*! 0x0C Host Control Register */
110 UInt32 GER; /*! 0x10 Global Enable Register */
111 UInt32 RES_14; /*! 0x14 reserved */
112 UInt32 RES_18; /*! 0x18 reserved */
113 UInt32 GNLR; /*! 0x1C Global Nesting Level Register */
114 UInt32 SISR; /*! 0x20 Status Index Set Register */
115 UInt32 SICR; /*! 0x24 Status Index Clear Register */
116 UInt32 EISR; /*! 0x28 Enable Index Set Register */
117 UInt32 EICR; /*! 0x2C Enable Index Clear Register */
118 UInt32 GWER; /*! 0x30 Global Wakeup Enable Register */
119 UInt32 HIEISR; /*! 0x34 Host Int Enable Index Set Register */
120 UInt32 HIDISR; /*! 0x38 Host Int Disable Index Set Register */
121 UInt32 RES_3C; /*! 0x3C reserved */
122 UInt32 PPR; /*! 0x40 Pacer Prescale Register */
123 UInt32 RES_44; /*! 0x44 reserved */
124 UInt32 RES_48; /*! 0x48 reserved */
125 UInt32 RES_4C; /*! 0x4C reserved */
126 Ptr *VBR; /*! 0x50 Vector Base Register */
127 UInt32 VSR; /*! 0x54 Vector Size Register */
128 Ptr VNR; /*! 0x58 Vector Null Register */
129 UInt32 RES_5C[9]; /*! 0x5C-0x7C reserved */
130 Int32 GPIR; /*! 0x80 Global Prioritized Index Register */
131 Ptr *GPVR; /*! 0x84 Global Prioritized Vector Register */
132 UInt32 RES_88; /*! 0x88 reserved */
133 UInt32 RES_8C; /*! 0x8C reserved */
134 UInt32 GSIER; /*! 0x90 Global Secure Interrupt Enable Register */
135 UInt32 SPIR; /*! 0x94 Secure Prioritized Index Register */
136 UInt32 RES_98[26]; /*! 0x98-0xFC reserved */
137 UInt32 PPMR[64]; /*! 0x100-0x1FC Pacer Parameter/Map Registers */
138 UInt32 SRSR[32]; /*! 0x200-0x27C Status Raw/Set Registers */
139 UInt32 SECR[32]; /*! 0x280-0x2FC Status Enabled/Clear Registers */
140 UInt32 ESR[32]; /*! 0x300-0x37C Enable Set Registers */
141 UInt32 ECR[32]; /*! 0x380-0x3FC Enable Clear Registers */
142 UInt8 CMR[1024]; /*! 0x400-0x7FC Channel Map Registers */
143 UInt8 HIMR[256]; /*! 0x800-0x8FC Host Interrupt Map Registers */
144 UInt32 HIPIR[256]; /*! 0x900-0xCFC Host Interrupt Pri Index Registers */
145 UInt32 PR[32]; /*! 0xD00-0xD7C Polarity Registers */
146 UInt32 TR[32]; /*! 0xD80-0xDFC Type Registers */
147 UInt32 WER[64]; /*! 0xE00-0xEFC Wakeup Enable Registers */
148 UInt32 DSR[64]; /*! 0xF00-0xFFC Debug Select Registers */
149 UInt32 SER[32]; /*! 0x1000-0x107C Secure Enable Registers */
150 UInt32 SDR[32]; /*! 0x1080-0x10FC Secure Disable Registers */
151 UInt32 HINLR[256]; /*! 0x1100-0x14FC Host Interrupt Nesting Level Registers */
152 UInt32 HIER[8]; /*! 0x1500-0x151F Host Interrupt Enable Registers */
153 UInt32 RES1520[56]; /*! 0x1520-0x15fC Reserved */
154 Ptr *HIPVR[256]; /*! 0x1600-0x19fC Host Interrupt Prioritized Vector */
155 UInt32 RES1A00[384];/*! 0x1A00-0x1FFC Reserved */
156 };
157
158 /*!
159 * System Interrupt Object.
160 */
161 metaonly struct SysIntObj {
162 FuncPtr fxn;
163 UArg arg;
164 UInt8 hostInt;
165 Bool enable;
166 };
167
168 /*!
169 * Error raised when an unplug system interrupt is executed.
170 */
171 config Error.Id E_unpluggedSysInt = {
172 msg: "E_unpluggedSysInt: System Interrupt# %d is unplugged"
173 };
174
175 /*!
176 * ======== sysInts ========
177 * Use for configuring the system interrupts.
178 *
179 * During static configuration this array can be used to configure
180 * the function to execute when a system interrupt is triggered,
181 * the arg to the function, the host interrupt to which the system
182 * interrupt is mapped too, and whether to enable the system interrupt.
183 */
184 metaonly config SysIntObj sysInts[];
185
186 /*!
187 * ======== getEventIdMeta ========
188 * Returns the GEM event id associated with the host interrupt
189 *
190 * If no event id is associated with the host interrupt, the value
191 * -1 will be returned.
192 *
193 * @param(hostInt) host interrupt number
194 */
195 metaonly Int getEventIdMeta(UInt hostInt);
196
197 /*!
198 * ======== mapHostIntToEventCombinerMeta ========
199 * Maps the host interrupt to the Event Combiner.
200 *
201 * The GEM event corresponding to the 'hostInt' in the Event Combiner
202 * will be unmask but the event group will not be dispatched.
203 * The Event Combiner function for this event will be set to the
204 * dispatch function and argument set to 'hostInt'.
205 * The event group must be dispatched from the Event Combiner Module.
206 *
207 * @param(hostInt) host interrupt number
208 */
209 metaonly Void mapHostIntToEventCombinerMeta(UInt hostInt);
210
211 /*!
212 * ======== mapHostIntToHwiMeta ========
213 * Maps the host interrupt to a Hwi.
214 *
215 * A Hwi object will be created with the 'hwiNum', the function
216 * set as the dispatch function and argument set to 'hostInt'.
217 *
218 * @param(hostInt) host interrupt number
219 * @param(hwiNum) Hwi number
220 */
221 metaonly Void mapHostIntToHwiMeta(UInt hostInt, UInt hwiNum);
222
223 /*!
224 * ======== clearSystInt ========
225 * Clears the system interrupt.
226 *
227 * Writes the system interrupt number to the System Interrupt
228 * Status Indexed Clear Register.
229 *
230 * @param(id) Cp_Intc number
231 * @param(sysInt) system interrupt number
232 */
233 Void clearSysInt(UInt id, UInt sysInt);
234
235 /*!
236 * ======== disableAllHostInts ========
237 * Disables all host interrupts.
238 *
239 * Writes a 0 to the Global Enable Register. It does not
240 * override the individual host interrupt enable/disable bits.
241 *
242 * @param(id) Cp_Intc number
243 */
244 Void disableAllHostInts(UInt id);
245
246 /*!
247 * ======== disableHostInt ========
248 * Disables the host interrupts.
249 *
250 * Writes the host interrupt number to the Host Interrupt
251 * Enable Index Clear Register.
252 *
253 * @param(id) Cp_Intc number
254 * @param(hostInt) host interrupt number
255 */
256 Void disableHostInt(UInt id, UInt hostInt);
257
258 /*!
259 * ======== disableSysInt ========
260 * Disables the system interrupt.
261 *
262 * Writes the system interrupt number to the System Interrupt
263 * Enable Indexed Clear Register.
264 *
265 * @param(id) Cp_Intc number
266 * @param(sysInt) system interrupt number
267 */
268 Void disableSysInt(UInt id, UInt sysInt);
269
270 /*!
271 * ======== dispatch ========
272 * The Interrupt service routine handler for CP_INTC events.
273 *
274 * It is used internally, but can also be used by the user.
275 *
276 * @param(hostInt) host interrupt number
277 */
278 Void dispatch(UInt hostInt);
279
280 /*!
281 * ======== dispatchPlug ========
282 * Configures a CpIntc ISR dispatch entry.
283 *
284 * Plugs the function and argument for the specified system interrupt.
285 * Also enables the system interrupt if 'unmask' is set to 'true'.
286 * Function does not map the system interrupt to a Hwi interrupt.
287 *
288 * @param(sysInt) system interrupt number
289 * @param(fxn) function
290 * @param(arg) argument to function
291 * @param(unmask) bool to unmask interrupt
292 */
293 Void dispatchPlug(UInt sysInt, FuncPtr fxn, UArg arg, Bool unmask);
294
295 /*!
296 * ======== enableAllHostInts ========
297 * Enables all host interrupts.
298 *
299 * Writes a 1 to the Global Enable Register. It does not
300 * override the individual host interrupt enable/disable bits.
301 *
302 * @param(id) Cp_Intc number
303 */
304 Void enableAllHostInts(UInt id);
305
306 /*!
307 * ======== enableHostInt ========
308 * Enables the host interrupt.
309 *
310 * Writes the host interrupt number to the Host Interrupt
311 * Enable Indexed Set Register.
312 *
313 * @param(id) Cp_Intc number
314 * @param(hostInt) host interrupt number
315 */
316 Void enableHostInt(UInt id, UInt hostInt);
317
318 /*!
319 * ======== enableSysInt ========
320 * Enables the system interrupt.
321 *
322 * Writes the system interrupt number to the System Interrupt
323 * Enable Indexed Set Register.
324 *
325 * @param(id) Cp_Intc number
326 * @param(sysInt) system interrupt number
327 */
328 Void enableSysInt(UInt id, UInt sysInt);
329
330 /*!
331 * ======== getEventId ========
332 * Returns the event id associated with the host interrupt
333 *
334 * @param(hostInt) host interrupt number
335 */
336 Int getEventId(UInt hostInt);
337
338 /*!
339 * ======== mapSysIntToHostInt ========
340 * Maps a system interrupt to a host interrupt.
341 *
342 * Writes the Channel Map Register to map a system interrupt to a
343 * channel. There is a 1 to 1 mapping between channels and
344 * host interrupts.
345 *
346 * @param(id) Cp_Intc number
347 * @param(sysInt) system interrupt number
348 * @param(hostInt) host interrupt number
349 */
350 Void mapSysIntToHostInt(UInt id, UInt sysInt, UInt hostInt);
351
352 /*!
353 * ======== postSysInt ========
354 * Triggers the system interrupt.
355 *
356 * Writes the system interrupt number to the System Interrupt
357 * Status Index Set Register. Used for diagnostic and test purposes
358 * only.
359 *
360 * @param(id) Cp_Intc number
361 * @param(sysInt) system interrupt number
362 */
363 Void postSysInt(UInt id, UInt sysInt);
364
365 /*!
366 * @_nodoc
367 * ======== unused ========
368 * Unused exists simply to map a call in the Event Combiner dispatcher
369 * calling context to the System_exit calling context (casts UArg to Int)
370 */
371 Void unused(UArg arg);
372
373 internal:
374
375
376 metaonly struct HostIntObj {
377 Int hwiNum;
378 Bool useEventCombiner;
379 };
380
381
382 metaonly config HostIntObj hostInts[];
383
384
385 metaonly config UInt32 baseAddr;
386
387
388 config UInt32 numSysInts;
389
390
391 config Int numStatusRegs;
392
393
394 config UInt8 sysIntToHostInt[];
395
396
397 config UInt8 hostIntToEventId[];
398
399 struct DispatchTabElem {
400 FuncPtr fxn;
401 UArg arg;
402 };
403
404 struct Module_State {
405 volatile RegisterMap *controller[];
406 Bits32 initSIER[];
407 UInt8 hostIntToSysInt[];
408 DispatchTabElem dispatchTab[];
409 };
410 }
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415