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C6x Register Usage

Cortex M3 DSP/BIOS Register Usage

This document provides a table describing the various Cortex M3 targets register conventions in terms of preservation across multi-threaded context switching and preconditions.

Overview

In a multi-threaded application using DSP/BIOS, it is necessary to know which registers can or cannot be modified. Furthermore, users need to understand which registers need to be saved/restored across a function call or an interrupt.

The following definitions describe the various possible register handling behaviors:

• Scratch register. These registers are saved/restored by the Hwi dispatcher with temporary register bit masks.
• Preserved register. These registers are saved/restored during a Task context switch.
• Initialized register. These registers are set to a particular value during Hwi processing and restored to their incoming value upon exiting from the interrupt routine.
• Read-Only register. These registers may be read but must not be modified.
• Global register. These registers are shared across all threads in the system. To make a temporary change, save the register, make the change, and then restore it.
• Other. These registers do not fit into one of the categories above.

Register Conventions

Table 1 Register and Status Bit Handling

Register	Status Bit	Register or Status Bit Name	Type	Notes
R0-R3, R12		General purpose registers	Scratch
R4-R11		General purpose registers	Preserved
R13 (SP_process)		Process Stack pointer	Preserved
R13 (SP_main)		Main Stack pointer	Other	?Set to top of ISR stack buffer at startup. Auto switched to in Hwi threads. Manually switched to in Swi threads.
R14 (LR)		Link Register	Preserved
xPSR		Program Status Register
	N,Z,C,V	Condition Codes	Scratch
	Q	Overflow	Scratch
	ICI	Interrupt-continuable instruction	Read-Only
	IT	IF-Then bits	Read-Only
	T	Thumb	Other	Always set
	ISRNUM	ISR Number	Read-Only	?
CONTROL		Control Register	Other	Used to manually force main/process stack switching
PRIMASK		Configurable Exception Mask Register	Other	Untouched
FAULTMASK		Fault Prioirty Set Register	Other	Untouched
BASEPRI		Base Priority Register	Other	Hwi_enable/disable/restore manipulate this register to manage maskable interrupts

Notes:

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