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32 33 34 35
36 requires ti.sysbios.interfaces;
37
38 /*!
39 * ======== ti.sysbios.family.arm.ducati ========
40 * Contains specifications for the Ducati device-specific SYS/BIOS functions.
41 *
42 * The two M3 cores share a number of hardware and software resources.
43 *
44 * The system software must carefully manage these resources when the
45 * dynamic loading of applications is required.
46 *
47 * Below is a list of the shared resources that SYS/BIOS modules utilize and
48 * manage.
49 *
50 * Shared resources:
51 *
52 * AMMU
53 * @p(blist)
54 * -Must be configured before unicache is enabled.
55 * -Must have a page descriptor for EVERY memory address
56 * accessed by either core before unicache is enabled.
57 * -AMMU is configured statically, no runtime APIs to modify
58 * the AMMU configuration are provided.
59 * -Initialization is controlled by the
60 * {@link ti.sysbios.hal.ammu.AMMU#configureAmmu AMMU.configureAmmu} flag.
61 * -By default, this flag is true.
62 * @p
63 *
64 * Unicache
65 * @p(blist)
66 * -Must be configured and enabled.
67 * -Runtime APIs use GateDualCore[0] to arbitrate shared unicache
68 * register usage.
69 * -Initialization is controlled by the
70 * {@link ti.sysbios.hal.unicache.Cache#configureCache Cache.configureCache} flag.
71 * -By default this flag is false.
72 * @p
73 *
74 * CTM 2,3,4,5 used for timestamping
75 * @p(blist)
76 * -These counters are initialized by the
77 * {@link TimestampProvider TimestampProvider} module, which
78 * is used by the {@link xdc.runtime.Timestamp} module to provide
79 * timestamp services.
80 * -Must be configured and started.
81 * -Configured and started by whichever core comes up first
82 * and detects (by testing register contents) that the CTM
83 * hasn't been configured and started.
84 * @p
85 *
86 * Reset Exception vector table (vectors 0-14)
87 * @p(blist)
88 * -The address of the Reset Exception vector table is shared by
89 * both cores.
90 * -Vectors 0 and 1 at addresses 0x0 are fetched each time
91 * a core is reset. At that time they must contain the SP and
92 * address of c_int00 for the core being reset.
93 * -Exception vectors 2-14 are used by each core until it has
94 * successfully configured its NVIC's Vector Table Offset Register (VTOR)
95 * to point to the vector table that will be used afterwards.
96 * -The Reset Exception vectors are required to be valid and unique
97 * to the core being reset in case an exception occurs prior to the
98 * VTOR being configured.
99 * -The Reset Exception vector table placement is controlled by the
100 * {@link ti.sysbios.family.arm.m3.Hwi#resetVectorAddress Hwi.resetVectorAddress}
101 * config parameter.
102 * -By default, both cores place their Reset Exception vector table
103 * at 0x00000000.
104 * -It is left to the system software design to guarantee
105 * that only one core is climbing up at a time.
106 * @p
107 *
108 * Runtime Exception and Interrupt vector table (vectors 0-79)
109 * @p(blist)
110 * -The address of the Runtime Exception and Interrupt vector table
111 * should be unique to each core.
112 * -The Runtime Exception and Interrupt vector table
113 * placement is controlled by the
114 * {@link ti.sysbios.family.arm.m3.Hwi#vectorTableAddress Hwi.vectorTableAddress}
115 * config parameter.
116 * -Default behavior is that core 0 places its runtime vector table
117 * at 0x400 and core 1 places its runtime vector table at 0x800.
118 * @p
119 *
120 * GateDualCore[0] is used by the unicache module.
121 * GateDualCore[1-n] can be used by applications to manage shared hardware/software resources
122 * @p(blist)
123 * -Initialization is controlled by the
124 * {@link GateDualCore#initGates GateDualCore.initGates} flag.
125 * -By default, core 0 initializes the gate objects.
126 * @p
127 *
128 */
129 package ti.sysbios.family.arm.ducati [2,0,0,0] {
130 module Core;
131 module CTM;
132 module GateDualCore;
133 module Timer;
134 module TimerSupport;
135 module TimestampProvider;
136 module Wugen;
137 }
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142