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37
38 package ti.sysbios.family.arm.ducati.omap4430;
39
40 import ti.sysbios.family.arm.ducati.GateDualCore;
41
42 /*!
43 * ======== Power ========
44 * Power support for Ducati on OMAP4430.
45 */
46 module Power
47 {
48 /*! Suspend arguments structure. */
49 struct SuspendArgs {
50 Bool pmMasterCore; /*! Master core for suspend/resume? */
51 Bool rendezvousResume; /*! Rendezvous before resume? */
52 Int dmaChannel; /*! SDMA channel for L2 RAM save; -1=CPU copy */
53 UInt intMask31_0; /*! Mask of interrupts (31-0) able to wake WFI */
54 UInt intMask63_32; /*! Mask of interrupts (63-32) able to wake WFI */
55 UInt intMask79_64; /*! Mask of interrupts (79-64) able to wake WFI */
56 };
57
58 /*! Physical address of L2 RAM */
59 const Ptr L2RAM = 0x55020000;
60
61 /*! Base address of SDMA registers */
62 config Ptr sdmaRegs = 0x4A056000;
63
64 /*! Rendezvous Gate index */
65 config UInt rendezvousGateIndex = 1;
66
67 /*! Idle the CPU when threads blocked waiting for an interrupt? */
68 config Bool idle = false;
69
70 /*! Segment to load Power's shared reset code and data */
71 metaonly config String loadSegment = "EXT_SHARED_RAM";
72
73 /*!
74 * ======== idleCPU ========
75 * Function used to automatically idle the CPU in the Idle loop.
76 *
77 * When the 'idle' configuration parameter is set, this function will
78 * be added to the list of Idle loop functions. When called from the
79 * Idle loop, it will invoke the wait for interrupt (WFI) instruction,
80 * to idle the CPU until the next interrupt occurs.
81 */
82 @DirectCall
83 Void idleCPU();
84
85 /*!
86 * ======== suspend ========
87 * Function used for suspend/resume of the M3 cores.
88 *
89 * Precondition and usage constraints:
90 *
91 * 1) Before this function is called the application must disable all
92 * interrupts that are not desired to wake the CPU from WFI while
93 * waiting for the core domain to go off.
94 *
95 * 2) For those interrupts that are desired to wake the CPU from WFI (for
96 * example, the mailbox interrupt), these interrupts cannot be generated
97 * until the Power_suspend API has reached the point of executing WFI.
98 * If the interrupts happen early, while this API is saving context,
99 * the resulting context may be stale, and the application may not
100 * resume correctly. Two global flags (one for each M3 core) are
101 * assert immediately before invoking WFI; the wakeup interrupts
102 * should not be asserted until these flags are asserted (non-zero):
103 * ti_sysbios_family_arm_ducati_omap4430_readyIdleCore0
104 * ti_sysbios_family_arm_ducati_omap4430_readyIdleCore1
105 */
106 @DirectCall
107 UInt suspend(SuspendArgs * args);
108
109 internal:
110
111 struct Struct8 {
112 UInt32 a0;
113 UInt32 a1;
114 UInt32 a2;
115 UInt32 a3;
116 UInt32 a4;
117 UInt32 a5;
118 UInt32 a6;
119 UInt32 a7;
120 }
121
122 struct Struct10 {
123 UInt32 a0;
124 UInt32 a1;
125 UInt32 a2;
126 UInt32 a3;
127 UInt32 a4;
128 UInt32 a5;
129 UInt32 a6;
130 UInt32 a7;
131 UInt32 a8;
132 UInt32 a9;
133 }
134
135 struct TablePIDS {
136 UInt32 PID1;
137 UInt32 PID2;
138 }
139
140 struct IPRxRegs {
141 UInt32 IPR0;
142 UInt32 IPR1;
143 UInt32 IPR2;
144 UInt32 IPR3;
145 UInt32 IPR4;
146 UInt32 IPR5;
147 UInt32 IPR6;
148 UInt32 IPR7;
149 UInt32 IPR8;
150 UInt32 IPR9;
151 UInt32 IPR10;
152 UInt32 IPR11;
153 UInt32 IPR12;
154 UInt32 IPR13;
155 UInt32 IPR14;
156 UInt32 IPR15;
157 }
158
159 struct CfgRegs {
160 UInt32 VTOR;
161 UInt32 AIRCR;
162 UInt32 SCR;
163 UInt32 CCR;
164 UInt32 SHPR0;
165 UInt32 SHPR4;
166 UInt32 SHPR8;
167 UInt32 SHCSR;
168 }
169
170 struct NVICContext {
171 UInt32 AUXCTRL;
172 UInt32 STCSR;
173 UInt32 STRVR;
174 UInt32 ISER0;
175 UInt32 ISER1;
176 IPRxRegs iprRegs;
177 CfgRegs cfgRegs;
178 }
179
180 struct ContextAMMU {
181 UInt32 largeAddr[4];
182 UInt32 largeXlteAddr[4];
183 UInt32 largePolicy[4];
184 UInt32 medAddr[2];
185 UInt32 medXlteAddr[2];
186 UInt32 medPolicy[2];
187 Struct10 smallAddr;
188 Struct10 smallXlteAddr;
189 Struct10 smallPolicy;
190 UInt32 mmuConfig;
191 }
192
193 struct ContextCTM {
194 UInt32 CNTL;
195 UInt32 STMCNTL;
196 UInt32 STMMSTID;
197 UInt32 STMINTVL;
198 UInt32 STMSEL0;
199 UInt32 TINTVLR0;
200 UInt32 TINTVLR1;
201 UInt32 GNBL0;
202 Struct8 control;
203 }
204
205 struct CpuRegs {
206 UInt32 R4;
207 UInt32 R5;
208 UInt32 R6;
209 UInt32 R7;
210 UInt32 R8;
211 UInt32 R9;
212 UInt32 R10;
213 UInt32 R11;
214 UInt32 LR;
215 UInt32 CONTROL;
216 UInt32 BASEPRI;
217 UInt32 MSP;
218 UInt32 pSP;
219 }
220
221 struct PrivateContext {
222 CpuRegs privateCPU;
223 NVICContext privateNVIC;
224 TablePIDS privatePIDS;
225 }
226
227 struct UnicacheConfig {
228 UInt32 L1_CONFIG;
229 UInt32 L1_OCP;
230 }
231
232 struct SubsystemContext {
233 UnicacheConfig cacheConfig;
234 ContextAMMU ammuConfig;
235 ContextCTM ctmConfig;
236 }
237
238 struct DucatiContext {
239 PrivateContext masterContext;
240 PrivateContext slaveContext;
241 SubsystemContext ssContext;
242 }
243
244 struct SdmaRegs {
245 volatile UInt32 CCR;
246 UInt32 CLNK;
247 UInt32 CICR;
248 UInt32 CSR;
249 UInt32 CSDP;
250 UInt32 CEN;
251 UInt32 CFN;
252 UInt32 CSSA;
253 UInt32 CDSA;
254 UInt32 CSEI;
255 UInt32 CSFI;
256 UInt32 CDEI;
257 UInt32 CDFI;
258 }
259
260 /*! Rendezvous Gate handle */
261 config GateDualCore.Handle rendezvousGate;
262
263 /*!
264 * ======== resetFxn ========
265 * Function used for resume upon reset of M3 cores.
266 */
267 Void resetFxn();
268
269 /*!
270 * ======== saveCpuRegs ========
271 * Function used to save parent-preserved CPU register context, assert
272 * ready to idle flag, and invoke WFI.
273 */
274 UInt32 saveCpuRegs(Ptr saveAddress, Ptr readyFlag);
275
276 }
277
278 279 280 281
282