1 /* 2 * Copyright (c) 2012, Texas Instruments Incorporated 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * */ 32 /* 33 * ======== Core.xdc ======== 34 * 35 */ 36 37 package ti.sysbios.family.arm.ducati; 38 39 import xdc.runtime.Error; 40 41 /*! 42 * ======== Core ======== 43 * Core Identification Module. 44 * 45 * The Core module is used to define which core within a dual core 46 * "Ducati" subsystem an application is being built for. 47 * 48 * At runtime, a comparison is made between the configured Core.id 49 * and the value of PID0 (at address 0xe00fffe0). If they do not 50 * agree, an Error is raised. 51 * 52 * Use of this module has the side effect of configuring default 53 * interrupt vector table placements for Core 0 and Core 1 if 54 * they haven't already been specified by the 55 * {@link ti.sysbios.family.arm.m3.Hwi#vectorTableAddress Hwi.vectorTableAddress} 56 * config parameter. 57 * 58 * Core 0's default vector table placement is at 0x400. 59 * 60 * Core 1's default vector table placement is at 0x800. 61 */ 62 63 @ModuleStartup /* to configure static timers */ 64 65 module Core 66 { 67 /*! 68 * Ducati Core ID, default is Core 0 69 * 70 * Used for making static decisions based on Core ID 71 */ 72 config UInt id = 0; 73 74 /*! 75 * Error raised if Core.id does not match the contents 76 * of PID0 (at 0xE00FFFE0). 77 */ 78 config Error.Id E_mismatchedIds = { 79 msg: "E_mismatchedIds: Core_Id: %d does not match hardware core Id: %d" 80 }; 81 82 /*! 83 * ======== getId ======== 84 * Reads M3 core ID (0 or 1). 85 * 86 * Used for making dynamic decisions based on Core ID 87 * 88 * @b(returns) core ID 89 */ 90 @Macro 91 UInt getId(); 92 } 93 94 /* 95 * @(#) ti.sysbios.family.arm.ducati; 2, 0, 0, 0,292; 2-24-2012 11:39:26; /db/vtree/library/trees/avala/avala-q28x/src/ xlibrary 96 97 */ 98