module ti.sysbios.family.arm.arm9.Mmu |
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Memory Management Unit Manager
This module allows the ARM processor to map a virtual address to a
different physical address and enable/disable the MMU. It does this
through a translation table in memory. The translation table is
16KB and manages only the first level descriptor table. Each entry
in the table defines the properties of memory areas of size 1MB.
These properties include memory access permissions, cacheability,
bufferability, and domain access.
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#include <ti/sysbios/family/arm/arm9/Mmu.h>
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Bool | |
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Functions common to all target modules |
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Typedefs |
typedef enum | |
typedef struct | |
Constants |
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extern const Bool | |
DETAILS
This module allows the ARM processor to map a virtual address to a
different physical address and enable/disable the MMU. It does this
through a translation table in memory. The translation table is
16KB and manages only the first level descriptor table. Each entry
in the table defines the properties of memory areas of size 1MB.
These properties include memory access permissions, cacheability,
bufferability, and domain access.
By default, the MMU translation table contains cache-enabled entries
for every memory segment from the platform.
Cache-disabled entries are added the peripheral
addresses used by SYS/BIOS (i.e. Timers, Interrupt controller).
The translation table is placed in
an output section called "ti.sysbios.family.arm.arm9.mmuTableSection".
This section is placed into the platform's default dataMemory and
specified to not be initialized via the "NOINIT" type. If
cacheable is true and bufferable is true, L1 data cache operates as
a write-back cache. If cacheable is true but bufferable is false,
L1 data cache operates as a write-through cache.
This module does not manage the second level descriptor tables.
A 'SECTION' mapped access requires only a first level fetch. In
this case, there is no need for a second level descriptor table.
A 'COARSE' or 'FINE' mapped access requires a second level
descriptor table which can be supplied by the user.
Note: There are size and alignment requirements on the second
level descriptor tables depending on the page size.
See the ARM Architecture Reference Manual for more info.
The following is an example of how to place the MMU table
and how to enable L1 data caching for the address range
0xC3000000-0xC4000000 in the *.cfg file:
var Cache = xdc.useModule('ti.sysbios.family.arm.arm9.Cache');
var Mmu = xdc.useModule('ti.sysbios.family.arm.arm9.Mmu');
// Enable the cache
Cache.enableCache = true;
// Enable the MMU (Required for L1 data caching)
Mmu.enableMMU = true;
// descriptor attribute structure
var attrs = {
type: Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
bufferable: true, // bufferable
cacheable: true, // cacheable
imp: 1, // implementation defined
domain: 0, // domain between 0-15
accPerm: 3, // read/write permission
};
// Set the descriptor for each entry in the address range
for (var i=0xC3000000; i < 0xC4000000; i = i + 0x00100000) {
// Each 'SECTION' descriptor entry spans a 1MB address range
Mmu.setFirstLevelDescMeta(i, i, attrs);
}
var memmap = Program.cpu.memoryMap;
var DDR = null;
// Find DDR in memory map
for (var i=0; i < memmap.length; i++) {
if (memmap[i].name == "DDR") {
DDR = memmap[i];
}
}
// Place the MMU table in the DDR memory segment if it exists
if (DDR != null) {
var sectionName = "ti.sysbios.family.arm.arm9.mmuTableSection";
Program.sectMap[sectionName] = new Program.SectionSpec();
Program.sectMap[sectionName].type = "NOINIT";
Program.sectMap[sectionName].loadSegment = "DDR";
}
else {
print("No DDR memory segment was found");
}
The following is an example of using a second level descriptor
to specify a 4KB block of memory. The first level descriptor
is specified as a COARSE page table. The second level descriptors
are specified as a small page, cacheable, and bufferable for the
addresses 0xFFFEE000-0xFFFF0000. This code is be placed in main()
in the *.c file. The MMU should not be enabled prior to initializing
the second level descriptors.
#define MMU_LEVEL2DESC_SMALLPAGE 0x2
#define MMU_LEVEL2DESC_BUFFERABLE 0x4
#define MMU_LEVEL2DESC_CACHEABLE 0x8
#pragma DATA_ALIGN(mmuL2Table, 4096); // align to 4KB
UInt32 mmuL2Table[256]; // each level 2 descriptor specifies a 4KB block
Void main(Int argc, Char * argv[])
{
Mmu_FirstLevelDescAttrs attrs;
Int i;
// initialize the second level descriptors
for (i=0; i < 256; i++) {
mmuL2Table[i] = 0;
}
// change the address starting at 0xFFFEE000 to be a small page
mmuL2Table[0xEE] = 0xFFFEE000 | // set the physical address
MMU_LEVEL2DESC_SMALLPAGE | // set descriptor to small page (4KB)
0xFF0; // set Access Permission bits to 1
// change the address starting at 0xFFFEF000 to be a small page
mmuL2Table[0xEF] = 0xFFFEF000 | // set the physical address
MMU_LEVEL2DESC_SMALLPAGE | // set descriptor to small page (4KB)
0xFF0; // set Access Permission bits to 1
// change the address starting at 0xFFFF0000 to be a small page
mmuL2Table[0xF0] = 0xFFFF0000 | // set the physical address
MMU_LEVEL2DESC_SMALLPAGE | // set descriptor to small page (4KB)
MMU_LEVEL2DESC_CACHEABLE | // set cacheable bit to true
MMU_LEVEL2DESC_BUFFERABLE | // set bufferable bit to true
0xFF0; // set Access Permission bits to 1
// first level descriptor properties
attrs.type = Mmu_FirstLevelDesc_COARSE; // set to a coarse descriptor
attrs.imp = 1; // defined to be 1 for ARM9
attrs.domain = 0; // set domain to 0
// Set the first level descriptor for the virtual address 0xFFFF0000.
Mmu_setFirstLevelDesc((Ptr)0xFFFF0000, &mmuL2Table, &attrs);
// enable MMU
Mmu_enable();
BIOS_start();
}
enum Mmu_FirstLevelDesc |
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First Level descriptors
typedef enum Mmu_FirstLevelDesc {
Mmu_FirstLevelDesc_FAULT,
// Virtual address is unmapped
Mmu_FirstLevelDesc_COARSE,
// Coarse page table descriptor
Mmu_FirstLevelDesc_SECTION,
// Section descriptor
Mmu_FirstLevelDesc_FINE
// Fine page table descriptor
} Mmu_FirstLevelDesc;
struct Mmu_FirstLevelDescAttrs |
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Structure for setting first level descriptor entries
typedef struct Mmu_FirstLevelDescAttrs {
// first level descriptor type
Bool bufferable;
// is memory section bufferable
Bool cacheable;
// is memory section cacheable
UInt8 imp;
// implementation defined
UInt8 domain;
// domain access control value 0-15
UInt8 accPerm;
// access permission bits value 0-3
} Mmu_FirstLevelDescAttrs;
DETAILS
See the 'Translation Tables' section of the ARM Architecture
Reference Manual for details
config Mmu_A_nullPointer // module-wide |
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Assert raised when a pointer is null
config Mmu_A_unknownDescType // module-wide |
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Assert raised when the descriptor type is not recognized
extern const Assert_Id Mmu_A_unknownDescType;
config Mmu_defaultAttrs // module-wide |
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default descriptor attributes structure
config Mmu_enableMMU // module-wide |
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Configuration parameter to enable MMU
extern const Bool Mmu_enableMMU;
Mmu_disable() // module-wide |
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Disables the MMU
DETAILS
If the MMU is already disabled, then simply return.
Otherwise this function does the following:
If the L1 data cache is enabled, write back invalidate all
of L1 data cache. If the L1 program cache is enabled,
invalidate all of L1 program cache. This function does not
change the cache L1 data/program settings.
Mmu_enable() // module-wide |
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Enables the MMU
DETAILS
If the MMU is already enabled, then simply return.
Otherwise this function does the following:
If the L1 program cache is enabled, invalidate all of L1
program cache. This function does not change the L1
data/program cache settings.
Mmu_initDescAttrs() // module-wide |
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Initializes the first level descriptor attribute structure
ARGUMENTS
attrs
Pointer to first level descriptor attribute struct
Mmu_isEnabled() // module-wide |
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Determines if the MMU is enabled
Mmu_setFirstLevelDesc() // module-wide |
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Sets the descriptor for the virtual address
ARGUMENTS
virtualAddr
The modified virtual address
phyAddr
The physical address
attrs
Pointer to first level descriptor attribute struct
DETAILS
The first level table entry for the virtual address is mapped
to the physical address with the attributes specified. The
descriptor table is effective when the MMU is enabled.
Module-Wide Built-Ins |
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// Get this module's unique id
Bool Mmu_Module_startupDone();
// Test if this module has completed startup
// The heap from which this module allocates memory
Bool Mmu_Module_hasMask();
// Test whether this module has a diagnostics mask
Bits16 Mmu_Module_getMask();
// Returns the diagnostics mask for this module
Void Mmu_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module
var Mmu = xdc.useModule('ti.sysbios.family.arm.arm9.Mmu');
module-wide constants & types
module-wide config parameters
msg: "A_nullPointer: Pointer is null"
};
msg: "A_unknownDescType: Descriptor type is not recognized"
};
bufferable: false,
cacheable: false,
imp: 1,
domain: 0,
accPerm: 3
};
module-wide functions
enum Mmu.FirstLevelDesc |
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First Level descriptors
XDCscript usage |
meta-domain |
values of type Mmu.FirstLevelDesc
const Mmu.FirstLevelDesc_FAULT;
// Virtual address is unmapped
const Mmu.FirstLevelDesc_COARSE;
// Coarse page table descriptor
const Mmu.FirstLevelDesc_SECTION;
// Section descriptor
const Mmu.FirstLevelDesc_FINE;
// Fine page table descriptor
C SYNOPSIS
struct Mmu.FirstLevelDescAttrs |
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Structure for setting first level descriptor entries
XDCscript usage |
meta-domain |
var obj = new Mmu.FirstLevelDescAttrs;
// first level descriptor type
obj.bufferable = Bool ...
// is memory section bufferable
obj.cacheable = Bool ...
// is memory section cacheable
obj.imp = UInt8 ...
// implementation defined
obj.domain = UInt8 ...
// domain access control value 0-15
obj.accPerm = UInt8 ...
// access permission bits value 0-3
DETAILS
See the 'Translation Tables' section of the ARM Architecture
Reference Manual for details
C SYNOPSIS
config Mmu.A_nullPointer // module-wide |
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Assert raised when a pointer is null
XDCscript usage |
meta-domain |
msg: "A_nullPointer: Pointer is null"
};
C SYNOPSIS
config Mmu.A_unknownDescType // module-wide |
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Assert raised when the descriptor type is not recognized
XDCscript usage |
meta-domain |
msg: "A_unknownDescType: Descriptor type is not recognized"
};
C SYNOPSIS
config Mmu.defaultAttrs // module-wide |
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default descriptor attributes structure
XDCscript usage |
meta-domain |
bufferable: false,
cacheable: false,
imp: 1,
domain: 0,
accPerm: 3
};
C SYNOPSIS
config Mmu.enableMMU // module-wide |
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Configuration parameter to enable MMU
XDCscript usage |
meta-domain |
Mmu.enableMMU = Bool true;
C SYNOPSIS
metaonly config Mmu.cachePlatformMemory // module-wide |
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Flag to automatically mark platform's code/data/stack memory as
cacheable in MMU descriptor table
XDCscript usage |
meta-domain |
Mmu.cachePlatformMemory = Bool true;
DETAILS
By default, all memory regions defined in the platform an
application is built with are marked as cacheable.
If manual configuration of memory regions is required, set
this config parameter to 'false'.
SEE
metaonly config Mmu.common$ // module-wide |
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Common module configuration parameters
XDCscript usage |
meta-domain |
DETAILS
All modules have this configuration parameter. Its name
contains the '$' character to ensure it does not conflict with
configuration parameters declared by the module. This allows
new configuration parameters to be added in the future without
any chance of breaking existing modules.
metaonly config Mmu.rovViewInfo // module-wide |
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XDCscript usage |
meta-domain |
metaonly Mmu.setFirstLevelDescMeta() // module-wide |
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Statically sets the descriptor for the virtual address
XDCscript usage |
meta-domain |
ARGUMENTS
virtualAddr
The modified virtual address
phyAddr
The physical address
attrs
Pointer to first level descriptor attribute struct
DETAILS
The first level table entry for the virtual address is mapped
to the physical address with the attributes specified. The
descriptor table is effective when the MMU is enabled.
generated on Thu, 01 Mar 2012 16:57:34 GMT