1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
32 33 34 35
36 package ti.sysbios.family.arm.a8.intcps;
37
38 import xdc.rov.ViewInfo;
39
40 import xdc.runtime.Diags;
41 import xdc.runtime.Log;
42 import xdc.runtime.Error;
43
44 import ti.sysbios.BIOS;
45 import ti.sysbios.interfaces.IHwi;
46
47 /*!
48 * ======== Hwi ========
49 * Hardware Interrupt Support Module.
50 *
51 * This Hwi module provides ARM family-specific implementations of the
52 * APIs defined in {@link ti.sysbios.interfaces.IHwi IHwi}.
53 *
54 * Additional ARM device-specific APIs are also provided.
55 *
56 * @a(NOTE)
57 * In this Hwi module implementation, the instance config parameter value
58 * {@link #MaskingOption_LOWER} is equivalent to {@link #MaskingOption_SELF}.
59 * Statically configuring a Hwi object's {@link #Params.maskSetting} to
60 * {@link #MaskingOption_LOWER} will result in the generation of a benign
61 * build warning. Dynamic usages of {@link #MaskingOption_LOWER} will be
62 * silently converted to {@link #MaskingOption_SELF}.
63 *
64 */
65
66 @Template("./Hwi.xdt")
67 @ModuleStartup
68
69 module Hwi inherits ti.sysbios.interfaces.IHwi
70 {
71
72
73
74 /*! intcps supports 128 interrupts. */
75 const Int NUM_INTERRUPTS = 128;
76
77
78
79 /*! Hwi vector function type definition. */
80 typedef Void (*VectorFuncPtr)(void);
81
82 /*!
83 * ======== BasicView ========
84 * @_nodoc
85 */
86 metaonly struct BasicView {
87 Ptr halHwiHandle;
88 String label;
89 Int intNum;
90 UInt priority;
91 String fxn;
92 UArg arg;
93 };
94
95 /*!
96 * ======== DetailedView ========
97 * @_nodoc
98 */
99 metaonly struct DetailedView {
100 Ptr halHwiHandle;
101 String label;
102 Int intNum;
103 UInt priority;
104 String fxn;
105 UArg arg;
106 Ptr irp;
107 Bool enabled;
108 Bool pending;
109 };
110
111 /*!
112 * ======== ModuleView ========
113 * @_nodoc
114 */
115 metaonly struct ModuleView {
116 String options[4];
117 UInt spuriousInterrupts;
118 UInt lastSpuriousInterrupt;
119 SizeT hwiStackPeak;
120 SizeT hwiStackSize;
121 Ptr hwiStackBase;
122 };
123
124 /*!
125 * ======== rovViewInfo ========
126 * @_nodoc
127 */
128 @Facet
129 metaonly config ViewInfo.Instance rovViewInfo =
130 ViewInfo.create({
131 viewMap: [
132 ['Basic', {type: ViewInfo.INSTANCE, viewInitFxn: 'viewInitBasic', structName: 'BasicView'}],
133 ['Detailed', {type: ViewInfo.INSTANCE, viewInitFxn: 'viewInitDetailed', structName: 'DetailedView'}],
134 ['Module', {type: ViewInfo.MODULE, viewInitFxn: 'viewInitModule', structName: 'ModuleView'}]
135 ]
136 });
137
138 /*! Interrupt type. IRQ or FIQ */
139 enum Type {
140 Type_IRQ, /*! IRQ interrupt. */
141 Type_FIQ /*! FIQ interrupt. */
142 };
143
144 /*! Interrupt Controller. Symbol "Hwi_intc" is physical device */
145 struct Intc {
146 UInt32 REVISION; /*! 0x00 Config Register */
147
148 UInt32 hole0[3]; /*! 0x04-0x0C */
149
150 UInt32 SYSCONFIG; /*! 0x10 Config Register */
151 UInt32 SYSSTATUS; /*! 0x14 Status Register */
152
153 UInt32 hole1[10]; /*! 0x18-0x3c */
154
155 UInt32 SIR_IRQ; /*! 0x40 Source IRQ Register */
156 UInt32 SIR_FIQ; /*! 0x44 Source FIQ Register */
157 UInt32 CONTROL; /*! 0x48 Control Register */
158 UInt32 PROTECTION; /*! 0x4C Protection Register */
159 UInt32 IDLE; /*! 0x50 Idle Register */
160
161 UInt32 hole2[3]; /*! 0x54-0x5C */
162
163 UInt32 IRQ_PRIORITY; /*! 0x60 IRQ Priority Register */
164 UInt32 FIQ_PRIORITY; /*! 0x64 IRQ Priority Register */
165 UInt32 THRESHOLD; /*! 0x68 Threshold Register */
166
167 UInt32 hole3[5]; /*! 0x6C-0x7C */
168
169 UInt32 ITR0; /*! 0x80 Interrupt Input Register */
170 UInt32 MIR0; /*! 0x84 Mask Interrupt Register */
171 UInt32 MIR_CLEAR0; /*! 0x88 MIR Clear Register */
172 UInt32 MIR_SET0; /*! 0x8C MIR Set Register */
173 UInt32 ISR_SET0; /*! 0x90 Interrupt Set Register */
174 UInt32 ISR_CLEAR0; /*! 0x94 Interrupt Clear Register */
175 UInt32 PENDING_IRQ0; /*! 0x98 Pending IRQ Register */
176 UInt32 PENDING_FIQ0; /*! 0x9C Pending FIQ Register */
177
178 UInt32 ITR1; /*! 0xA0 Interrupt Input Register */
179 UInt32 MIR1; /*! 0xA4 Mask Interrupt Register */
180 UInt32 MIR_CLEAR1; /*! 0xA8 MIR Clear Register */
181 UInt32 MIR_SET1; /*! 0xAC MIR Set Register */
182 UInt32 ISR_SET1; /*! 0xB0 Interrupt Set Register */
183 UInt32 ISR_CLEAR1; /*! 0xB4 Interrupt Clear Register */
184 UInt32 PENDING_IRQ1; /*! 0xB8 Pending IRQ Register */
185 UInt32 PENDING_FIQ1; /*! 0xBC Pending FIQ Register */
186
187 UInt32 ITR2; /*! 0xC0 Interrupt Input Register */
188 UInt32 MIR2; /*! 0xC4 Mask Interrupt Register */
189 UInt32 MIR_CLEAR2; /*! 0xC8 MIR Clear Register */
190 UInt32 MIR_SET2; /*! 0xCC MIR Set Register */
191 UInt32 ISR_SET2; /*! 0xD0 Interrupt Set Register */
192 UInt32 ISR_CLEAR2; /*! 0xD4 Interrupt Clear Register */
193 UInt32 PENDING_IRQ2; /*! 0xD8 Pending IRQ Register */
194 UInt32 PENDING_FIQ2; /*! 0xDC Pending FIQ Register */
195
196 UInt32 ITR3; /*! 0xE0 Interrupt Input Register */
197 UInt32 MIR3; /*! 0xE4 Mask Interrupt Register */
198 UInt32 MIR_CLEAR3; /*! 0xE8 MIR Clear Register */
199 UInt32 MIR_SET3; /*! 0xEC MIR Set Register */
200 UInt32 ISR_SET3; /*! 0xF0 Interrupt Set Register */
201 UInt32 ISR_CLEAR3; /*! 0xF4 Interrupt Clear Register */
202 UInt32 PENDING_IRQ3; /*! 0xF8 Pending IRQ Register */
203 UInt32 PENDING_FIQ3; /*! 0xFC Pending FIQ Register */
204
205 UInt32 ILR[128]; /*! 0x100 thru 0x2FC */
206 };
207
208 extern volatile Intc intc;
209
210 /*!
211 * Exception Context - Register contents at the time of an exception.
212 */
213 struct ExcContext {
214
215 BIOS.ThreadType threadType;
216
217 Ptr threadHandle;
218
219 Ptr threadStack;
220
221
222
223
224 Ptr r0;
225 Ptr r1;
226 Ptr r2;
227 Ptr r3;
228 Ptr r4;
229 Ptr r5;
230 Ptr r6;
231 Ptr r7;
232 Ptr r8;
233 Ptr r9;
234 Ptr r10;
235 Ptr r11;
236 Ptr r12;
237 Ptr sp;
238 Ptr lr;
239 Ptr pc;
240 Ptr psr;
241 }
242
243
244
245 /*! Reset Handler. Default is c_int00 */
246 metaonly config VectorFuncPtr resetFunc;
247
248 /*!
249 * Undefined instruction exception handler.
250 * Default is an internal exception handler.
251 */
252 metaonly config VectorFuncPtr undefinedInstFunc;
253
254 /*!
255 * SWI Handler. Default is internal SWI handler.
256 * Default is an internal exception handler.
257 */
258 metaonly config VectorFuncPtr swiFunc;
259
260 /*!
261 * Prefetch abort exception handler.
262 * Default is an internal exception handler.
263 */
264 metaonly config VectorFuncPtr prefetchAbortFunc;
265
266 /*!
267 * Data abort exception handler.
268 * Default is an internal exception handler.
269 */
270 metaonly config VectorFuncPtr dataAbortFunc;
271
272 /*!
273 * Reserved exception handler.
274 * Default is an internal exception handler.
275 */
276 metaonly config VectorFuncPtr reservedFunc;
277
278 /*! IRQ interrupt handler. Default is internal IRQ dispatcher */
279 metaonly config VectorFuncPtr irqFunc;
280
281 /*! FIQ interrupt handler. Default is internal FIQ dispatcher */
282 metaonly config VectorFuncPtr fiqFunc;
283
284 /*!
285 * Enable full exception decoding
286 *
287 * When this is enabled, the exception handler will fully
288 * decode an exception and dump the registers to the
289 * system console.
290 */
291 metaonly config Bool enableException = false;
292
293 /*!
294 * FIQ stack pointer. Default = null.
295 * (Indicates that stack is to be created internally)
296 */
297 config Ptr fiqStack = null;
298
299 /*!
300 * FIQ stack size in MAUs.
301 * Default is 1024 bytes.
302 */
303 metaonly config SizeT fiqStackSize = 1024;
304
305 /*!
306 * Memory section used for FIQ stack
307 * Default is null.
308 */
309 metaonly config String fiqStackSection = null;
310
311 /*!
312 * Exception stack pointer. Default = null.
313 * (Indicates that stack is to be created internally)
314 */
315 config Ptr excStack = null;
316
317 /*!
318 * Exception stack size in MAUs.
319 * Default is 1024 bytes.
320 */
321 metaonly config SizeT excStackSize = 1024;
322
323 /*!
324 * Memory section used for Exception stack
325 * Default is null.
326 */
327 metaonly config String excStackSection = null;
328
329 /*! Initial MIR0 Interrupt Mask. Default is 0xffffffff */
330 config Bits32 mir0Mask = 0xffffffff;
331
332 /*! Initial MIR1 Interrupt Mask. Default is 0xffffffff */
333 config Bits32 mir1Mask = 0xffffffff;
334
335 /*! Initial MIR2 Interrupt Mask. Default is 0xffffffff */
336 config Bits32 mir2Mask = 0xffffffff;
337
338 /*! Initial MIR3 Interrupt Mask. Default is 0xffffffff */
339 config Bits32 mir3Mask = 0xffffffff;
340
341 /*!
342 * Error raised when an attempt is made to create a Hwi
343 * that has already been created.
344 */
345 config Error.Id E_alreadyDefined = {
346 msg: "E_alreadyDefined: Hwi already defined, intnum: %d"
347 };
348
349 /*!
350 * Error raised when an undefined interrupt has fired.
351 */
352 config Error.Id E_undefined = {
353 msg: "E_undefined: Hwi undefined, intnum: %d"
354 };
355
356 /*!
357 * Error raised if an attempt is made to create a Hwi
358 * with an interrupt number greater than NUM_INTERRUPTS - 1.
359 */
360 config Error.Id E_badIntNum = {
361 msg: "E_badIntNum, intnum: %d is out of range"
362 };
363
364 /*!
365 * Error raised when an exception occurs
366 */
367 config Error.Id E_excMin = {
368 msg: "E_exception: pc = 0x%08x, lr = 0x%08x."
369 };
370
371 /*!
372 * Issued just prior to Hwi function invocation (with interrupts disabled)
373 */
374 config Log.Event LM_begin = {
375 mask: Diags.USER1 | Diags.USER2,
376 msg: "LM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x"
377 };
378
379 /*!
380 * Issued just after return from Hwi function (with interrupts disabled)
381 */
382 config Log.Event LD_end = {
383 mask: Diags.USER2,
384 msg: "LD_end: hwi: 0x%x"
385 };
386
387
388
389
390 /*!
391 * ======== disable ========
392 */
393 @Macro
394 override UInt disable();
395
396 /*!
397 * ======== enable ========
398 */
399 @Macro
400 override UInt enable();
401
402 /*!
403 * ======== restore ========
404 */
405 @Macro
406 override Void restore(UInt key);
407
408 /*!
409 * ======== inUseMeta ========
410 * @_nodoc
411 * Check for Hwi already in use.
412 * For internal SYS/BIOS use only.
413 * Should be called prior to any internal Hwi.create().
414 *
415 * @param(intNum) interrupt number
416 */
417 metaonly Bool inUseMeta(UInt intNum);
418
419 /*!
420 * ======== getHandle ========
421 * Returns Hwi_Handle associated with intNum
422 *
423 * @param(intNum) interrupt number
424 */
425 @DirectCall
426 Handle getHandle(UInt intNum);
427
428 /*!
429 * ======== enableFIQ ========
430 * Enable FIQ interrupts.
431 *
432 * @b(returns) previous FIQ interrupt enable/disable state
433 */
434 @DirectCall
435 UInt enableFIQ();
436
437 /*!
438 * ======== disableFIQ ========
439 * Disable FIQ interrupts.
440 *
441 * @b(returns) previous FIQ interrupt enable/disable state
442 */
443 @DirectCall
444 UInt disableFIQ();
445
446 /*!
447 * ======== restoreFIQ ========
448 * Restore FIQ interrupts.
449 *
450 * @param(key) enable/disable state to restore
451 */
452 @DirectCall
453 Void restoreFIQ(UInt key);
454
455 /*!
456 * ======== enableIRQ ========
457 * Enable IRQ interrupts.
458 *
459 * @param(key) enable/disable state to restore
460 */
461 @DirectCall
462 UInt enableIRQ();
463
464 /*!
465 * ======== disableIRQ ========
466 * Disable IRQ interrupts.
467 *
468 * @b(returns) previous IRQ interrupt enable/disable state
469 */
470 @DirectCall
471 UInt disableIRQ();
472
473 /*!
474 * ======== restoreIRQ ========
475 * Restore IRQ interrupts.
476 *
477 * @param(key) enable/disable state to restore
478 */
479 @DirectCall
480 Void restoreIRQ(UInt key);
481
482 /*!
483 * ======== disableMIR0 ========
484 * Disable specific interrupts.
485 *
486 * Disables specific interrupts by setting the bits specified by
487 * mask in the Mask Interrupts Register (MIR).
488 *
489 * @param(mask) bitmask of interrupts to disable
490 * @b(returns) previous MIR0 settings bitmask
491 */
492 @DirectCall
493 Bits32 disableMIR0(Bits32 mask);
494 @DirectCall
495 Bits32 disableMIR1(Bits32 mask);
496 @DirectCall
497 Bits32 disableMIR2(Bits32 mask);
498 @DirectCall
499 Bits32 disableMIR3(Bits32 mask);
500
501 /*!
502 * ======== enableMIR ========
503 * Enable specific interrupts.
504 *
505 * Enables specific interrupts by clearing the bits specified by
506 * mask in the Mask Interrupts Register (MIR).
507 *
508 * @param(mask) bitmask of interrupts to enable
509 * @b(returns) previous MIR settings bitmask
510 */
511 @DirectCall
512 Bits32 enableMIR0(Bits32 mask);
513 @DirectCall
514 Bits32 enableMIR1(Bits32 mask);
515 @DirectCall
516 Bits32 enableMIR2(Bits32 mask);
517 @DirectCall
518 Bits32 enableMIR3(Bits32 mask);
519
520 /*!
521 * ======== restoreMIR0 ========
522 * Restore maskable interrupts to the state they were in
523 * when either disableMIR0() or enableMIR0() was called.
524 *
525 * Simply writes mask to the MIR register.
526 *
527 * @param(mask) bitmask of interrupts to restore
528 * @b(returns) previous MIR0 settings bitmask
529 */
530 @DirectCall
531 Bits32 restoreMIR0(Bits32 mask);
532 @DirectCall
533 Bits32 restoreMIR1(Bits32 mask);
534 @DirectCall
535 Bits32 restoreMIR2(Bits32 mask);
536 @DirectCall
537 Bits32 restoreMIR3(Bits32 mask);
538
539 /*!
540 * ======== setPriority ========
541 * Set an interrupt's priority.
542 *
543 * Not an instance function so that it can be used
544 * with non-dispatched interrupts.
545 *
546 * @param(intNum) ID of interrupt
547 * @param(priority) priority
548 */
549 @DirectCall
550 Void setPriority(UInt intNum, UInt priority);
551
552 /*!
553 * ======== setType ========
554 * Set an interrupt's type (FIQ/IRQ).
555 *
556 * Not an instance function so that it can be used
557 * with non-dispatched interrupts.
558 *
559 * @param(intNum) ID of interrupt
560 * @param(type) type = FIQ/IRQ
561 */
562 @DirectCall
563 Void setType(UInt intNum, Type type);
564
565 instance:
566
567 /*! Interrupt type (IRQ/FIQ). Default is IRQ. */
568 config Type type = Type_IRQ;
569
570 571 572 573 574
575 override config Int priority = 63;
576
577 /*! The interrupt controller is designed for priority based interrupts */
578 override config IHwi.MaskingOption maskSetting = IHwi.MaskingOption_LOWER;
579
580 /*!
581 * ======== reconfig ========
582 * Reconfigure a dispatched interrupt.
583 */
584 @DirectCall
585 Void reconfig(FuncPtr fxn, const Params *params);
586
587 internal:
588
589 590 591 592 593 594
595 config UInt (*swiDisable)();
596 config Void (*swiRestoreHwi)(UInt);
597 config UInt (*taskDisable)();
598 config Void (*taskRestoreHwi)(UInt);
599
600
601 Void init();
602
603
604 Void dispatchIRQ();
605
606
607 Void dispatchIRQC(Irp irp);
608
609
610 Void dispatchFIQC();
611
612
613 Void nonPluggedHwiHandler(UArg arg);
614
615 /*!
616 * const array to hold all HookSet objects.
617 */
618 config HookSet hooks[length] = [];
619
620 /*! Meta World Only Hwi Configuration Object. */
621 metaonly struct InterruptObj {
622 Bool used;
623 FuncPtr fxn;
624 };
625
626 /*!
627 * Meta-only array of interrupt objects.
628 * This meta-only array of Hwi config objects is initialized
629 * in Hwi.xs:module$meta$init().
630 */
631 metaonly config InterruptObj interrupt[NUM_INTERRUPTS];
632
633 struct Instance_State {
634 Type type;
635 UInt priority;
636 UArg arg;
637 FuncPtr fxn;
638 Irp irp;
639 Ptr hookEnv[];
640 };
641
642 struct Module_State {
643 Bits32 mir0Mask;
644 Bits32 mir1Mask;
645 Bits32 mir2Mask;
646 Bits32 mir3Mask;
647 UInt spuriousInts;
648 UInt lastSpuriousInt;
649 UInt irp;
650 Char *taskSP;
651
652
653 Char *isrStack;
654 Ptr isrStackBase;
655 Ptr isrStackSize;
656 Char fiqStack[];
657 SizeT fiqStackSize;
658 Hwi.Object nonPluggedHwi;
659 Handle dispatchTable[NUM_INTERRUPTS];
660
661 };
662 }
663
664 665 666 667
668