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32
33
34 /*!
35 * ======== UCS ========
36 * MSP430 Unified Clock System
37 */
38 metaonly module UCS inherits IClock
39 {
40 /*! DCO4 Bit */
41 enum DCO4_t {
42 DCO4_OFF = 0x0000, /*! Disable DCO4 bit */
43 DCO4 = 0x1000 /*! Enable DCO4 bit */
44 };
45
46 /*! DCO3 Bit */
47 enum DCO3_t {
48 DCO3_OFF = 0x0000, /*! Disable DCO3 bit */
49 DCO3 = 0x0800 /*! Enable DCO3 bit */
50 };
51
52 /*! DCO2 Bit */
53 enum DCO2_t {
54 DCO2_OFF = 0x0000, /*! Disable DCO2 bit */
55 DCO2 = 0x0400 /*! Enable DCO2 bit */
56 };
57
58 /*! DCO1 Bit */
59 enum DCO1_t {
60 DCO1_OFF = 0x0000, /*! Disable DCO1 bit */
61 DCO1 = 0x0200 /*! Enable DCO1 bit */
62 };
63
64 /*! DCO0 Bit */
65 enum DCO0_t {
66 DCO0_OFF = 0x0000, /*! Disable DCO0 bit */
67 DCO0 = 0x0100 /*! Enable DCO0 bit */
68 };
69
70 /*! MOD4 Bit */
71 enum MOD4_t {
72 MOD4_OFF = 0x0000, /*! Disable MOD4 bit */
73 MOD4 = 0x0080 /*! Enable MOD4 bit */
74 };
75
76 /*! MOD3 Bit */
77 enum MOD3_t {
78 MOD3_OFF = 0x0000, /*! Disable MOD3 bit */
79 MOD3 = 0x0040 /*! Enable MOD3 bit */
80 };
81
82 /*! MOD2 Bit */
83 enum MOD2_t {
84 MOD2_OFF = 0x0000, /*! Disable MOD2 bit */
85 MOD2 = 0x0020 /*! Enable MOD2 bit */
86 };
87
88 /*! MOD1 Bit */
89 enum MOD1_t {
90 MOD1_OFF = 0x0000, /*! Disable MOD1 bit */
91 MOD1 = 0x0010 /*! Enable MOD1 bit */
92 };
93
94 /*! MOD0 Bit */
95 enum MOD0_t {
96 MOD0_OFF = 0x0000, /*! Disable MOD0 bit */
97 MOD0 = 0x0080 /*! Enable MOD0 bit */
98 };
99
100 /*! DCO frequency range select */
101 enum DCORSEL_t {
102 DCORSEL_0 = 0x0000, /*! DCORSEL_0 */
103 DCORSEL_1 = 0x0010, /*! DCORSEL_1 */
104 DCORSEL_2 = 0x0020, /*! DCORSEL_2 */
105 DCORSEL_3 = 0x0030, /*! DCORSEL_3 */
106 DCORSEL_4 = 0x0040, /*! DCORSEL_4 */
107 DCORSEL_5 = 0x0050, /*! DCORSEL_5 */
108 DCORSEL_6 = 0x0060, /*! DCORSEL_6 */
109 DCORSEL_7 = 0x0070 /*! DCORSEL_7 */
110 };
111
112 /*! DISMOD Bit */
113 enum DISMOD_t {
114 DISMOD_OFF = 0x0000, /*! Modulation enabled */
115 DISMOD = 0x0001 /*! Modulation disabled */
116 };
117
118 /*! FLL Loop Divider */
119 enum FLLD_t {
120 FLLD_0 = 0x0000, /*! Multiply Selected Loop Freq. 1 */
121 FLLD_1 = 0x1000, /*! Multiply Selected Loop Freq. 2 */
122 FLLD_2 = 0x2000, /*! Multiply Selected Loop Freq. 4 */
123 FLLD_3 = 0x3000, /*! Multiply Selected Loop Freq. 8 */
124 FLLD_4 = 0x4000, /*! Multiply Selected Loop Freq. 16 */
125 FLLD_5 = 0x5000, /*! Multiply Selected Loop Freq. 32 */
126 FLLD_6 = 0x6000, /*! Multiply Selected Loop Freq. 32 */
127 FLLD_7 = 0x7000 /*! Multiply Selected Loop Freq. 32 */
128 };
129
130 /*! FLL Multiplier Bit 0 */
131 enum FLLN0_t {
132 FLLN0_OFF = 0x0000, /*! Disable FLLN bit 0 */
133 FLLN0 = 0x0001 /*! Enable FLLN bit 0 */
134 };
135
136 /*! FLL Multiplier Bit 1 */
137 enum FLLN1_t {
138 FLLN1_OFF = 0x0000, /*! Disable FLLN bit 1 */
139 FLLN1 = 0x0002 /*! Enable FLLN bit 1 */
140 };
141
142 /*! FLL Multiplier Bit 2 */
143 enum FLLN2_t {
144 FLLN2_OFF = 0x0000, /*! Disable FLLN bit 2 */
145 FLLN2 = 0x0004 /*! Enable FLLN bit 2 */
146 };
147
148 /*! FLL Multiplier Bit 3 */
149 enum FLLN3_t {
150 FLLN3_OFF = 0x0000, /*! Disable FLLN bit 3 */
151 FLLN3 = 0x0008 /*! Enable FLLN bit 3 */
152 };
153
154 /*! FLL Multiplier Bit 4 */
155 enum FLLN4_t {
156 FLLN4_OFF = 0x0000, /*! Disable FLLN bit 4 */
157 FLLN4 = 0x0010 /*! Enable FLLN bit 4 */
158 };
159
160 /*! FLL Multiplier Bit 5 */
161 enum FLLN5_t {
162 FLLN5_OFF = 0x0000, /*! Disable FLLN bit 5 */
163 FLLN5 = 0x0020 /*! Enable FLLN bit 5 */
164 };
165
166 /*! FLL Multiplier Bit 6 */
167 enum FLLN6_t {
168 FLLN6_OFF = 0x0000, /*! Disable FLLN bit 6 */
169 FLLN6 = 0x0040 /*! Enable FLLN bit 6 */
170 };
171
172 /*! FLL Multiplier Bit 7 */
173 enum FLLN7_t {
174 FLLN7_OFF = 0x0000, /*! Disable FLLN bit 7 */
175 FLLN7 = 0x0080 /*! Enable FLLN bit 7 */
176 };
177
178 /*! FLL Multiplier Bit 8 */
179 enum FLLN8_t {
180 FLLN8_OFF = 0x0000, /*! Disable FLLN bit 8 */
181 FLLN8 = 0x0100 /*! Enable FLLN bit 8 */
182 };
183
184 /*! FLL Multiplier Bit 9 */
185 enum FLLN9_t {
186 FLLN9_OFF = 0x0000, /*! Disable FLLN bit 9 */
187 FLLN9 = 0x0200 /*! Enable FLLN bit 9 */
188 };
189
190 /*! FLL Reference Select */
191 enum SELREF_t {
192 SELREF_0 = 0x0000, /*! FLL Reference by XT1CLK */
193 SELREF_1 = 0x0010, /*! Reserved */
194 SELREF_2 = 0x0020, /*! FLL Reference by REFOCLK */
195 SELREF_3 = 0x0030, /*! Reserved */
196 SELREF_4 = 0x0040, /*! Reserved */
197 SELREF_5 = 0x0050, /*! FLL Reference by XT2CLK */
198 SELREF_6 = 0x0060, /*! Reserved */
199 SELREF_7 = 0x0070 /*! Reserved */
200 };
201
202 /*! FLL Reference Divider */
203 enum FLLREFDIV_t {
204 FLLREFDIV_0 = 0x0000, /*! f(FLLREFCLK) / 1 */
205 FLLREFDIV_1 = 0x0001, /*! f(FLLREFCLK) / 2 */
206 FLLREFDIV_2 = 0x0002, /*! f(FLLREFCLK) / 4 */
207 FLLREFDIV_3 = 0x0003, /*! f(FLLREFCLK) / 8 */
208 FLLREFDIV_4 = 0x0004, /*! f(FLLREFCLK) / 12 */
209 FLLREFDIV_5 = 0x0005, /*! f(FLLREFCLK) / 16 */
210 FLLREFDIV_6 = 0x0006, /*! Reserved */
211 FLLREFDIV_7 = 0x0007 /*! Reserved */
212 };
213
214 /*! Select the ACLK source */
215 enum SELA_t {
216 SELA_0 = 0x0000, /*! XT1CLK */
217 SELA_1 = 0x0100, /*! VLOCLK */
218 SELA_2 = 0x0200, /*! REFOCLK */
219 SELA_3 = 0x0300, /*! DCOCLK */
220 SELA_4 = 0x0400, /*! DCOCLKDIV */
221 SELA_5 = 0x0500, /*! XT2CLK */
222 SELA_6 = 0x0600, /*! Reserved */
223 SELA_7 = 0x0700 /*! Reserved */
224 };
225
226 /*! Select the SMCLK source */
227 enum SELS_t {
228 SELS_0 = 0x0000, /*! XT1CLK */
229 SELS_1 = 0x0010, /*! VLOCLK */
230 SELS_2 = 0x0020, /*! REFOCLK */
231 SELS_3 = 0x0030, /*! DCOCLK */
232 SELS_4 = 0x0040, /*! DCOCLKDIV */
233 SELS_5 = 0x0050, /*! XT2CLK */
234 SELS_6 = 0x0060, /*! Reserved */
235 SELS_7 = 0x0070 /*! Reserved */
236 };
237
238 /*! Select the MCLK source */
239 enum SELM_t {
240 SELM_0 = 0x0000, /*! XT1CLK */
241 SELM_1 = 0x0001, /*! VLOCLK */
242 SELM_2 = 0x0002, /*! REFOCLK */
243 SELM_3 = 0x0003, /*! DCOCLK */
244 SELM_4 = 0x0004, /*! DCOCLKDIV */
245 SELM_5 = 0x0005, /*! XT2CLK */
246 SELM_6 = 0x0006, /*! Reserved */
247 SELM_7 = 0x0007 /*! Reserved */
248 };
249
250 /*! ACLK source divider available at external pin */
251 enum DIVPA_t {
252 DIVPA_0 = 0x0000, /*! Divide by 1 */
253 DIVPA_1 = 0x1000, /*! Divide by 2 */
254 DIVPA_2 = 0x2000, /*! Divide by 4 */
255 DIVPA_3 = 0x3000, /*! Divide by 8 */
256 DIVPA_4 = 0x4000, /*! Divide by 16 */
257 DIVPA_5 = 0x5000, /*! Divide by 32 */
258 DIVPA_6 = 0x6000, /*! Reserved */
259 DIVPA_7 = 0x7000 /*! Reserved */
260 };
261
262 /*! ACLK source divider */
263 enum DIVA_t {
264 DIVA_0 = 0x0000, /*! Divide by 1 */
265 DIVA_1 = 0x0100, /*! Divide by 2 */
266 DIVA_2 = 0x0200, /*! Divide by 4 */
267 DIVA_3 = 0x0300, /*! Divide by 8 */
268 DIVA_4 = 0x0400, /*! Divide by 16 */
269 DIVA_5 = 0x0500, /*! Divide by 32 */
270 DIVA_6 = 0x0600, /*! Reserved */
271 DIVA_7 = 0x0700 /*! Reserved */
272 };
273
274 /*! SMCLK source divider */
275 enum DIVS_t {
276 DIVS_0 = 0x0000, /*! Divide by 1 */
277 DIVS_1 = 0x0010, /*! Divide by 2 */
278 DIVS_2 = 0x0020, /*! Divide by 4 */
279 DIVS_3 = 0x0030, /*! Divide by 8 */
280 DIVS_4 = 0x0040, /*! Divide by 16 */
281 DIVS_5 = 0x0050, /*! Divide by 32 */
282 DIVS_6 = 0x0060, /*! Reserved */
283 DIVS_7 = 0x0070 /*! Reserved */
284 };
285
286 /*! MCLK source divider */
287 enum DIVM_t {
288 DIVM_0 = 0x0000, /*! Divide by 1 */
289 DIVM_1 = 0x0010, /*! Divide by 2 */
290 DIVM_2 = 0x0020, /*! Divide by 4 */
291 DIVM_3 = 0x0030, /*! Divide by 8 */
292 DIVM_4 = 0x0040, /*! Divide by 16 */
293 DIVM_5 = 0x0050, /*! Divide by 32 */
294 DIVM_6 = 0x0060, /*! Reserved */
295 DIVM_7 = 0x0070 /*! Reserved */
296 };
297
298 /*! XT2 oscillator current */
299 enum XT2DRIVE_t {
300 XT2DRIVE_0 = 0x0000, /*! 4 MHz to 8 MHz */
301 XT2DRIVE_1 = 0x4000, /*! 8 MHz to 16 MHz */
302 XT2DRIVE_2 = 0x8000, /*! 16 MHz to 24 MHz */
303 XT2DRIVE_3 = 0xC000 /*! 24 MHz to 32 MHz */
304 };
305
306 /*! XT2 bypass select */
307 enum XT2BYPASS_t {
308 XT2BYPASS_OFF = 0x0000, /*! XT2 sourced internally */
309 XT2BYPASS = 0x1000 /*! XT2 sourced externally from pin */
310 };
311
312 /*! Turns off the XT2 oscillator */
313 enum XT2OFF_t {
314 XT2OFF_OFF = 0x0000, /*! Enable XT2 */
315 XT2OFF = 0x0100 /*! Disable XT2*/
316 };
317
318 /*! XT1 oscillator current */
319 enum XT1DRIVE_t {
320 XT1DRIVE_0 = 0x0000, /*! XT1 drive 0 */
321 XT1DRIVE_1 = 0x0040, /*! XT1 drive 1 */
322 XT1DRIVE_2 = 0x0080, /*! XT1 drive 2 */
323 XT1DRIVE_3 = 0x00C0 /*! XT1 drive 3 */
324 };
325
326 /*! XTS mode select */
327 enum XTS_t {
328 XTS_OFF = 0x0000, /*! Low Frequency */
329 XTS = 0x0020 /*! High Frequency */
330 };
331
332 /*! XT1 bypass select */
333 enum XT1BYPASS_t {
334 XT1BYPASS_OFF = 0x0000, /*! XT1 sourced internally */
335 XT1BYPASS = 0x0010 /*! XT1 sourced externally from pin */
336 };
337
338 /*! XT1 oscillator capacitor select */
339 enum XCAP_t {
340 XCAP_0 = 0x0000, /*! XT1 Cap 0 */
341 XCAP_1 = 0x0004, /*! XT1 Cap 1 */
342 XCAP_2 = 0x0008, /*! XT1 Cap 2 */
343 XCAP_3 = 0x000C /*! XT1 Cap 3 */
344 };
345
346 /*! SMCLK off */
347 enum SMCLKOFF_t {
348 SMCLKOFF_OFF = 0x0000, /*! SMCLK on */
349 SMCLKOFF = 0x0002 /*! SMCLK off */
350 };
351
352 /*! Turns off the XT1 oscillator */
353 enum XT1OFF_t {
354 XT1OFF_OFF = 0x0000, /*! Enable XT1 */
355 XT1OFF = 0x0001 /*! Disable XT1 */
356 };
357
358 /*! XT2 oscillator fault flag */
359 enum XT2OFFG_t {
360 XT2OFFG_OFF = 0x0000, /*! No fault condition present */
361 XT2OFFG = 0x0008 /*! XT2 fault condition present */
362 };
363
364 /*! XT1 high frequency oscillator fault flag */
365 enum XT1HFOFFG_t {
366 XT1HFOFFG_OFF = 0x0000, /*! No fault condition present */
367 XT1HFOFFG = 0x0004 /*! XT1 HF fault condition present */
368 };
369
370 /*! XT1 low frequency oscillator fault flag */
371 enum XT1LFOFFG_t {
372 XT1LFOFFG_OFF = 0x0000, /*! No fault condition present */
373 XT1LFOFFG = 0x0002 /*! XT1 LF fault condition present */
374 };
375
376 /*! DCO fault flag */
377 enum DCOFFG_t {
378 DCOFFG_OFF = 0x0000, /*! No fault condition present */
379 DCOFFG = 0x0001 /*! DCO fault condition present */
380 };
381
382 /*! MODOSC clock request enable */
383 enum MODOSCREQEN_t {
384 MODOSCREQEN_OFF = 0x0000, /*! MODOSC conditional requests are disabled */
385 MODOSCREQEN = 0x0008 /*! MODOSC conditional requests are enabled */
386 };
387
388 /*! SMCLK clock request enable */
389 enum SMCLKREQEN_t {
390 SMCLKREQEN_OFF = 0x0000, /*! SMCLK conditional requests are disabled */
391 SMCLKREQEN = 0x0004 /*! SMCLK conditional requests are enabled */
392 };
393
394 /*! MCLK clock request enable */
395 enum MCLKREQEN_t {
396 MCLKREQEN_OFF = 0x0000, /*! MCLK conditional requests are disabled */
397 MCLKREQEN = 0x0002 /*! MCLK conditional requests are enabled */
398 };
399
400 /*! ACLK clock request enable */
401 enum ACLKREQEN_t {
402 ACLKREQEN_OFF = 0x0000, /*! ACLK conditional requests are disabled */
403 ACLKREQEN = 0x0001 /*! ACLK conditional requests are enabled */
404 };
405
406 /*! Selects XT2 bypass input swing level */
407 enum XT2BYPASSLV_t {
408 XT2BYPASSLV_OFF = 0x0000, /*! Input range from 0 to DVCC */
409 XT2BYPASSLV = 0x0002 /*! Input range from 0 to DVIO */
410 };
411
412 /*! Selects XT1 bypass input swing level */
413 enum XT1BYPASSLV_t {
414 XT1BYPASSLV_OFF = 0x0000, /*! Input range from 0 to DVCC */
415 XT1BYPASSLV = 0x0001 /*! Input range from 0 to DVIO */
416 };
417
418 /*!
419 * ======== UCSCTL0_t ========
420 * Unified Clock System Control 0 Register
421 *
422 * @field(DCO) DCO tap selection.
423 * @field(MOD) Modulation bit counter.
424 */
425 struct UCSCTL0_t {
426 DCO0_t DCO0; /*! DCO tap selection bit 0 */
427 DCO1_t DCO1; /*! DCO tap selection bit 1 */
428 DCO2_t DCO2; /*! DCO tap selection bit 2 */
429 DCO3_t DCO3; /*! DCO tap selection bit 3 */
430 DCO4_t DCO4; /*! DCO tap selection bit 4 */
431 MOD0_t MOD0; /*! Modulation bit counter bit 0 */
432 MOD1_t MOD1; /*! Modulation bit counter bit 1 */
433 MOD2_t MOD2; /*! Modulation bit counter bit 2 */
434 MOD3_t MOD3; /*! Modulation bit counter bit 3 */
435 MOD4_t MOD4; /*! Modulation bit counter bit 4 */
436 }
437
438 /*!
439 * ======== UCSCTL1_t ========
440 * Unified Clock System Control 1 Register
441 *
442 * @field(DCORSEL) DCO frequency range select. These bits select the DCO frequency range of operation defined in the
443 * device-specific datasheet.
444 * @field(DISMOD) 0 Modulation enabled, 1 Modulation disabled.
445 */
446 struct UCSCTL1_t {
447 DCORSEL_t DCORSEL; /*! DCO frequency range select. These bits select the DCO frequency range of operation defined in the
448 * device-specific datasheet. */
449 DISMOD_t DISMOD; /*! Modulation. This bit enables/disables the modulation.
450 * 0 Modulation enabled
451 * 1 Modulation disabled */
452 }
453
454 /*!
455 * ======== UCSCTL2_t ========
456 * Unified Clock System Control 2 Register
457 *
458 * @field(FLLD) FLL loop divider. These bits divide fDCOCLK in the FLL feedback loop. This results in an additional multiplier
459 * for the multiplier bits.
460 * @field(FLLN) Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to
461 * FLLN causes N to be set to 1.
462 */
463 struct UCSCTL2_t {
464 FLLD_t FLLD; /*! FLL loop divider. These bits divide fDCOCLK in the FLL feedback loop. This results in an additional multiplier
465 * for the multiplier bits. See also multiplier bits.
466 * 000 fDCOCLK/1
467 * 001 fDCOCLK/2
468 * 010 fDCOCLK/4
469 * 011 fDCOCLK/8
470 * 100 fDCOCLK/16
471 * 101 fDCOCLK/32
472 * 110 Reserved for future use. Defaults to fDCOCLK/32
473 * 111 Reserved for future use. Defaults to fDCOCLK/32 */
474 FLLN0_t FLLN0; /*! Multiplier bit 0 */
475 FLLN1_t FLLN1; /*! Multiplier bit 1 */
476 FLLN2_t FLLN2; /*! Multiplier bit 2 */
477 FLLN3_t FLLN3; /*! Multiplier bit 3 */
478 FLLN4_t FLLN4; /*! Multiplier bit 4 */
479 FLLN5_t FLLN5; /*! Multiplier bit 5 */
480 FLLN6_t FLLN6; /*! Multiplier bit 6 */
481 FLLN7_t FLLN7; /*! Multiplier bit 7 */
482 FLLN8_t FLLN8; /*! Multiplier bit 8 */
483 FLLN9_t FLLN9; /*! Multiplier bit 9 */
484 }
485
486 /*!
487 * ======== UCSCTL3_t ========
488 * Unified Clock System Control 3 Register
489 *
490 * @field(SELREF) FLL reference select. These bits select the FLL reference clock source.
491 * @field(FLLREFDIV) FLL reference divider. These bits define the divide factor for fFLLREFCLK. The divided frequency is used as the
492 * FLL reference frequency.
493 */
494 struct UCSCTL3_t {
495 SELREF_t SELREF; /*! FLL reference select. These bits select the FLL reference clock source.
496 * 000 XT1CLK
497 * 001 Reserved for future use. Defaults to XT1CLK.
498 * 010 REFOCLK
499 * 011 Reserved for future use. Defaults to REFOCLK.
500 * 100 Reserved for future use. Defaults to REFOCLK.
501 * 101 XT2CLK when available, otherwise REFOCLK.
502 * 110 Reserved for future use. XT2CLK when available, otherwise REFOCLK.
503 * 111 No selection. For the 'F543x and 'F541x non-A versions only, this defaults to XT2CLK. Reserved for
504 * future use. XT2CLK when available, otherwise REFOCLK. */
505 FLLREFDIV_t FLLREFDIV; /*! FLL reference divider. These bits define the divide factor for fFLLREFCLK. The divided frequency is used as the
506 * FLL reference frequency.
507 * 000 fFLLREFCLK/1
508 * 001 fFLLREFCLK/2
509 * 010 fFLLREFCLK/4
510 * 011 fFLLREFCLK/8
511 * 100 fFLLREFCLK/12
512 * 101 fFLLREFCLK/16
513 * 110 Reserved for future use. Defaults to fFLLREFCLK/16.
514 * 111 Reserved for future use. Defaults to fFLLREFCLK/16. */
515 }
516
517 /*!
518 * ======== UCSCTL4_t ========
519 * Unified Clock System Control 4 Register
520 *
521 * @field(SELA) Selects the ACLK source
522 * @field(SELS) Selects the SMCLK source
523 * @field(SELM) Selects the MCLK source
524 */
525 struct UCSCTL4_t {
526 SELA_t SELA; /*! Selects the ACLK source
527 * 000 XT1CLK
528 * 001 VLOCLK
529 * 010 REFOCLK
530 * 011 DCOCLK
531 * 100 DCOCLKDIV
532 * 101 XT2CLK when available, otherwise DCOCLKDIV
533 * 110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV.
534 * 111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. */
535 SELS_t SELS; /*! Selects the SMCLK source
536 * 000 XT1CLK
537 * 001 VLOCLK
538 * 010 REFOCLK
539 * 011 DCOCLK
540 * 100 DCOCLKDIV
541 * 101 XT2CLK when available, otherwise DCOCLKDIV
542 * 110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV.
543 * 111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. */
544 SELM_t SELM; /*! Selects the MCLK source
545 * 000 XT1CLK
546 * 001 VLOCLK
547 * 010 REFOCLK
548 * 011 DCOCLK
549 * 100 DCOCLKDIV
550 * 101 XT2CLK when available, otherwise DCOCLKDIV
551 * 110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV.
552 * 111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. */
553 }
554
555 /*!
556 * ======== UCSCTL5_t ========
557 * Unified Clock System Control 5 Register
558 *
559 * @field(SELA) Selects the ACLK source
560 * @field(SELS) Selects the SMCLK source
561 * @field(SELM) Selects the MCLK source
562 */
563 struct UCSCTL5_t {
564 DIVPA_t DIVPA; /*! ACLK source divider available at external pin. Divides the frequency of ACLK and presents it to an external pin.
565 * 000 fACLK/1
566 * 001 fACLK/2
567 * 010 fACLK/4
568 * 011 fACLK/8
569 * 100 fACLK/16
570 * 101 fACLK/32
571 * 110 Reserved for future use. Defaults to fACLK/32.
572 * 111 Reserved for future use. Defaults to fACLK/32. */
573 DIVA_t DIVA; /*! ACLK source divider. Divides the frequency of the ACLK clock source.
574 * 000 fACLK/1
575 * 001 fACLK/2
576 * 010 fACLK/4
577 * 011 fACLK/8
578 * 100 fACLK/16
579 * 101 fACLK/32
580 * 110 Reserved for future use. Defaults to fACLK/32.
581 * 111 Reserved for future use. Defaults to fACLK/32. */
582 DIVS_t DIVS; /*! SMCLK source divider
583 * 000 fSMCLK/1
584 * 001 fSMCLK/2
585 * 010 fSMCLK/4
586 * 011 fSMCLK/8
587 * 100 fSMCLK/16
588 * 101 fSMCLK/32
589 * 110 Reserved for future use. Defaults to fSMCLK/32.
590 * 111 Reserved for future use. Defaults to fSMCLK/32. */
591 DIVM_t DIVM; /*! MCLK source divider
592 * 000 fMCLK/1
593 * 001 fMCLK/2
594 * 010 fMCLK/4
595 * 011 fMCLK/8
596 * 100 fMCLK/16
597 * 101 fMCLK/32
598 * 110 Reserved for future use. Defaults to fMCLK/32.
599 * 111 Reserved for future use. Defaults to fMCLK/32.*/
600 }
601
602 /*!
603 * ======== UCSCTL6_t ========
604 * Unified Clock System Control 6 Register
605 *
606 * @field(SELA) Selects the ACLK source
607 * @field(SELS) Selects the SMCLK source
608 * @field(SELM) Selects the MCLK source
609 */
610 struct UCSCTL6_t {
611 XT2DRIVE_t XT2DRIVE; /*! The XT2 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current
612 * for reliable and quick startup. If needed, user software can reduce the drive strength.
613 * 00 Lowest current consumption. XT2 oscillator operating range is 4 MHz to 8 MHz.
614 * 01 Increased drive strength XT2 oscillator. XT2 oscillator operating range is 8 MHz to 16 MHz.
615 * 10 Increased drive capability XT2 oscillator. XT2 oscillator operating range is 16 MHz to 24 MHz.
616 * 11 Maximum drive capability and maximum current consumption for both XT2 oscillator. XT2 oscillator
617 * operating range is 24 MHz to 32 MHz. */
618 XT2BYPASS_t XT2BYPASS; /*! XT2 bypass select
619 * 0 XT2 sourced internally
620 * 1 XT2 sourced externally from pin */
621 XT2OFF_t XT2OFF; /*! Turns off the XT2 oscillator
622 * 0 XT2 is on if XT2 is selected via the port selection and XT2 is not in bypass mode of operation.
623 * 1 XT2 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source
624 * required for FLL operation. */
625 XT1DRIVE_t XT1DRIVE; /*! The XT1 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current
626 * for reliable and quick startup. If needed, user software can reduce the drive strength.
627 * 00 Lowest current consumption for XT1 LF mode. XT1 oscillator operating range in HF mode is 4 MHz to
628 * 8 MHz.
629 * 01 Increased drive strength for XT1 LF mode. XT1 oscillator operating range in HF mode is 8 MHz to
630 * 16 MHz.
631 * 10 Increased drive capability for XT1 LF mode. XT1 oscillator operating range in HF mode is 16 MHz to
632 * 24 MHz.
633 * 11 Maximum drive capability and maximum current consumption for XT1 LF mode. XT1 oscillator operating
634 * range in HF mode is 24 MHz to 32 MHz. */
635 XTS_t XTS; /*! XT1 mode select
636 * 0 Low-frequency mode. XCAP bits define the capacitance at the XIN and XOUT pins.
637 * 1 High-frequency mode. XCAP bits are not used. */
638 XT1BYPASS_t XT1BYPASS; /*! XT1 bypass select
639 * 0 XT1 sourced internally
640 * 1 XT1 sourced externally from pin */
641 XCAP_t XCAP; /*! Oscillator capacitor selection. These bits select the capacitors applied to the LF crystal or resonator in the LF
642 * mode (XTS = 0). The effective capacitance (seen by the crystal) is Ceff (CXIN + 2 pF)/2. It is assumed that
643 * CXIN = CXOUT and that a parasitic capacitance of 2 pF is added by the package and the printed circuit board. For
644 * details about the typical internal and the effective capacitors, refer to the device-specific data sheet. */
645 SMCLKOFF_t SMCLKOFF; /*! SMCLK off. This bit turns off the SMCLK.
646 * 0 SMCLK on
647 * 1 SMCLK off */
648 XT1OFF_t XT1OFF; /*! XT1 off. This bit turns off the XT1.
649 * 0 XT1 is on if XT1 is selected via the port selection and XT1 is not in bypass mode of operation.
650 * 1 XT1 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source
651 * required for FLL operation. */
652 }
653
654 /*!
655 * ======== UCSCTL7_t ========
656 * Unified Clock System Control 7 Register
657 *
658 * @field(XT2OFFG) 0 No fault condition, 1 XT2 fault
659 * @field(XT1HFOFFG) 0 No fault condition, 1 XT1 HF fault
660 * @field(XT1LFOFFG) 0 No fault condition, 1 XT1 LF fault
661 * @field(DCOFFG) 0 No fault condition, 1 DCO fault
662 */
663 struct UCSCTL7_t {
664 XT2OFFG_t XT2OFFG; /*! XT2 oscillator fault flag. If this bit is set, the OFIFG flag is also set. XT2OFFG is set if a XT2 fault
665 * condition exists. XT2OFFG can be cleared via software. If the XT2 fault condition still remains,
666 * XT2OFFG is set.
667 * 0 No fault condition occurred after the last reset.
668 * 1 XT2 fault. An XT2 fault occurred after the last reset. */
669 XT1HFOFFG_t XT1HFOFFG; /*! XT1 oscillator fault flag (HF mode). If this bit is set, the OFIFG flag is also set. XT1HFOFFG is set if a
670 * XT1 fault condition exists. XT1HFOFFG can be cleared via software. If the XT1 fault condition still
671 * remains, XT1HFOFFG is set.
672 * 0 No fault condition occurred after the last reset.
673 * 1 XT1 fault. An XT1 fault occurred after the last reset. */
674 XT1LFOFFG_t XT1LFOFFG; /*! XT1 oscillator fault flag (LF mode). If this bit is set, the OFIFG flag is also set. XT1LFOFFG is set if a
675 * XT1 fault condition exists. XT1LFOFFG can be cleared via software. If the XT1 fault condition still
676 * remains, XT1LFOFFG is set.
677 * 0 No fault condition occurred after the last reset.
678 * 1 XT1 fault (LF mode). A XT1 fault occurred after the last reset. */
679 DCOFFG_t DCOFFG; /*! DCO fault flag. If this bit is set, the OFIFG flag is also set. The DCOFFG bit is set if DCO = {0} or
680 * DCO = {31}. DCOFFG can be cleared via software. If the DCO fault condition still remains, DCOFFG is
681 * set.
682 * 0 No fault condition occurred after the last reset.
683 * 1 DCO fault. A DCO fault occurred after the last reset. */
684 }
685
686 /*!
687 * ======== UCSCTL8_t ========
688 * Unified Clock System Control 8 Register
689 *
690 * @field(MODOSCREQEN) 0 MODOSC conditional requests are disabled
691 * 1 MODOSC conditional requests are enabled
692 * @field(SMCLKREQEN) 0 SMCLK conditional requests are disabled
693 * 1 SMCLK conditional requests are enabled
694 * @field(MCLKREQEN) 0 MCLK conditional requests are disabled
695 * 1 MCLK conditional requests are enabled
696 * @field(ACLKREQEN) 0 ACLK conditional requests are disabled
697 * 1 ACLK conditional requests are enabled
698 */
699 struct UCSCTL8_t {
700 MODOSCREQEN_t MODOSCREQEN; /*! MODOSC clock request enable. Setting this enables conditional module requests for MODOSC.
701 * 0 MODOSC conditional requests are disabled.
702 * 1 MODOSC conditional requests are enabled. */
703 SMCLKREQEN_t SMCLKREQEN; /*! SMCLK clock request enable. Setting this enables conditional module requests for SMCLK.
704 * 0 SMCLK conditional requests are disabled.
705 * 1 SMCLK conditional requests are enabled. */
706 MCLKREQEN_t MCLKREQEN; /*! MCLK clock request enable. Setting this enables conditional module requests for MCLK
707 * 0 MCLK conditional requests are disabled.
708 * 1 MCLK conditional requests are enabled. */
709 ACLKREQEN_t ACLKREQEN; /*! ACLK clock request enable. Setting this enables conditional module requests for ACLK
710 * 0 ACLK conditional requests are disabled.
711 * 1 ACLK conditional requests are enabled. */
712 }
713
714 /*!
715 * ======== UCSCTL9_t ========
716 * Unified Clock System Control 9 Register
717 *
718 * @field(XT2BYPASSLV) 0 Input range from 0 to DVCC
719 * 1 Input range from 0 to DVIO
720 * @field(XT1BYPASSLV) 0 Input range from 0 to DVCC
721 * 1 Input range from 0 to DVIO
722 */
723 struct UCSCTL9_t {
724 XT2BYPASSLV_t XT2BYPASSLV; /*! Selects XT2 bypass input swing level. Must be set for reduced swing operation.
725 * 0 Input range from 0 to DVCC
726 * 1 Input range from 0 to DVIO */
727 XT1BYPASSLV_t XT1BYPASSLV; /*! Selects XT1 bypass input swing level. Must be set for reduced swing operation.
728 * 0 Input range from 0 to DVCC
729 * 1 Input range from 0 to DVIO */
730 }
731
732 733 734
735 /*! Select the clock source */
736 enum UCS_CLK_SOURCE_t {
737 UCS_XT1CLK_SELECT = 0x0000, /*! XT1CLK */
738 UCS_VLOCLK_SELECT = 0x0010, /*! VLOCLK */
739 UCS_REFOCLK_SELECT = 0x0020, /*! REFOCLK */
740 UCS_DCOCLK_SELECT = 0x0030, /*! DCOCLK */
741 UCS_DCOCLKDIV_SELECT = 0x0040, /*! DCOCLKDIV */
742 UCS_XT2CLK_SELECT = 0x0050 /*! XT2CLK */
743 };
744
745 /*! Select clock source divider */
746 enum UCS_CLK_SRC_DIVIDER_t {
747 UCS_CLOCK_DIVIDER_1 = 0x0000, /*! Divide by 1 */
748 UCS_CLOCK_DIVIDER_2 = 0x0010, /*! Divide by 2 */
749 UCS_CLOCK_DIVIDER_4 = 0x0020, /*! Divide by 4 */
750 UCS_CLOCK_DIVIDER_8 = 0x0030, /*! Divide by 8 */
751 UCS_CLOCK_DIVIDER_12 = 0x0040, /*! Divide by 12 */
752 UCS_CLOCK_DIVIDER_16 = 0x0050, /*! Divide by 16 */
753 UCS_CLOCK_DIVIDER_32 = 0x0060 /*! Divide by 32 */
754 };
755
756 /*! XT1 oscillator capacitor select */
757 enum UCS_XCAP_t {
758 UCS_XCAP_0 = 0x0000, /*! ~ 2 pF */
759 UCS_XCAP_1 = 0x0004, /*! ~ 5.5 pF */
760 UCS_XCAP_2 = 0x0008, /*! ~ 8.5 pF */
761 UCS_XCAP_3 = 0x000C /*! ~ 12 pF */
762 };
763
764 instance:
765
766 /*! Unified Clock System Control 0 Register */
767 config UCSCTL0_t UCSCTL0 = {
768 DCO0 : DCO0_OFF,
769 DCO1 : DCO1_OFF,
770 DCO2 : DCO2_OFF,
771 DCO3 : DCO3_OFF,
772 DCO4 : DCO4_OFF,
773 MOD0 : MOD0_OFF,
774 MOD1 : MOD1_OFF,
775 MOD2 : MOD2_OFF,
776 MOD3 : MOD3_OFF,
777 MOD4 : MOD4_OFF,
778 };
779
780 /*! Unified Clock System Control 1 Register */
781 config UCSCTL1_t UCSCTL1 = {
782 DCORSEL : DCORSEL_2,
783 DISMOD : DISMOD_OFF,
784 };
785
786 /*! Unified Clock System Control 2 Register */
787 config UCSCTL2_t UCSCTL2 = {
788 FLLD : FLLD_1,
789 FLLN0 : FLLN0,
790 FLLN1 : FLLN1,
791 FLLN2 : FLLN2,
792 FLLN3 : FLLN3,
793 FLLN4 : FLLN4,
794 FLLN5 : FLLN5_OFF,
795 FLLN6 : FLLN6_OFF,
796 FLLN7 : FLLN7_OFF,
797 FLLN8 : FLLN8_OFF,
798 FLLN9 : FLLN9_OFF,
799 };
800
801 /*! Unified Clock System Control 3 Register */
802 config UCSCTL3_t UCSCTL3 = {
803 SELREF : SELREF_0,
804 FLLREFDIV : FLLREFDIV_0,
805 };
806
807 /*! Unified Clock System Control 4 Register */
808 config UCSCTL4_t UCSCTL4 = {
809 SELA : SELA_0,
810 SELS : SELS_4,
811 SELM : SELM_4,
812 };
813
814 /*! Unified Clock System Control 5 Register */
815 config UCSCTL5_t UCSCTL5 = {
816 DIVPA : DIVPA_0,
817 DIVA : DIVA_0,
818 DIVS : DIVS_0,
819 DIVM : DIVM_0,
820 };
821
822 /*! Unified Clock System Control 6 Register */
823 config UCSCTL6_t UCSCTL6 = {
824 XT2DRIVE : XT2DRIVE_3,
825 XT2BYPASS : XT2BYPASS_OFF,
826 XT2OFF : XT2OFF,
827 XT1DRIVE : XT1DRIVE_3,
828 XTS : XTS,
829 XT1BYPASS : XT1BYPASS,
830 XCAP : XCAP_3,
831 SMCLKOFF : SMCLKOFF_OFF,
832 XT1OFF : XT1OFF,
833 };
834
835 /*! Unified Clock System Control 7 Register */
836 config UCSCTL7_t UCSCTL7 = {
837 XT2OFFG : XT2OFFG_OFF,
838 XT1HFOFFG : XT1HFOFFG_OFF,
839 XT1LFOFFG : XT1LFOFFG,
840 DCOFFG : DCOFFG,
841 };
842
843 /*! Unified Clock System Control 8 Register */
844 config UCSCTL8_t UCSCTL8 = {
845 MODOSCREQEN : MODOSCREQEN_OFF,
846 SMCLKREQEN : SMCLKREQEN,
847 MCLKREQEN : MCLKREQEN,
848 ACLKREQEN : ACLKREQEN,
849 };
850
851 /*! Unified Clock System Control 9 Register */
852 config UCSCTL9_t UCSCTL9 = {
853 XT2BYPASSLV : XT2BYPASSLV_OFF,
854 XT1BYPASSLV : XT1BYPASSLV_OFF,
855 };
856
857 /*! MCLK clock source select */
858 config UCS_CLK_SOURCE_t UCS_MCLK_SOURCE = UCS_DCOCLKDIV_SELECT;
859
860 /*! SMCLK clock source select */
861 config UCS_CLK_SOURCE_t UCS_SMCLK_SOURCE = UCS_DCOCLKDIV_SELECT;
862
863 /*! ACLK clock source select */
864 config UCS_CLK_SOURCE_t UCS_ACLK_SOURCE = UCS_XT1CLK_SELECT;
865
866 /*! FLL reference clock source select */
867 config UCS_CLK_SOURCE_t UCS_FLL_REF_CLK_SOURCE = UCS_XT1CLK_SELECT;
868
869 /*! MCLK clock source divider select */
870 config UCS_CLK_SRC_DIVIDER_t UCS_MCLK_SRC_DIVIDER = UCS_CLOCK_DIVIDER_1;
871
872 /*! SMCLK clock source divider select */
873 config UCS_CLK_SRC_DIVIDER_t UCS_SMCLK_SRC_DIVIDER = UCS_CLOCK_DIVIDER_1;
874
875 /*! ACLK clock source divider select */
876 config UCS_CLK_SRC_DIVIDER_t UCS_ACLK_SRC_DIVIDER = UCS_CLOCK_DIVIDER_1;
877
878 /*! External pin ACLK clock source divider select */
879 config UCS_CLK_SRC_DIVIDER_t UCS_PACLK_SRC_DIVIDER = UCS_CLOCK_DIVIDER_1;
880
881 /*! FLL reference clock source divider select */
882 config UCS_CLK_SRC_DIVIDER_t UCS_FLL_REF_SRC_DIVIDER = UCS_CLOCK_DIVIDER_1;
883
884 /*! FLLN value */
885 config UInt UCS_FLL_RATIO = 31;
886
887 /*! Set FLL target frequency */
888 config Float UCS_FLL_FREQ = 0;
889
890 /*! Set XT1 drive strength */
891 config XT1DRIVE_t UCS_XT1_DRIVE = XT1DRIVE_3;
892
893 /*! Set XT2 drive strength */
894 config XT2DRIVE_t UCS_XT2_DRIVE = XT2DRIVE_3;
895
896 /*! Set oscillator capacitor. Available only in LF mode. See device-specific datasheet for actual values. */
897 config UCS_XCAP_t UCS_XCAP = UCS_XCAP_3;
898
899 /*! Set XT1 in bypass mode. The frequency input at XIN1 pin requires 0 to VCC. */
900 config Bool UCS_XT1BYPASS = false;
901
902 /*! Set XT2 in bypass mode. The frequency input at XIN2 pin requires 0 to VCC. */
903 config Bool UCS_XT2BYPASS = false;
904
905 /*! MODOSC clock request enable. Setting this enables conditional module requests for MODOSC.
906 * 0 MODOSC conditional requests are disabled.
907 * 1 MODOSC conditional requests are enabled. */
908 config MODOSCREQEN_t UCS_MODOSCREQEN = MODOSCREQEN_OFF;
909
910 /*! SMCLK clock request enable. Setting this enables conditional module requests for SMCLK.
911 * 0 SMCLK conditional requests are disabled.
912 * 1 SMCLK conditional requests are enabled. */
913 config SMCLKREQEN_t UCS_SMCLKREQEN = SMCLKREQEN;
914
915 /*! MCLK clock request enable. Setting this enables conditional module requests for MCLK
916 * 0 MCLK conditional requests are disabled.
917 * 1 MCLK conditional requests are enabled. */
918 config MCLKREQEN_t UCS_MCLKREQEN = MCLKREQEN;
919
920 /*! ACLK clock request enable. Setting this enables conditional module requests for ACLK
921 * 0 ACLK conditional requests are disabled.
922 * 1 ACLK conditional requests are enabled. */
923 config ACLKREQEN_t UCS_ACLKREQEN = ACLKREQEN;
924
925 /*! Turns OFF SMCLK using the SMCLKOFF bit
926 * 0 SMCLK On
927 * 1 SMCLK Off */
928 config Bool UCS_SMCLKOFF = false;
929
930 config Float VLOCLKHz = 12000;
931 config Float WATCHCRYSTALCLKHz = 32768;
932 config Float REFOCLKHz = 32768;
933 config Float XT1CLKHz = 0;
934 config Float XT2CLKHz = 0;
935
936 /*!
937 * ======== DCOCLKDIVHz ========
938 * Divided DCO clock frequency in Hertz
939 */
940 readonly config Float DCOCLKDIVHz;
941
942 /*! Determine if each Register needs to be forced set or not */
943 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
944 [
945 { register : "UCS_SMCLKREQEN" , regForceSet : false },
946 { register : "UCS_MCLKREQEN" , regForceSet : false },
947 { register : "UCS_ACLKREQEN" , regForceSet : false },
948 { register : "UCS_MODOSCREQEN" , regForceSet : false }
949 ];
950 }