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32
33 /*!
34 * ======== Timer3_A2 ========
35 * MSP430 Timer3_A2 timer
36 */
37 metaonly module Timer3_A2 inherits ITimer_A {
38
39 instance:
40 /*! TA3CTL, Timer3_A2 Control Register */
41 config TACTL_t TA3CTL = {
42 TASSEL : TASSEL_0,
43 ID : ID_0,
44 MC : MC_0,
45 TACLR : TACLR_OFF,
46 TAIE : TAIE_OFF,
47 TAIFG : TAIFG_OFF
48 };
49
50 /*! TA3CCTL0, Capture/Compare Control Register 0 */
51 config TACCTLx_t TA3CCTL0 = {
52 CM : CM_0,
53 CCIS : CCIS_0,
54 SCS : SCS_OFF,
55 SCCI : SCCI_OFF,
56 CAP : CAP_OFF,
57 OUTMOD : OUTMOD_0,
58 CCIE : CCIE_OFF,
59 CCI : CCI_OFF,
60 OUT : OUT_OFF,
61 COV : COV_OFF,
62 CCIFG : CCIFG_OFF
63 };
64
65 /*! TA3CCTL1, Capture/Compare Control Register 1 */
66 config TACCTLx_t TA3CCTL1 = {
67 CM : CM_0,
68 CCIS : CCIS_0,
69 SCS : SCS_OFF,
70 SCCI : SCCI_OFF,
71 CAP : CAP_OFF,
72 OUTMOD : OUTMOD_0,
73 CCIE : CCIE_OFF,
74 CCI : CCI_OFF,
75 OUT : OUT_OFF,
76 COV : COV_OFF,
77 CCIFG : CCIFG_OFF
78 };
79
80 /*! TA3CCR0, Timer_A Capture/Compare Register 0 */
81 config Bits16 TA3CCR0 = 0;
82 /*! TA3CCR1, Timer_A Capture/Compare Register 1 */
83 config Bits16 TA3CCR1 = 0;
84
85 /*! Timer interrupt enables */
86 config regIntVect_t interruptSource[3];
87
88 /*! Determine if each Register needs to be forced set or not */
89 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
90 [
91 { register : "TA3CTL" , regForceSet : false },
92 { register : "TA3CCTL0" , regForceSet : false },
93 { register : "TA3CCTL1" , regForceSet : false },
94 { register : "TA3CCR0" , regForceSet : false },
95 { register : "TA3CCR1" , regForceSet : false }
96 ];
97 }