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32
33 import ti.catalog.msp430.peripherals.clock.IClock;
34
35 /*!
36 * Universal Serial Communication Interface B1 SPI 2xx
37 */
38 metaonly module USCI_B1_SPI_2xx inherits IUSCI_B1_SPI {
39 40 41
42 create(IClock.Instance clock);
43
44 /*! USCI_B1 transmit interrupt enable */
45 enum UCB1TXIE_t {
46 UCB1TXIE_OFF = 0x00, /*! Interrupt disabled */
47 UCB1TXIE = 0x08 /*! Interrupt enabled */
48 };
49
50 /*! USCI_B1 receive interrupt enable */
51 enum UCB1RXIE_t {
52 UCB1RXIE_OFF = 0x00, /*! Interrupt disabled */
53 UCB1RXIE = 0x04 /*! Interrupt enabled */
54 };
55
56 /*! USCI_xx SPI Interrupt Enable Register */
57 struct UC1IE_t {
58 UCB1TXIE_t UCB1TXIE; /*! USCI_B1 transmit interrupt enable
59 * 0 Interrupt disabled
60 * 1 Interrupt enabled */
61 UCB1RXIE_t UCB1RXIE; /*! USCI_B1 receive interrupt enable
62 * 0 Interrupt disabled
63 * 1 Interrupt enabled */
64 }
65
66 instance:
67 /*! @_nodoc */
68 config IClock.Instance clock;
69
70 /*! USCI_B1 Interrupt Enable Register */
71 config UC1IE_t UC1IE = {
72 UCB1TXIE : UCB1TXIE_OFF,
73 UCB1RXIE : UCB1RXIE_OFF
74 };
75
76 /*! USCI_A1 SPI interrupt enables */
77 config regIntVect_t interruptSource[2];
78
79 /*! Determine if each Register needs to be forced set or not */
80 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
81 [
82 { register : "UCB1CTL0" , regForceSet : false },
83 { register : "UCB1CTL1" , regForceSet : false },
84 { register : "UCB1BR0" , regForceSet : false },
85 { register : "UCB1BR1" , regForceSet : false },
86 { register : "UCB1STAT" , regForceSet : false },
87 { register : "UCB1RXBUF" , regForceSet : false },
88 { register : "UCB1TXBUF" , regForceSet : false },
89 { register : "UC1IE" , regForceSet : false }
90 ];
91 }