1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    import ti.catalog.msp430.peripherals.clock.IClock;
    34    
    35    /*!
    36     * Universal Serial Interface
    37     */
    38    metaonly module USI inherits IUSI {
    39        /*
    40         *  ======== create ========
    41         */
    42        create(IClock.Instance clock);
    43    
    44    instance:
    45        /*! @_nodoc */
    46        config IClock.Instance clock;
    47    
    48        /*! USI Control Register 0 */
    49        config USICTL0_t USICTL0 = {
    50            USIPE7      : USIPE7_OFF,
    51            USIPE6      : USIPE6_OFF,
    52            USIPE5      : USIPE5_OFF,
    53            USILSB      : USILSB_OFF,
    54            USIMST      : USIMST_OFF,
    55            USIGE       : USIGE_OFF,
    56            USIOE       : USIOE_OFF,
    57            USISWRST    : USISWRST,
    58        };
    59    
    60        /*! USI Control Register 1 */
    61        config USICTL1_t USICTL1 = {
    62            USICKPH     : USICKPH_OFF,
    63            USII2C      : USII2C_OFF,
    64            USISTTIE    : USISTTIE_OFF,
    65            USIIE       : USIIE_OFF,
    66            USIAL       : USIAL_OFF,
    67            USISTP      : USISTP_OFF,
    68            USISTTIFG   : USISTTIFG_OFF,
    69            USIIFG      : USIIFG,
    70        };
    71    
    72        /*! USI Clock Control Register */
    73        config USICKCTL_t USICKCTL = {
    74            USIDIV      : USIDIV_0,
    75            USISSEL     : USISSEL_0,
    76            USICKPL     : USICKPL_OFF,
    77            USISWCLK    : USISWCLK_OFF,
    78        };
    79    
    80        /*! USI Bit Counter Register */
    81        config USICNT_t USICNT = {
    82            USISCLREL   : USISCLREL_OFF,
    83            USI16B      : USI16B_OFF,
    84            USIIFGCC    : USIIFGCC_OFF,
    85            USICNT4     : USICNT4_OFF,
    86            USICNT3     : USICNT3_OFF,
    87            USICNT2     : USICNT2_OFF,
    88            USICNT1     : USICNT1_OFF,
    89            USICNT0     : USICNT0_OFF,
    90        };
    91    
    92        /*! USI interrupt enables */
    93        config regIntVect_t interruptSource[2];
    94    
    95        /*! Determine if each Register needs to be forced set or not */
    96        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
    97        [
    98            { register : "USICTL0"    , regForceSet : false },
    99            { register : "USICTL1"    , regForceSet : false },
   100            { register : "USICKCTL"   , regForceSet : false },
   101            { register : "USICNT"     , regForceSet : false }
   102        ];
   103    }