1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    
    34    import ti.catalog.msp430.peripherals.timer.Timer_A3;
    35    import ti.catalog.msp430.peripherals.timer.Timer_B3;
    36    import ti.catalog.msp430.peripherals.clock.BCSplus;
    37    import ti.catalog.msp430.peripherals.communication.USCI_A0_UART_2xx;
    38    import ti.catalog.msp430.peripherals.communication.USCI_A0_SPI_2xx;
    39    import ti.catalog.msp430.peripherals.communication.USCI_B0_SPI_2xx;
    40    import ti.catalog.msp430.peripherals.communication.USCI_B0_I2C_2xx;
    41    import ti.catalog.msp430.peripherals.adc.ADC10;
    42    import ti.catalog.msp430.peripherals.watchdog.WDTplus;
    43    import ti.catalog.msp430.peripherals.oa.OA_2;
    44    import ti.catalog.msp430.peripherals.gpio.GPIO_MSP430F22x4;
    45    import ti.catalog.msp430.peripherals.memory.Flash_2xx;
    46    import ti.catalog.msp430.peripherals.special_function.IE1;
    47    import ti.catalog.msp430.peripherals.special_function.IE2;
    48    import ti.catalog.msp430.peripherals.interrupt.Interrupt_Controller;
    49    
    50    /*!
    51     *  ======== IMSP430x22xx.xdc ========
    52     *  Common definition for MSP430x22xx devices
    53     */
    54    metaonly interface IMSP430x22xx inherits ti.catalog.msp430.IMSP430
    55    {
    56    
    57    instance:
    58    
    59        config Timer_A3.Instance timer_A3;
    60        config Timer_B3.Instance timer_B3;
    61        config BCSplus.Instance clock;
    62        config USCI_A0_UART_2xx.Instance usci_A0_UART;
    63        config USCI_A0_SPI_2xx.Instance usci_A0_SPI;
    64        config USCI_B0_SPI_2xx.Instance usci_B0_SPI;
    65        config USCI_B0_I2C_2xx.Instance usci_B0_I2C;
    66        config ADC10.Instance adc10;
    67        config WDTplus.Instance wdtPlus;
    68        config OA_2.Instance oa;
    69        config GPIO_MSP430F22x4.Instance gpio;
    70        config Flash_2xx.Instance flash;
    71        config IE1.Instance interruptEnableRegister1;
    72        config IE2.Instance interruptEnableRegister2;
    73        config Interrupt_Controller.Instance interruptController;
    74    
    75        /*!
    76         *  ======== commonMap ========
    77         *  Memory map elements shared by all MSP430x22xx devices
    78         */
    79        config xdc.platform.IPlatform.Memory commonMap[string]  = [
    80            ["PERIPHERALS_8BIT", {
    81                comment:    "Memory mapped I/O registers",
    82                name:       "PERIPHERALS_8BIT",
    83                base:       0x0010,
    84                len:        0x00F0,
    85                space:      "io",
    86                access:     "RW"
    87            }],
    88    
    89            ["PERIPHERALS_16BIT", {
    90                comment:    "Memory mapped I/O registers",
    91                name:       "PERIPHERALS_16BIT",
    92                base:       0x0100,
    93                len:        0x0100,
    94                space:      "io",
    95                access:     "RW"
    96            }],
    97    
    98            ["BSLSKEY", {
    99                comment:    "Boot loader security key",
   100                name:       "BSLSKEY",
   101                base:       0xFFDE,
   102                len:        0x0002,
   103                space:      "data",
   104                access:     "RI"
   105            }],
   106    
   107            ["INT00", {
   108                comment:    "Reserved Vector (int00)",
   109                name:       "INT00",
   110                base:       0xFFE0,
   111                len:        0x0002,
   112                space:      "data",
   113                access:     "RW"
   114            }],
   115    
   116            ["INT01", {
   117                comment:    "Reserved Vector (int01)",
   118                name:       "INT01",
   119                base:       0xFFE2,
   120                len:        0x0002,
   121                space:      "data",
   122                access:     "RW"
   123            }],
   124    
   125            ["INT02", {
   126                comment:    "I/O Port P1 Vector (int02)",
   127                name:       "INT02",
   128                base:       0xFFE4,
   129                len:        0x0002,
   130                space:      "data",
   131                access:     "RW"
   132            }],
   133    
   134            ["INT03", {
   135                comment:    "I/O Port P2 Vector (int03)",
   136                name:       "INT03",
   137                base:       0xFFE6,
   138                len:        0x0002,
   139                space:      "data",
   140                access:     "RW"
   141            }],
   142    
   143            ["INT04", {
   144                comment:    "Reserved Vector (int04)",
   145                name:       "INT04",
   146                base:       0xFFE8,
   147                len:        0x0002,
   148                space:      "data",
   149                access:     "RW"
   150            }],
   151    
   152            ["INT05", {
   153                comment:    "ADC10 Vector (int05)",
   154                name:       "INT05",
   155                base:       0xFFEA,
   156                len:        0x0002,
   157                space:      "data",
   158                access:     "RW"
   159            }],
   160    
   161            ["INT06", {
   162                comment:    "USCI_A0/B0 Transmit Vector (int06)",
   163                name:       "INT06",
   164                base:       0xFFEC,
   165                len:        0x0002,
   166                space:      "data",
   167                access:     "RW"
   168            }],
   169    
   170            ["INT07", {
   171                comment:    "USCI_A0/B0 Receive Vector (int07)",
   172                name:       "INT07",
   173                base:       0xFFEE,
   174                len:        0x0002,
   175                space:      "data",
   176                access:     "RW"
   177            }],
   178    
   179            ["INT08", {
   180                comment:    "Timer_A3 TBCCR1 Vector (int08)",
   181                name:       "INT08",
   182                base:       0xFFF0,
   183                len:        0x0002,
   184                space:      "data",
   185                access:     "RW"
   186            }],
   187    
   188            ["INT09", {
   189                comment:    "Timer_A3 TBCCR0 Vector (int09)",
   190                name:       "INT09",
   191                base:       0xFFF2,
   192                len:        0x0002,
   193                space:      "data",
   194                access:     "RW"
   195            }],
   196    
   197            ["INT10", {
   198                comment:    "Watchdog Vector (int10)",
   199                name:       "INT10",
   200                base:       0xFFF4,
   201                len:        0x0002,
   202                space:      "data",
   203                access:     "RW"
   204            }],
   205    
   206            ["INT11", {
   207                comment:    "Reserved Vector (int11)",
   208                name:       "INT11",
   209                base:       0xFFF6,
   210                len:        0x0002,
   211                space:      "data",
   212                access:     "RW"
   213            }],
   214    
   215            ["INT12", {
   216                comment:    "Timer_B3 TBCCR1 Vector (int12)",
   217                name:       "INT12",
   218                base:       0xFFF8,
   219                len:        0x0002,
   220                space:      "data",
   221                access:     "RW"
   222            }],
   223    
   224            ["INT13", {
   225                comment:    "Timer_B3 TBCCR0 Vector (int13)",
   226                name:       "INT13",
   227                base:       0xFFFA,
   228                len:        0x0002,
   229                space:      "data",
   230                access:     "RW"
   231            }],
   232    
   233            ["INT14", {
   234                comment:    "NMI Vector (int14)",
   235                name:       "INT14",
   236                base:       0xFFFC,
   237                len:        0x0002,
   238                space:      "data",
   239                access:     "RW"
   240            }],
   241    
   242            ["RESET", {
   243                comment:    "Reset Vector (int15)",
   244                name:       "RESET",
   245                base:       0xFFFE,
   246                len:        0x0002,
   247                space:      "data",
   248                access:     "RW"
   249            }],
   250    
   251            ["INFOA", {
   252                comment:    "INFO Flash Memory Segment A",
   253                name:       "INFOA",
   254                base:       0x10C0,
   255                len:        0x0040,
   256                space:      "data",
   257                access:     "RW"
   258            }],
   259    
   260            ["INFOB", {
   261                comment:    "INFO Flash Memory Segment B",
   262                name:       "INFOB",
   263                base:       0x1080,
   264                len:        0x0040,
   265                space:      "data",
   266                access:     "RW"
   267            }],
   268    
   269            ["INFOC", {
   270                comment:    "INFO Flash Memory Segment C",
   271                name:       "INFOC",
   272                base:       0x1040,
   273                len:        0x0040,
   274                space:      "data",
   275                access:     "RW"
   276            }],
   277    
   278            ["INFOD", {
   279                comment:    "INFO Flash Memory Segment D",
   280                name:       "INFOD",
   281                base:       0x1000,
   282                len:        0x0040,
   283                space:      "data",
   284                access:     "RW"
   285            }],
   286        ];
   287    }