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32
33 /*!
34 * ======== IUSI ========
35 * Universal Serial Interface
36 */
37 metaonly interface IUSI inherits xdc.platform.IPeripheral {
38 39 40
41
42 /*! USI SDI/SDA port enable.
43 *Input in SPI mode, input or open drain output in I2C mode. */
44 enum USIPE7_t {
45 USIPE7_OFF = 0x00, /*! USI function disabled */
46 USIPE7 = 0x80 /*! USI function enabled */
47 };
48
49 /*! USI SDO/SCL port enable.
50 *Output in SPI mode, input or open drain output in I2C mode. */
51 enum USIPE6_t {
52 USIPE6_OFF = 0x00, /*! USI function disabled */
53 USIPE6 = 0x40 /*! USI function enabled */
54 };
55
56 /*! USI SCLK port enable.
57 *Input in SPI slave mode, or I2C mode, output in SPI master mode. */
58 enum USIPE5_t {
59 USIPE5_OFF = 0x00, /*! USI function disabled */
60 USIPE5 = 0x20 /*! USI function enabled */
61 };
62
63 /*! LSB first select. This bit controls the direction of the receive and transmit shift register. */
64 enum USILSB_t {
65 USILSB_OFF = 0x00, /*! MSB first */
66 USILSB = 0x10 /*! LSB first */
67 };
68
69 /*! Master select */
70 enum USIMST_t {
71 USIMST_OFF = 0x00, /*! Slave mode */
72 USIMST = 0x08 /*! Master mode */
73 };
74
75 /*! Output latch control */
76 enum USIGE_t {
77 USIGE_OFF = 0x00, /*! Output latch enable depends on shift clock */
78 USIGE = 0x04 /*! Output latch always enabled and transparent */
79 };
80
81 /*! Data output enable */
82 enum USIOE_t {
83 USIOE_OFF = 0x00, /*! Output disabled */
84 USIOE = 0x02 /*! Output enabled */
85 };
86
87 /*! USI software reset */
88 enum USISWRST_t {
89 USISWRST_OFF = 0x00, /*! USI released for operation. */
90 USISWRST = 0x01 /*! USI logic held in reset state. */
91 };
92
93 /*! Clock phase select */
94 enum USICKPH_t {
95 USICKPH_OFF = 0x00, /*! Data is changed on the first SCLK edge and captured on the following edge. */
96 USICKPH = 0x80 /*! Data is captured on the first SCLK edge and changed on the following edge. */
97 };
98
99 /*! I2C mode enable */
100 enum USII2C_t {
101 USII2C_OFF = 0x00, /*! I2C mode disabled */
102 USII2C = 0x40 /*! I2C mode enabled */
103 };
104
105 /*! START condition interrupt-enable */
106 enum USISTTIE_t {
107 USISTTIE_OFF = 0x00, /*! Interrupt on START condition disabled */
108 USISTTIE = 0x20 /*! Interrupt on START condition enabled */
109 };
110
111 /*! USI counter interrupt enable */
112 enum USIIE_t {
113 USIIE_OFF = 0x00, /*! Interrupt disabled */
114 USIIE = 0x10 /*! Interrupt enabled */
115 };
116
117 /*! Arbitration lost */
118 enum USIAL_t {
119 USIAL_OFF = 0x00, /*! No arbitration lost condition */
120 USIAL = 0x08 /*! Arbitration lost */
121 };
122
123 /*! STOP condition received. USISTP is automatically cleared if USICNTx is
124 *loaded with a value > 0 when USIIFGCC = 0. */
125 enum USISTP_t {
126 USISTP_OFF = 0x00, /*! No STOP condition received */
127 USISTP = 0x04 /*! STOP condition received */
128 };
129
130 /*! START condition interrupt flag */
131 enum USISTTIFG_t {
132 USISTTIFG_OFF = 0x00, /*! No START condition received. No interrupt pending. */
133 USISTTIFG = 0x02 /*! START condition received. Interrupt pending. */
134 };
135
136 /*! USI counter interrupt flag. Set when the USICNTx = 0. Automatically
137 *cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. */
138 enum USIIFG_t {
139 USIIFG_OFF = 0x00, /*! No interrupt pending */
140 USIIFG = 0x01 /*! Interrupt pending */
141 };
142
143 /*! Clock divider select */
144 enum USIDIV_t {
145 USIDIV_0 = 0x00, /*! Divide by 1 */
146 USIDIV_1 = 0x20, /*! Divide by 2 */
147 USIDIV_2 = 0x40, /*! Divide by 4 */
148 USIDIV_3 = 0x60, /*! Divide by 8 */
149 USIDIV_4 = 0x80, /*! Divide by 16 */
150 USIDIV_5 = 0xA0, /*! Divide by 32 */
151 USIDIV_6 = 0xC0, /*! Divide by 64 */
152 USIDIV_7 = 0xE0 /*! Divide by 128 */
153 };
154
155 /*! Clock source select. Not used in slave mode. */
156 enum USISSEL_t {
157 USISSEL_0 = 0x00, /*! SCLK (Not used in SPI mode) */
158 USISSEL_1 = 0x04, /*! ACLK */
159 USISSEL_2 = 0x08, /*! SMCLK */
160 USISSEL_3 = 0x0C, /*! SMCLK */
161 USISSEL_4 = 0x10, /*! USISWCLK bit */
162 USISSEL_5 = 0x14, /*! TACCR0 */
163 USISSEL_6 = 0x18, /*! TACCR1 */
164 USISSEL_7 = 0x1C /*! TACCR2 (Reserved on MSP430F20xx devices) */
165 };
166
167 /*! Clock polarity select */
168 enum USICKPL_t {
169 USICKPL_OFF = 0x00, /*! Inactive state is low */
170 USICKPL = 0x02 /*! Inactive state is high */
171 };
172
173 /*! Software clock */
174 enum USISWCLK_t {
175 USISWCLK_OFF = 0x00, /*! Input clock is low */
176 USISWCLK = 0x01 /*! Input clock is high */
177 };
178
179 /*! SCL release. The SCL line is released from low to idle. USISCLREL is
180 *cleared if a START condition is detected. */
181 enum USISCLREL_t {
182 USISCLREL_OFF = 0x00, /*! SCL line is held low if USIIFG is set */
183 USISCLREL = 0x80 /*! SCL line is released */
184 };
185
186 /*! 16-bit shift register enable */
187 enum USI16B_t {
188 USI16B_OFF = 0x00, /*! 8-bit shift register mode. Low byte register USISRL is used. */
189 USI16B = 0x40 /*! 16-bit shift register mode. Both high and low byte registers USISRL
190 *and USISRH are used. USISR addresses all 16 bits simultaneously. */
191 };
192
193 /*! USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be
194 *cleared automatically when USICNTx is written with a value > 0. */
195 enum USIIFGCC_t {
196 USIIFGCC_OFF = 0x00, /*! USIIFG automatically cleared on USICNTx update */
197 USIIFGCC = 0x20 /*! USIIFG is not cleared automatically */
198 };
199
200 /*! USI bit count - Bit4 */
201 enum USICNT4_t {
202 USICNT4_OFF = 0x00, /*! USI bit count */
203 USICNT4 = 0x10 /*! USI bit count */
204 };
205
206 /*! USI bit count - Bit3 */
207 enum USICNT3_t {
208 USICNT3_OFF = 0x00, /*! USI bit count */
209 USICNT3 = 0x08 /*! USI bit count */
210 };
211
212 /*! USI bit count - Bit2 */
213 enum USICNT2_t {
214 USICNT2_OFF = 0x00, /*! USI bit count */
215 USICNT2 = 0x04 /*! USI bit count */
216 };
217
218 /*! USI bit count - Bit1 */
219 enum USICNT1_t {
220 USICNT1_OFF = 0x00, /*! USI bit count */
221 USICNT1 = 0x02 /*! USI bit count */
222 };
223
224 /*! USI bit count - Bit0 */
225 enum USICNT0_t {
226 USICNT0_OFF = 0x00, /*! USI bit count */
227 USICNT0 = 0x01 /*! USI bit count */
228 };
229
230 struct USICTL0_t {
231 USIPE7_t USIPE7; /*! USI SDI/SDA port enable.
232 *Input in SPI mode, input or open drain output in I2C mode.
233 * 0 USI function disabled
234 * 1 USI function enabled */
235 USIPE6_t USIPE6; /*! USI SDO/SCL port enable.
236 *Output in SPI mode, input or open drain output in I2C mode.
237 * 0 USI function disabled
238 * 1 USI function enabled */
239 USIPE5_t USIPE5; /*! USI SCLK port enable.
240 *Input in SPI slave mode, or I2C mode, output in SPI master mode.
241 * 0 USI function disabled
242 * 1 USI function enabled */
243 USILSB_t USILSB; /*! LSB first select. This bit controls the direction of the receive and transmit shift register.
244 * 0 MSB first
245 * 1 LSB first */
246 USIMST_t USIMST; /*! Master select
247 * 0 Slave mode
248 * 1 Master mode */
249 USIGE_t USIGE; /*! Output latch control
250 * 0 Output latch enable depends on shift clock
251 * 1 Output latch always enabled and transparent */
252 USIOE_t USIOE; /*! Data output enable
253 * 0 Output disabled
254 * 1 Output enabled */
255 USISWRST_t USISWRST; /*! USI software reset
256 * 0 USI released for operation.
257 * 1 USI logic held in reset state. */
258 }
259
260 struct USICTL1_t {
261 USICKPH_t USICKPH; /*! Clock phase select
262 * 0 Data is changed on the first SCLK edge and captured on the
263 * following edge.
264 * 1 Data is captured on the first SCLK edge and changed on the
265 * following edge. */
266 USII2C_t USII2C; /*! I2C mode enable
267 * 0 I2C mode disabled
268 * 1 I2C mode enabled*/
269 USISTTIE_t USISTTIE; /*! START condition interrupt-enable
270 * 0 Interrupt on START condition disabled
271 * 1 Interrupt on START condition enabled */
272 USIIE_t USIIE; /*! USI counter interrupt enable
273 * 0 Interrupt disabled
274 * 1 Interrupt enabled */
275 USIAL_t USIAL; /*! Arbitration lost
276 * 0 No arbitration lost condition
277 * 1 Arbitration lost */
278 USISTP_t USISTP; /*! STOP condition received. USISTP is automatically cleared if USICNTx is
279 *loaded with a value > 0 when USIIFGCC = 0.
280 * 0 No STOP condition received
281 * 1 STOP condition received */
282 USISTTIFG_t USISTTIFG; /*! START condition interrupt flag
283 * 0 No START condition received. No interrupt pending.
284 * 1 START condition received. Interrupt pending. */
285 USIIFG_t USIIFG; /*! USI counter interrupt flag. Set when the USICNTx = 0. Automatically
286 *cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0.
287 * 0 No interrupt pending
288 * 1 Interrupt pending */
289 }
290
291 struct USICKCTL_t {
292 USIDIV_t USIDIV; /*! Clock divider select
293 * 000 Divide by 1
294 * 001 Divide by 2
295 * 010 Divide by 4
296 * 011 Divide by 8
297 * 100 Divide by 16
298 * 101 Divide by 32
299 * 110 Divide by 64
300 * 111 Divide by 128 */
301 USISSEL_t USISSEL; /*! Clock source select. Not used in slave mode.
302 * 000 SCLK (Not used in SPI mode)
303 * 001 ACLK
304 * 010 SMCLK
305 * 011 SMCLK
306 * 100 USISWCLK bit
307 * 101 TACCR0
308 * 110 TACCR1
309 * 111 TACCR2 (Reserved on MSP430F20xx devices) */
310 USICKPL_t USICKPL; /*! Clock polarity select
311 * 0 Inactive state is low
312 * 1 Inactive state is high */
313 USISWCLK_t USISWCLK; /*! Software clock
314 * 0 Input clock is low
315 * 1 Input clock is high */
316 }
317
318 struct USICNT_t {
319 USISCLREL_t USISCLREL; /*! SCL release. The SCL line is released from low to idle. USISCLREL is
320 * cleared if a START condition is detected.
321 * 0 SCL line is held low if USIIFG is set
322 * 1 SCL line is released */
323 USI16B_t USI16B; /*! 16-bit shift register enable
324 * 0 8-bit shift register mode. Low byte register USISRL is used.
325 * 1 16-bit shift register mode. Both high and low byte registers USISRL
326 * and USISRH are used. USISR addresses all 16 bits simultaneously.*/
327 USIIFGCC_t USIIFGCC; /*! USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be
328 *cleared automatically when USICNTx is written with a value > 0.
329 * 0 USIIFG automatically cleared on USICNTx update
330 * 1 USIIFG is not cleared automatically */
331 USICNT4_t USICNT4; /*! USI bit count bit 4
332 *The USICNTx bits set the number of bits to be received or transmitted. */
333 USICNT3_t USICNT3; /*! USI bit count bit 3
334 *The USICNTx bits set the number of bits to be received or transmitted. */
335 USICNT2_t USICNT2; /*! USI bit count bit 2
336 *The USICNTx bits set the number of bits to be received or transmitted. */
337 USICNT1_t USICNT1; /*! USI bit count bit 1
338 *The USICNTx bits set the number of bits to be received or transmitted. */
339 USICNT0_t USICNT0; /*! USI bit count bit 0
340 *The USICNTx bits set the number of bits to be received or transmitted. */
341 }
342
343 /*!
344 * ======== ForceSetDefaultRegister_t ========
345 * Force Set Default Register
346 *
347 * Type to store if each register needs to be forced initialized
348 * even if the register is in default state.
349 *
350 * @see #ForceSetDefaultRegister_t
351 */
352 struct ForceSetDefaultRegister_t {
353 String register;
354 Bool regForceSet;
355 }
356
357 /*!
358 * ======== regIntVect_t ========
359 * Interrupt vector description
360 *
361 * Type to describe a single interrupt vector pin and all its possible
362 * configurations.
363 *
364 * @see #regIntVect_t
365 */
366 struct regIntVect_t {
367 String registerName;
368 String registerDescription;
369 String isrToggleString;
370 String priorityName;
371 Bool interruptEnable;
372 Bool interruptHandler;
373 Int priority;
374 }
375
376 instance:
377
378 /*!
379 * ======== setUSIIE ========
380 * Sets USIIE register
381 *
382 * @see #setUSIIE
383 */
384 Bool setUSIIE(Bool set);
385
386 /*!
387 * ======== setUSIIE ========
388 * Gets USIIE register
389 *
390 * @see #setUSIIE
391 */
392 Bool getUSIIE();
393
394 /*!
395 * ======== setUSISTTIE ========
396 * Sets USISTTIE register
397 *
398 * @see #setUSISTTIE
399 */
400 Bool setUSISTTIE(Bool set);
401
402 /*!
403 * ======== getUSISTTIE ========
404 * Gets USISTTIE register
405 *
406 * @see #getUSISTTIE
407 */
408 Bool getUSISTTIE();
409 }