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32
33 import ti.catalog.msp430.peripherals.clock.IClock;
34
35 /*!
36 * Universal Serial Communication Interface
37 */
38 metaonly module USCI_A1_UART_2xx inherits IUSCI_A1_UART {
39
40
41 42 43
44 create(IClock.Instance clock);
45
46 /*! USCI_A1 transmit interrupt enable */
47 enum UCA1TXIE_t {
48 UCA1TXIE_OFF = 0x00, /*! Interrupt disabled */
49 UCA1TXIE = 0x02 /*! Interrupt enabled */
50 };
51
52 /*! USCI_A1 receive interrupt enable */
53 enum UCA1RXIE_t {
54 UCA1RXIE_OFF = 0x00, /*! Interrupt disabled */
55 UCA1RXIE = 0x01 /*! Interrupt enabled */
56 };
57
58 /*! USCI_Ax UART Interrupt Enable Register */
59 struct UC1IE_t {
60 UCA1TXIE_t UCA1TXIE; /*! USCI_A1 transmit interrupt enable
61 * 0 Interrupt disabled
62 * 1 Interrupt enabled */
63 UCA1RXIE_t UCA1RXIE; /*! USCI_A1 receive interrupt enable
64 * 0 Interrupt disabled
65 * 1 Interrupt enabled */
66 }
67
68 instance:
69 /*! @_nodoc */
70 config IClock.Instance clock;
71
72 /*! USCI_A1 Interrupt Enable Register */
73 config UC1IE_t UC1IE = {
74 UCA1TXIE : UCA1TXIE_OFF,
75 UCA1RXIE : UCA1RXIE_OFF
76 };
77
78 /*! USCI_A1 UART interrupt enables */
79 config regIntVect_t interruptSource[2];
80
81 /*! Determine if each Register needs to be forced set or not */
82 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
83 [
84 { register : "UCA1CTL0" , regForceSet : false },
85 { register : "UCA1CTL1" , regForceSet : false },
86 { register : "UCA1BR0" , regForceSet : false },
87 { register : "UCA1BR1" , regForceSet : false },
88 { register : "UCA1MCTL" , regForceSet : false },
89 { register : "UCA1STAT" , regForceSet : false },
90 { register : "UCA1RXBUF" , regForceSet : false },
91 { register : "UCA1TXBUF" , regForceSet : false },
92 { register : "UCA1ABCTL" , regForceSet : false },
93 { register : "UCA1IRTCTL" , regForceSet : false },
94 { register : "UCA1IRRCTL" , regForceSet : false },
95 { register : "UC1IE" , regForceSet : false }
96 ];
97 }