1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*!
    34     *  ======== SR ========
    35     *  MSP430 Status Register
    36     */
    37    metaonly module SR inherits xdc.platform.IPeripheral {
    38    
    39        /* System clock generator 1. This bit, when set, turns off the SMCLK. */
    40        enum SCG1_t {
    41            SCG1_OFF   = 0x0000,              /*! Disable System clock generator 1 */
    42            SCG1       = 0x0080               /*! Enable System clock generator 1 */
    43        };
    44    
    45        enum SCG0_t {
    46            SCG0_OFF   = 0x0000,              /*! Disable System clock generator 0 */
    47            SCG0       = 0x0040               /*! Enable System clock generator 0 */
    48        };
    49    
    50        enum OSCOFF_t {
    51            OSCOFF_OFF = 0x0000,              /*! Oscillator On */
    52            OSCOFF     = 0x0020               /*! Oscillator Off */
    53        };
    54    
    55        /* CPU off. This bit, when set, turns off the CPU. */
    56        enum CPUOFF_t {
    57            CPUOFF_OFF = 0x0000,              /*! CPU On */
    58            CPUOFF     = 0x0010               /*! CPU Off */
    59        };
    60    
    61        enum GIE_t {
    62            GIE_OFF    = 0x0000,              /*! General interrupt disable */
    63            GIE        = 0x0008               /*! General interrupt enable */
    64        };
    65    
    66        /* SR */
    67        struct SR_t {
    68            SCG1_t      SCG1;                 /*! System clock generator 1
    69                                               *This bit, when set, turns off the SMCLK.
    70                                               */
    71            SCG0_t      SCG0;                 /*! System clock generator 0
    72                                               *This bit, when set, turns off the DCO dc
    73                                               *generator, if DCOCLK is not used for MCLK
    74                                               *or SMCLK.
    75                                               */
    76            OSCOFF_t    OSCOFF;               /*!Oscillator Off
    77                                               *This bit, when set, turns off the LFXT1
    78                                               *crystal oscillator, when LFXT1CLK is not
    79                                               *use for MCLK or SMCLK
    80                                               */
    81            CPUOFF_t    CPUOFF;               /*! CPU off
    82                                               *This bit, when set, turns off the CPU.
    83                                               */
    84            GIE_t       GIE;                  /*! General interrupt enable
    85                                               *This bit, when set, enables maskable
    86                                               *interrupts. When reset, all maskable
    87                                               *interrupts are disabled
    88                                               */
    89        }
    90    
    91       /*!
    92        *  ======== ForceSetDefaultRegister_t ========
    93        *  Force Set Default Register
    94        *
    95        *  Type to store if each register needs to be forced initialized
    96        *  even if the register is in default state.
    97        *
    98        *  @see #ForceSetDefaultRegister_t
    99        */
   100        struct ForceSetDefaultRegister_t {
   101            String     register;
   102            Bool       regForceSet;
   103        }
   104    
   105    instance:
   106        /*! SR, Status Register */
   107        config SR_t SR = {
   108            SCG1        : SCG1_OFF,
   109            SCG0        : SCG0_OFF,
   110            OSCOFF      : OSCOFF_OFF,
   111            CPUOFF      : CPUOFF_OFF,
   112            GIE         : GIE_OFF
   113        };
   114    
   115       /*!
   116        *  ======== getSCG1 ========
   117        *  Gets SCG1 bit
   118        *
   119        *  @see #getSCG1
   120        */
   121        Bool    getSCG1();
   122    
   123       /*!
   124        *  ======== setSCG1 ========
   125        *  Sets SCG1 bit
   126        *
   127        *  @see #setSCG1
   128        */
   129        Bool    setSCG1(Bool set);
   130    
   131       /*!
   132        *  ======== getSCG0 ========
   133        *  Gets SCG0 bit
   134        *
   135        *  @see #getSCG0
   136        */
   137        Bool    getSCG0();
   138    
   139       /*!
   140        *  ======== setSCG0 ========
   141        *  Sets SCG0 bit
   142        *
   143        *  @see #setSCG0
   144        */
   145        Bool    setSCG0(Bool set);
   146    
   147       /*!
   148        *  ======== getOSCOFF ========
   149        *  Gets OSCOFF bit
   150        *
   151        *  @see #getOSCOFF
   152        */
   153        Bool    getOSCOFF();
   154    
   155       /*!
   156        *  ======== setOSCOFF ========
   157        *  Sets OSCOFF bit
   158        *
   159        *  @see #setOSCOFF
   160        */
   161        Bool    setOSCOFF(Bool set);
   162    
   163        /*!
   164        *  ======== getCPUOFF ========
   165        *  Gets CPUOFF bit
   166        *
   167        *  @see #getCPUOFF
   168        */
   169        Bool    getCPUOFF();
   170    
   171       /*!
   172        *  ======== setCPUOFF ========
   173        *  Sets CPUOFF bit
   174        *
   175        *  @see #setCPUOFF
   176        */
   177        Bool    setCPUOFF(Bool set);
   178    
   179        /*!
   180        *  ======== getGIE ========
   181        *  Gets GIE bit
   182        *
   183        *  @see #getGIE
   184        */
   185        Bool    getGIE();
   186    
   187       /*!
   188        *  ======== setGIE ========
   189        *  Sets GIE bit
   190        *
   191        *  @see #setGIE
   192        */
   193        Bool    setGIE(Bool set);
   194    
   195        /*! Determine if each Register needs to be forced set or not */
   196        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   197        [
   198            { register : "SR" , regForceSet : false },
   199        ];
   200    }