1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*!
    34     *  ======== IUSCI ========
    35     *  Universal Serial Communication Interface
    36     */
    37    metaonly interface IUSCI inherits xdc.platform.IPeripheral {
    38        /*****************************************************************
    39         * REGISTER BIT DEFINITIONS                                      *
    40         *****************************************************************/
    41    
    42        /*! MSB first select. Controls the direction of the receive and transmit shift register. */
    43        enum UCMSB_t {
    44            UCMSB_OFF = 0x00,       /*! LSB first */
    45            UCMSB = 0x02            /*! MSB first */
    46        };
    47    
    48        /*! Character length. Selects 7-bit or 8-bit character length. */
    49        enum UC7BIT_t {
    50            UC7BIT_OFF = 0x00,      /*! 8-bit */
    51            UC7BIT = 0x02           /*! 7-bit */
    52        };
    53    
    54        /*! Synchronous mode enable */
    55        enum UCSYNC_t {
    56            UCSYNC_OFF = 0x00,      /*! Asynchronous mode */
    57            UCSYNC = 0x02           /*! Synchronous Mode */
    58        };
    59    
    60        /*! Receive erroneous-character interrupt-enable */
    61        enum UCRXEIE_t {
    62            UCRXEIE_OFF = 0x00,     /*! Erroneous characters rejected and UCAxRXIFG is not set */
    63            UCRXEIE = 0x02          /*! Erroneous characters received will set UCAxRXIFG */
    64        };
    65    
    66        /*! Receive break character interrupt-enable */
    67        enum UCBRKIE_t {
    68            UCBRKIE_OFF = 0x00,     /*! Received break characters do not set UCAxRXIFG. */
    69            UCBRKIE = 0x02          /*! Received break characters set UCAxRXIFG. */
    70        };
    71    
    72        /*! Dormant. Puts USCI into sleep mode. */
    73        enum UCDORM_t {
    74            UCDORM_OFF = 0x00,      /*! Not dormant. All received characters will set UCAxRXIFG. */
    75            UCDORM = 0x02           /*! Dormant. Only characters that are preceded by an idle-line or with
    76                                     * address bit set will set UCAxRXIFG. In UART mode with automatic baud
    77                                     * rate detection only the combination of a break and synch field will set
    78                                     * UCAxRXIFG. */
    79        };
    80    
    81        /*! Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode. */
    82        enum UCTXADDR_t {
    83            UCTXADDR_OFF = 0x00,    /*! Next frame transmitted is data */
    84            UCTXADDR = 0x02         /*! Next frame transmitted is an address */
    85        };
    86    
    87        /*! Transmit break. Transmits a break with the next write to the transmit buffer.
    88         * In UART mode with automatic baud rate detection 055h must be written
    89         * into UCAxTXBUF to generate the required break/synch fields. Otherwise
    90         * 0h must be written into the transmit buffer. */
    91        enum UCTXBRK_t {
    92            UCTXBRK_OFF = 0x00,     /*! Next frame transmitted is not a break */
    93            UCTXBRK = 0x02          /*! Next frame transmitted is a break or a break/synch */
    94        };
    95    
    96        /*! Software reset enable */
    97        enum UCSWRST_t {
    98            UCSWRST_OFF = 0x00,     /*! Disabled. USCI reset released for operation. */
    99            UCSWRST = 0x02          /*! Enabled. USCI logic held in reset state. */
   100        };
   101    
   102        /*! Listen enable. The UCLISTEN bit selects loopback mode. */
   103        enum UCLISTEN_t {
   104            UCLISTEN_OFF = 0x00,   /*! Disabled. */
   105            UCLISTEN = 0x02        /*! Enabled. UCAxTXD is internally fed back to the receiver. */
   106        };
   107    
   108        /*! Framing error flag */
   109        enum UCFE_t {
   110            UCFE_OFF = 0x00,        /*! 0 No error */
   111            UCFE = 0x02             /*! Character received with low stop bit */
   112        };
   113    
   114        /*! Overrun error flag. */
   115        enum UCOE_t {
   116            UCOE_OFF = 0x00,        /*! No error. */
   117            UCOE = 0x02             /*! Overrun error occurred. */
   118        };
   119    
   120        /*! Parity error flag. When UCPEN = 0, UCPE is read as 0. */
   121        enum UCPE_t {
   122            UCPE_OFF = 0x00,        /*! No error. */
   123            UCPE = 0x02             /*! Character received with parity error. */
   124        };
   125    
   126        /*! Break detect flag */
   127        enum UCBRK_t {
   128            UCBRK_OFF = 0x00,       /*! No break condition */
   129            UCBRK = 0x02            /*! Break condition occurred */
   130        };
   131    
   132        /*!  Bit 2 Receive error flag. This bit indicates a character was received with error(s).
   133         * When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also
   134         * set. UCRXERR is cleared when UCAxRXBUF is read. */
   135        enum UCRXERR_t {
   136            UCRXERR_OFF = 0x00,     /*! No receive errors detected */
   137            UCRXERR = 0x02          /*! Receive error detected */
   138        };
   139    
   140        /*! Address received in address-bit multiprocessor mode. */
   141        enum UCADDR_t {
   142            UCADDR_OFF = 0x00,      /*! Received character is data */
   143            UCADDR = 0x02           /*! Received character is an address */
   144        };
   145    
   146        /*!  Idle line detected in idle-line multiprocessor mode. */
   147        enum UCIDLE_t {
   148            UCIDLE_OFF = 0x00,      /*! No idle line detected */
   149            UCIDLE = 0x02           /*! Idle line detected */
   150        };
   151    
   152        /*! USCI busy. This bit indicates if a transmit or receive operation is in progress. */
   153        enum UCBUSY_t {
   154            UCBUSY_OFF = 0x00,      /*! USCI inactive */
   155            UCBUSY = 0x01           /*! USCI transmitting or receiving */
   156        };
   157    
   158        /*! USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. */
   159        enum UCMODE_SYNC_t {
   160            UCMODE_0 = 0x00,        /*! 3-Pin SPI */
   161            UCMODE_1 = 0x01,        /*! 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1 */
   162            UCMODE_2 = 0x02,        /*! 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0 */
   163            UCMODE_3 = 0x04         /*! I2C Mode */
   164        };
   165    
   166        /*!
   167        *  ======== regIntVect_t ========
   168        *  Interrupt vector description
   169        *
   170        *  Type to describe a single interrupt vector pin and all its possible
   171        *  configurations.
   172        *
   173        *  @see #regIntVect_t
   174        */
   175        struct regIntVect_t {
   176            String                    registerName;
   177            String                    registerDescription;
   178            String                    isrToggleString;
   179            String                    priorityName;
   180            Bool                      interruptEnable;
   181            Bool                      interruptHandler;
   182            Int                       priority;
   183        }
   184    
   185        /*!
   186        *  ======== ForceSetDefaultRegister_t ========
   187        *  Force Set Default Register
   188        *
   189        *  Type to store if each register needs to be forced initialized
   190        *  even if the register is in default state.
   191        *
   192        *  @see #ForceSetDefaultRegister_t
   193        */
   194        struct ForceSetDefaultRegister_t {
   195            String     register;
   196            Bool       regForceSet;
   197        }
   198    
   199    instance:
   200        /*!
   201         * Stores the UCLK external clock frequency in float
   202         */
   203        config float UCLKHz = 1000000;
   204    
   205        /*!
   206        *  ======== setUCxxBR0 ========
   207        *  Sets UCxxBR0 register value based on which module
   208        *
   209        *  @see #setUCxxBR0
   210        */
   211        void setUCxxBR0(Bits8 value);
   212    
   213        /*!
   214        *  ======== getUCxxBR0 ========
   215        *  Returns UCxxBR0 register value based on which module
   216        *
   217        *  @see #getUCxxBR0
   218        */
   219        Bits8 getUCxxBR0();
   220    
   221        /*!
   222        *  ======== setUCxxBR1 ========
   223        *  Sets UCxxBR1 register value based on which module
   224        *
   225        *  @see #setUCxxBR1
   226        */
   227        void setUCxxBR1(Bits8 value);
   228    
   229        /*!
   230        *  ======== getUCxxBR1 ========
   231        *  Returns UCxxBR1 register value based on which module
   232        *
   233        *  @see #getUCxxBR1
   234        */
   235        Bits8 getUCxxBR1();
   236    
   237        /*!
   238         *  ======== getUCxxTXIE ========
   239         *  Gets UCxxTXIE bit
   240         *
   241         *  @see #getUCxxTXIE
   242         */
   243        Bool    getUCxxTXIE();
   244    
   245        /*!
   246         *  ======== setUCxxTXIE ========
   247         *  Sets UCxxTXIE bit
   248         *
   249         *  @see #setUCxxTXIE
   250         */
   251        Bool    setUCxxTXIE(Bool set);
   252    
   253        /*!
   254         *  ======== getUCxxRXIE ========
   255         *  Gets UCxxRXIE bit
   256         *
   257         *  @see #getUCxxRXIE
   258         */
   259        Bool    getUCxxRXIE();
   260    
   261        /*!
   262         *  ======== setUCxxRXIE ========
   263         *  Sets UCxxRXIE bit
   264         *
   265         *  @see #setUCxxRXIE
   266         */
   267        Bool    setUCxxRXIE(Bool set);
   268    }