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32
33 /*!
34 * ======== ADC12 ========
35 * MSP430 12-bit Analog to Digital Converter
36 */
37 metaonly module ADC12 inherits IADC {
38
39 /*! SHT1 Bits */
40 enum ADC12SHT1_t {
41 SHT1_0 = (0*0x1000u), /*! 4 ADC12CLK cycles */
42 SHT1_1 = (1*0x1000u), /*! 8 ADC12CLK cycles */
43 SHT1_2 = (2*0x1000u), /*! 16 ADC12CLK cycles */
44 SHT1_3 = (3*0x1000u), /*! 32 ADC12CLK cycles */
45 SHT1_4 = (4*0x1000u), /*! 64 ADC12CLK cycles */
46 SHT1_5 = (5*0x1000u), /*! 96 ADC12CLK cycles */
47 SHT1_6 = (6*0x1000u), /*! 128 ADC12CLK cycles */
48 SHT1_7 = (7*0x1000u), /*! 192 ADC12CLK cycles */
49 SHT1_8 = (8*0x1000u), /*! 256 ADC12CLK cycles */
50 SHT1_9 = (9*0x1000u), /*! 384 ADC12CLK cycles */
51 SHT1_10 = (10*0x1000u), /*! 512 ADC12CLK cycles */
52 SHT1_11 = (11*0x1000u), /*! 768 ADC12CLK cycles */
53 SHT1_12 = 12*0x1000u /*! 1024 ADC12CLK cycles */
54 };
55
56 /*! SHT0 Bits */
57 enum ADC12SHT0_t {
58 SHT0_0 = (0*0x1000u), /*! 4 ADC12CLK cycles */
59 SHT0_1 = (1*0x1000u), /*! 8 ADC12CLK cycles */
60 SHT0_2 = (2*0x1000u), /*! 16 ADC12CLK cycles */
61 SHT0_3 = (3*0x1000u), /*! 32 ADC12CLK cycles */
62 SHT0_4 = (4*0x1000u), /*! 64 ADC12CLK cycles */
63 SHT0_5 = (5*0x1000u), /*! 96 ADC12CLK cycles */
64 SHT0_6 = (6*0x1000u), /*! 128 ADC12CLK cycles */
65 SHT0_7 = (7*0x1000u), /*! 192 ADC12CLK cycles */
66 SHT0_8 = (8*0x1000u), /*! 256 ADC12CLK cycles */
67 SHT0_9 = (9*0x1000u), /*! 384 ADC12CLK cycles */
68 SHT0_10 = (10*0x1000u), /*! 512 ADC12CLK cycles */
69 SHT0_11 = (11*0x1000u), /*! 768 ADC12CLK cycles */
70 SHT0_12 = 12*0x1000u /*! 1024 ADC12CLK cycles */
71 };
72
73 /*! MSC Bit */
74 enum MSC_t {
75 MSC_OFF = 0x000, /*! The sampling timer requires a rising edge of the SHI
76 * signal to trigger each sample-and-conversion */
77 MSC = 0x080 /*! The first rising edge of the SHI signal triggers
78 * the sampling timer, but further sample-and-conversions
79 * are performed automatically as soon as the prior conversion
80 * is completed */
81 };
82
83 /*! REF2_5V Bit */
84 enum REF2_5V_t {
85 REF2_5V_OFF = 0x000, /*! 1.5V */
86 REF2_5V = 0x040 /*! 2.5V */
87 };
88
89 /*! REFON Bit */
90 enum REFON_t {
91 REFON_OFF = 0x000, /*! Reference off */
92 REFON = 0x020 /*! Reference on */
93 };
94
95 /*! ADC12ON Bit */
96 enum ADC12ON_t {
97 ADC12ON_OFF = 0x000, /*! ADC12 off */
98 ADC12ON = 0x010 /*! ADC12 on */
99 };
100
101 /*! ADC12OVIE Bit */
102 enum ADC12OVIE_t {
103 ADC12OVIE_OFF = 0x000, /*! Overflow interrupt disabled */
104 ADC12OVIE = 0x008 /*! Overflow interrupt enabled */
105 };
106
107 /*! ADC12TOVIE Bit */
108 enum ADC12TOVIE_t {
109 ADC12TOVIE_OFF = 0x000, /*! Conversion time overflow interrupt disabled */
110 ADC12TOVIE = 0x004 /*! Conversion time overflow interrupt disabled */
111 };
112
113 /*! ENC Bit */
114 enum ENC_t {
115 ENC_OFF = 0x000, /*! ADC12 disabled */
116 ENC = 0x002 /*! ADC12 enabled */
117 };
118
119 /*! ADC12SC Bit */
120 enum ADC12SC_t {
121 ADC12SC_OFF = 0x000, /*! No sample-and-conversion-start */
122 ADC12SC = 0x001 /*! Start sample-and-conversion */
123 };
124
125 /*! CSTARTADD Bits */
126 enum CSTARTADD_t {
127 CSTARTADD_0 = (0*0x1000u), /*! ADC12MEM0 */
128 CSTARTADD_1 = (1*0x1000u), /*! ADC12MEM1 */
129 CSTARTADD_2 = (2*0x1000u), /*! ADC12MEM2 */
130 CSTARTADD_3 = (3*0x1000u), /*! ADC12MEM3 */
131 CSTARTADD_4 = (4*0x1000u), /*! ADC12MEM4 */
132 CSTARTADD_5 = (5*0x1000u), /*! ADC12MEM5 */
133 CSTARTADD_6 = (6*0x1000u), /*! ADC12MEM6 */
134 CSTARTADD_7 = (7*0x1000u), /*! ADC12MEM7 */
135 CSTARTADD_8 = (8*0x1000u), /*! ADC12MEM8 */
136 CSTARTADD_9 = (9*0x1000u), /*! ADC12MEM9 */
137 CSTARTADD_10 = (10*0x1000u), /*! ADC12MEM10 */
138 CSTARTADD_11 = (11*0x1000u), /*! ADC12MEM11 */
139 CSTARTADD_12 = (12*0x1000u), /*! ADC12MEM12 */
140 CSTARTADD_13 = (13*0x1000u), /*! ADC12MEM13 */
141 CSTARTADD_14 = (14*0x1000u), /*! ADC12MEM14 */
142 CSTARTADD_15 = 15*0x1000u /*! ADC12MEM15 */
143 };
144
145 /*! SHS Bits */
146 enum SHS_t {
147 SHS_0 = (0*0x400u), /*! ADC12SC bit */
148 SHS_1 = (1*0x400u), /*! Timer_A.OUT1 */
149 SHS_2 = (2*0x400u), /*! Timer_B.OUT0 */
150 SHS_3 = 3*0x400u /*! Timer_B.OUT1 */
151 };
152
153 /*! SHP Bits */
154 enum SHP_t {
155 SHP_OFF = 0x0000, /*! SAMPCON signal is sourced from the sample-input signal */
156 SHP = 0x0200 /*! SAMPCON signal is sourced from the sampling timer. */
157 };
158
159 /*! ISSH Bits */
160 enum ISSH_t {
161 ISSH_OFF = 0x0000, /*! The sample-input signal is not inverted */
162 ISSH = 0x0100 /*! The sample-input signal is inverted */
163 };
164
165
166 /*! ADC12DIV Bits */
167 enum ADC12DIV_t {
168 ADC12DIV_0 = (0*0x20u), /*! Divide by 1 */
169 ADC12DIV_1 = (1*0x20u), /*! Divide by 2 */
170 ADC12DIV_2 = (2*0x20u), /*! Divide by 3 */
171 ADC12DIV_3 = (3*0x20u), /*! Divide by 4 */
172 ADC12DIV_4 = (4*0x20u), /*! Divide by 5 */
173 ADC12DIV_5 = (5*0x20u), /*! Divide by 6 */
174 ADC12DIV_6 = (6*0x20u), /*! Divide by 7 */
175 ADC12DIV_7 = 7*0x20u /*! Divide by 8 */
176 };
177
178 /*! ADC12SSEL Bits */
179 enum ADC12SSEL_t {
180 ADC12SSEL_0 = (0*8u), /*! ADC12OSC */
181 ADC12SSEL_1 = (1*8u), /*! ACLK */
182 ADC12SSEL_2 = (2*8u), /*! MCLK */
183 ADC12SSEL_3 = 3*8u /*! SMCLK */
184 };
185
186 /*! CONSEQ Bits */
187 enum CONSEQ_t {
188 CONSEQ_0 = (0*2u), /*! Single channel single conversion */
189 CONSEQ_1 = (1*2u), /*! Sequence of channels */
190 CONSEQ_2 = (2*2u), /*! Repeat single channel */
191 CONSEQ_3 = 3*2u /*! Repeat sequence of channels */
192 };
193
194 /*! ADC12 Busy Bit */
195 enum ADC12BUSY_t {
196 ADC12BUSY_OFF = 0x0000,
197 ADC12BUSY = 0x0001
198 };
199
200 /*! EOS Bit */
201 enum EOS_t {
202 EOS_OFF = 0x0000, /*! Not end of sequence */
203 EOS = 0x0080 /*! End of sequence */
204 };
205
206 /*! SREF Bits */
207 enum SREF_t {
208 SREF_0 = (0*0x10u), /*! VR+ = AVcc and VR-- = AVss */
209 SREF_1 = (1*0x10u), /*! VR+ = VREF+ and VR-- = AVss */
210 SREF_2 = (2*0x10u), /*! VR+ = VeREF+ and VR-- = AVss */
211 SREF_3 = (3*0x10u), /*! VR+ = VeREF+ and VR-- = AVss */
212 SREF_4 = (4*0x10u), /*! VR+ = AVcc and VR-- = VREF--/ VeREF-- */
213 SREF_5 = (5*0x10u), /*! VR+ = VREF+ and VR-- = VREF--/ VeREF-- */
214 SREF_6 = (6*0x10u), /*! VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
215 SREF_7 = 7*0x10u /*! VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
216 };
217
218 /*! ADC12 Interrupt Enable Bit 15 */
219 enum ADC12IE15_t {
220 ADC12IE15_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG15 bit */
221 ADC12IE15 = 0x8000 /*! Enable the interrupt request for the ADC12IFG15 bit */
222 };
223
224 /*! ADC12 Interrupt Enable Bit 14 */
225 enum ADC12IE14_t {
226 ADC12IE14_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG14 bit */
227 ADC12IE14 = 0x4000 /*! Enable the interrupt request for the ADC12IFG14 bit */
228 };
229
230 /*! ADC12 Interrupt Enable Bit 13 */
231 enum ADC12IE13_t {
232 ADC12IE13_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG13 bit */
233 ADC12IE13 = 0x2000 /*! Enable the interrupt request for the ADC12IFG13 bit */
234 };
235
236 /*! ADC12 Interrupt Enable Bit 12 */
237 enum ADC12IE12_t {
238 ADC12IE12_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG12 bit */
239 ADC12IE12 = 0x1000 /*! Enable the interrupt request for the ADC12IFG12 bit */
240 };
241
242 /*! ADC12 Interrupt Enable Bit 11 */
243 enum ADC12IE11_t {
244 ADC12IE11_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG11 bit */
245 ADC12IE11 = 0x0800 /*! Enable the interrupt request for the ADC12IFG11 bit */
246 };
247
248 /*! ADC12 Interrupt Enable Bit 10 */
249 enum ADC12IE10_t {
250 ADC12IE10_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG10 bit */
251 ADC12IE10 = 0x0400 /*! Enable the interrupt request for the ADC12IFG10 bit */
252 };
253
254 /*! ADC12 Interrupt Enable Bit 9 */
255 enum ADC12IE9_t {
256 ADC12IE9_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG9 bit */
257 ADC12IE9 = 0x0200 /*! Enable the interrupt request for the ADC12IFG9 bit */
258 };
259
260 /*! ADC12 Interrupt Enable Bit 8 */
261 enum ADC12IE8_t {
262 ADC12IE8_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG8 bit */
263 ADC12IE8 = 0x0100 /*! Enable the interrupt request for the ADC12IFG8 bit */
264 };
265
266 /*! ADC12 Interrupt Enable Bit 7 */
267 enum ADC12IE7_t {
268 ADC12IE7_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG7 bit */
269 ADC12IE7 = 0x0080 /*! Enable the interrupt request for the ADC12IFG7 bit */
270 };
271
272 /*! ADC12 Interrupt Enable Bit 6 */
273 enum ADC12IE6_t {
274 ADC12IE6_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG6 bit */
275 ADC12IE6 = 0x0040 /*! Enable the interrupt request for the ADC12IFG6 bit */
276 };
277
278 /*! ADC12 Interrupt Enable Bit 5 */
279 enum ADC12IE5_t {
280 ADC12IE5_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG5 bit */
281 ADC12IE5 = 0x0020 /*! Enable the interrupt request for the ADC12IFG5 bit */
282 };
283
284 /*! ADC12 Interrupt Enable Bit 4 */
285 enum ADC12IE4_t {
286 ADC12IE4_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG4 bit */
287 ADC12IE4 = 0x0010 /*! Enable the interrupt request for the ADC12IFG4 bit */
288 };
289
290 /*! ADC12 Interrupt Enable Bit 3 */
291 enum ADC12IE3_t {
292 ADC12IE3_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG3 bit */
293 ADC12IE3 = 0x0008 /*! Enable the interrupt request for the ADC12IFG3 bit */
294 };
295
296 /*! ADC12 Interrupt Enable Bit 2 */
297 enum ADC12IE2_t {
298 ADC12IE2_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG2 bit */
299 ADC12IE2 = 0x0004 /*! Enable the interrupt request for the ADC12IFG2 bit */
300 };
301
302 /*! ADC12 Interrupt Enable Bit 1 */
303 enum ADC12IE1_t {
304 ADC12IE1_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG1 bit */
305 ADC12IE1 = 0x0002 /*! Enable the interrupt request for the ADC12IFG1 bit */
306 };
307
308 /*! ADC12 Interrupt Enable Bit 0 */
309 enum ADC12IE0_t {
310 ADC12IE0_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG0 bit */
311 ADC12IE0 = 0x0001 /*! Enable the interrupt request for the ADC12IFG0 bit */
312 };
313
314 /*! INCH Bits */
315 enum INCH_t {
316 INCH_0 = (0), /*! A0 */
317 INCH_1 = (1), /*! A1 */
318 INCH_2 = (2), /*! A2 */
319 INCH_3 = (3), /*! A3 */
320 INCH_4 = (4), /*! A4 */
321 INCH_5 = (5), /*! A5 */
322 INCH_6 = (6), /*! A6 */
323 INCH_7 = (7), /*! A7 */
324 INCH_8 = (8), /*! VeREF+ */
325 INCH_9 = (9), /*! VREF--/VeREF- */
326 INCH_10 = (10), /*! Temperature diode */
327 INCH_11 = (11), /*! (AVcc - AVss) / 2 */
328 INCH_12 = (12), /*! GND */
329 INCH_13 = (13), /*! GND */
330 INCH_14 = (14), /*! GND */
331 INCH_15 = 15 /*! GND */
332 };
333
334
335 /*! ADC12IV Definitions */
336 enum ADC12IV_t {
337 ADC12IV_NONE = (0x0000), /*! No Interrupt pending */
338 ADC12IV_ADC12OVIFG = (0x0002), /*! ADC12OVIFG */
339 ADC12IV_ADC12TOVIFG = (0x0004), /*! ADC12TOVIFG */
340 ADC12IV_ADC12IFG0 = (0x0006), /*! ADC12IFG0 */
341 ADC12IV_ADC12IFG1 = (0x0008), /*! ADC12IFG1 */
342 ADC12IV_ADC12IFG2 = (0x000A), /*! ADC12IFG2 */
343 ADC12IV_ADC12IFG3 = (0x000C), /*! ADC12IFG3 */
344 ADC12IV_ADC12IFG4 = (0x000E), /*! ADC12IFG4 */
345 ADC12IV_ADC12IFG5 = (0x0010), /*! ADC12IFG5 */
346 ADC12IV_ADC12IFG6 = (0x0012), /*! ADC12IFG6 */
347 ADC12IV_ADC12IFG7 = (0x0014), /*! ADC12IFG7 */
348 ADC12IV_ADC12IFG8 = (0x0016), /*! ADC12IFG8 */
349 ADC12IV_ADC12IFG9 = (0x0018), /*! ADC12IFG9 */
350 ADC12IV_ADC12IFG10 = (0x001A), /*! ADC12IFG10 */
351 ADC12IV_ADC12IFG11 = (0x001C), /*! ADC12IFG11 */
352 ADC12IV_ADC12IFG12 = (0x001E), /*! ADC12IFG12 */
353 ADC12IV_ADC12IFG13 = (0x0020), /*! ADC12IFG13 */
354 ADC12IV_ADC12IFG14 = (0x0022), /*! ADC12IFG14 */
355 ADC12IV_ADC12IFG15 = 0x0024 /*! ADC12IFG15 */
356 };
357
358 /*! ADC12 Control Register 0 */
359 struct ADC12CTL0_t {
360 ADC12SHT1_t ADC12SHT1; /*! Sample-and-hold time. These bits define the number
361 * of ADC12CLK cycles in the sampling period for registers
362 * ADC12MEM8 to ADC12MEM15. */
363 ADC12SHT0_t ADC12SHT0; /*! Sample-and-hold time. These bits define the number
364 * of ADC12CLK cycles in the sampling period for registers
365 * ADC12MEM0 to ADC12MEM7. */
366 MSC_t MSC; /*! Multiple sample and conversion. Valid only for sequence
367 * or repeated modes.
368 * 0 The sampling timer requires a rising edge of the SHI signal
369 * to trigger each sample-and-conversion.
370 * 1 The first rising edge of the SHI signal triggers the sampling
371 * timer, but further sample-and-conversions are performed
372 * automatically as soon as the prior conversion is completed. */
373 REF2_5V_t REF2_5V; /*! Reference generator voltage. REFON must also be set.
374 * 0 1.5V
375 * 1 2.5V */
376 REFON_t REFON; /*! Reference generator on
377 * 0 Reference off
378 * 1 Reference on */
379 ADC12ON_t ADC12ON; /*! ADC12 on
380 * 0 ADC12 off
381 * 1 ADC12 on */
382 ADC12OVIE_t ADC12OVIE; /*! ADC12MEMx overflow-interrupt enable. The GIE bit must also be
383 * set to enable the interrupt.
384 * 0 Overflow interrupt disabled
385 * 1 Overflow interrupt enabled */
386 ADC12TOVIE_t ADC12TOVIE; /*! ADC12 conversion-time-overflow interrupt enable.
387 * The GIE bit must also be set to enable the interrupt.
388 * 0 Conversion time overflow interrupt disabled
389 * 1 Conversion time overflow interrupt enabled */
390 ENC_t ENC; /*! Enable conversion
391 * 0 ADC12 disabled
392 * 1 ADC12 enabled */
393 ADC12SC_t ADC12SC; /*! Start conversion. Software-controlled sample-and-conversion start.
394 * ADC12SC and ENC may be set together with one instruction. ADC12SC is
395 * reset automatically.
396 * 0 No sample-and-conversion-start
397 * 1 Start sample-and-conversion */
398 };
399
400 /*! ADC12 Control Register 1 */
401 struct ADC12CTL1_t {
402 CSTARTADD_t CSTARTADD; /*! Conversion start address. These bits select which ADC12
403 * conversion-memory register is used for a single conversion or for the first
404 * conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh,
405 * corresponding to ADC12MEM0 to ADC12MEM15. */
406 SHS_t SHS; /*! Sample-and-hold source select
407 * 00 ADC12SC bit
408 * 01 Timer_A.OUT1
409 * 10 Timer_B.OUT0
410 * 11 Timer_B.OUT1 */
411 SHP_t SHP; /*! Sample-and-hold pulse-mode select. This bit selects the source of the
412 * sampling signal (SAMPCON) to be either the output of the sampling timer or
413 * the sample-input signal directly.
414 * 0 SAMPCON signal is sourced from the sample-input signal.
415 * 1 SAMPCON signal is sourced from the sampling timer. */
416 ISSH_t ISSH; /*! Invert signal sample-and-hold
417 * 0 The sample-input signal is not inverted.
418 * 1 The sample-input signal is inverted. */
419 ADC12DIV_t ADC12DIV; /*! ADC12 clock divider
420 * 000 /1
421 * 001 /2
422 * 010 /3
423 * 011 /4
424 * 100 /5
425 * 101 /6
426 * 110 /7
427 * 111 /8 */
428 ADC12SSEL_t ADC12SSEL; /*! ADC12 clock source select
429 * 00 ADC12OSC
430 * 01 ACLK
431 * 10 MCLK
432 * 11 SMCLK */
433 CONSEQ_t CONSEQ; /*! Conversion sequence mode select
434 * 00 Single-channel, single-conversion
435 * 01 Sequence-of-channels
436 * 10 Repeat-single-channel
437 * 11 Repeat-sequence-of-channels */
438 ADC12BUSY_t ADC12BUSY; /*! ADC12 busy. This bit indicates an active sample or conversion operation.
439 * 0 No operation is active.
440 * 1 A sequence, sample, or conversion is active. */
441 };
442
443 /*! ADC12 Conversion Memory Control Registers */
444 struct ADC12MCTL_t {
445 EOS_t EOS; /*! End of sequence. Indicates the last conversion in a sequence.
446 * 0 Not end of sequence
447 * 1 End of sequence */
448 SREF_t SREF; /*! Select reference
449 * 000 VR+ = AVCC and VR-- = AVSS
450 * 001 VR+ = VREF+ and VR-- = AVSS
451 * 010 VR+ = VeREF+ and VR-- = AVSS
452 * 011 VR+ = VeREF+ and VR-- = AVSS
453 * 100 VR+ = AVCC and VR-- = VREF--/ VeREF--
454 * 101 VR+ = VREF+ and VR-- = VREF--/ VeREF--
455 * 110 VR+ = VeREF+ and VR-- = VREF--/ VeREF--
456 * 111 VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
457 INCH_t INCH; /*! Input channel select
458 * 0000 A0
459 * 0001 A1
460 * 0010 A2
461 * 0011 A3
462 * 0100 A4
463 * 0101 A5
464 * 0110 A6
465 * 0111 A7
466 * 1000 VeREF+
467 * 1001 VREF--/VeREF--
468 * 1010 Temperature diode
469 * 1011 (AVCC ??? AVSS) /
470 * 1100 GND
471 * 1101 GND
472 * 1110 GND
473 * 1111 GND */
474 };
475
476 /*! ADC12 Interrupt Enable Register */
477 struct ADC12IE_t {
478 ADC12IE15_t ADC12IE15; /*! Enable or disable the interrupt request for the ADC12IFG15 bit.
479 * 0 Interrupt disabled
480 * 1 Interrupt enabled */
481 ADC12IE14_t ADC12IE14; /*! Enable or disable the interrupt request for the ADC12IFG14 bit.
482 * 0 Interrupt disabled
483 * 1 Interrupt enabled */
484 ADC12IE13_t ADC12IE13; /*! Enable or disable the interrupt request for the ADC12IFG13 bit.
485 * 0 Interrupt disabled
486 * 1 Interrupt enabled */
487 ADC12IE12_t ADC12IE12; /*! Enable or disable the interrupt request for the ADC12IFG12 bit.
488 * 0 Interrupt disabled
489 * 1 Interrupt enabled */
490 ADC12IE11_t ADC12IE11; /*! Enable or disable the interrupt request for the ADC12IFG11 bit.
491 * 0 Interrupt disabled
492 * 1 Interrupt enabled */
493 ADC12IE10_t ADC12IE10; /*! Enable or disable the interrupt request for the ADC12IFG10 bit.
494 * 0 Interrupt disabled
495 * 1 Interrupt enabled */
496 ADC12IE9_t ADC12IE9; /*! Enable or disable the interrupt request for the ADC12IFG9 bit.
497 * 0 Interrupt disabled
498 * 1 Interrupt enabled */
499 ADC12IE8_t ADC12IE8; /*! Enable or disable the interrupt request for the ADC12IFG8 bit.
500 * 0 Interrupt disabled
501 * 1 Interrupt enabled */
502 ADC12IE7_t ADC12IE7; /*! Enable or disable the interrupt request for the ADC12IFG7 bit.
503 * 0 Interrupt disabled
504 * 1 Interrupt enabled */
505 ADC12IE6_t ADC12IE6; /*! Enable or disable the interrupt request for the ADC12IFG6 bit.
506 * 0 Interrupt disabled
507 * 1 Interrupt enabled */
508 ADC12IE5_t ADC12IE5; /*! Enable or disable the interrupt request for the ADC12IFG5 bit.
509 * 0 Interrupt disabled
510 * 1 Interrupt enabled */
511 ADC12IE4_t ADC12IE4; /*! Enable or disable the interrupt request for the ADC12IFG4 bit.
512 * 0 Interrupt disabled
513 * 1 Interrupt enabled */
514 ADC12IE3_t ADC12IE3; /*! Enable or disable the interrupt request for the ADC12IFG3 bit.
515 * 0 Interrupt disabled
516 * 1 Interrupt enabled */
517 ADC12IE2_t ADC12IE2; /*! Enable or disable the interrupt request for the ADC12IFG2 bit.
518 * 0 Interrupt disabled
519 * 1 Interrupt enabled */
520 ADC12IE1_t ADC12IE1; /*! Enable or disable the interrupt request for the ADC12IFG1 bit.
521 * 0 Interrupt disabled
522 * 1 Interrupt enabled */
523 ADC12IE0_t ADC12IE0; /*! Enable or disable the interrupt request for the ADC12IFG0 bit.
524 * 0 Interrupt disabled
525 * 1 Interrupt enabled */
526 };
527
528 instance:
529 /*! ADC12CTL0 Register */
530 config ADC12CTL0_t ADC12CTL0 = {
531 ADC12SHT1 : SHT1_0,
532 ADC12SHT0 : SHT0_0,
533 MSC : MSC_OFF,
534 REF2_5V : REF2_5V_OFF,
535 REFON : REFON_OFF,
536 ADC12ON : ADC12ON_OFF,
537 ADC12OVIE : ADC12OVIE_OFF,
538 ADC12TOVIE : ADC12TOVIE_OFF,
539 ENC : ENC_OFF,
540 ADC12SC : ADC12SC_OFF
541 };
542
543 /*! ADC12CTL1 Register */
544 config ADC12CTL1_t ADC12CTL1 = {
545 CSTARTADD : CSTARTADD_0,
546 SHS : SHS_0,
547 SHP : SHP_OFF,
548 ISSH : ISSH_OFF,
549 ADC12DIV : ADC12DIV_0,
550 ADC12SSEL : ADC12SSEL_0,
551 CONSEQ : CONSEQ_0,
552 ADC12BUSY : ADC12BUSY_OFF
553 };
554
555 /*! ADC12MCTL0 Register */
556 config ADC12MCTL_t ADC12MCTL0 = {
557 EOS : EOS_OFF,
558 SREF : SREF_0,
559 INCH : INCH_0
560 };
561
562 /*! ADC12MCTL1 Register */
563 config ADC12MCTL_t ADC12MCTL1 = {
564 EOS : EOS_OFF,
565 SREF : SREF_0,
566 INCH : INCH_0
567 };
568
569 /*! ADC12MCTL2 Register */
570 config ADC12MCTL_t ADC12MCTL2 = {
571 EOS : EOS_OFF,
572 SREF : SREF_0,
573 INCH : INCH_0
574 };
575
576 /*! ADC12MCTL3 Register */
577 config ADC12MCTL_t ADC12MCTL3 = {
578 EOS : EOS_OFF,
579 SREF : SREF_0,
580 INCH : INCH_0
581 };
582
583 /*! ADC12MCTL4 Register */
584 config ADC12MCTL_t ADC12MCTL4 = {
585 EOS : EOS_OFF,
586 SREF : SREF_0,
587 INCH : INCH_0
588 };
589
590 /*! ADC12MCTL5 Register */
591 config ADC12MCTL_t ADC12MCTL5 = {
592 EOS : EOS_OFF,
593 SREF : SREF_0,
594 INCH : INCH_0
595 };
596
597 /*! ADC12MCTL6 Register */
598 config ADC12MCTL_t ADC12MCTL6 = {
599 EOS : EOS_OFF,
600 SREF : SREF_0,
601 INCH : INCH_0
602 };
603
604 /*! ADC12MCTL7 Register */
605 config ADC12MCTL_t ADC12MCTL7 = {
606 EOS : EOS_OFF,
607 SREF : SREF_0,
608 INCH : INCH_0
609 };
610
611 /*! ADC12MCTL8 Register */
612 config ADC12MCTL_t ADC12MCTL8 = {
613 EOS : EOS_OFF,
614 SREF : SREF_0,
615 INCH : INCH_0
616 };
617
618 /*! ADC12MCTL9 Register */
619 config ADC12MCTL_t ADC12MCTL9 = {
620 EOS : EOS_OFF,
621 SREF : SREF_0,
622 INCH : INCH_0
623 };
624
625 /*! ADC12MCTL10 Register */
626 config ADC12MCTL_t ADC12MCTL10 = {
627 EOS : EOS_OFF,
628 SREF : SREF_0,
629 INCH : INCH_0
630 };
631
632 /*! ADC12MCTL11 Register */
633 config ADC12MCTL_t ADC12MCTL11 = {
634 EOS : EOS_OFF,
635 SREF : SREF_0,
636 INCH : INCH_0
637 };
638
639 /*! ADC12MCTL12 Register */
640 config ADC12MCTL_t ADC12MCTL12 = {
641 EOS : EOS_OFF,
642 SREF : SREF_0,
643 INCH : INCH_0
644 };
645
646 /*! ADC12MCTL13 Register */
647 config ADC12MCTL_t ADC12MCTL13 = {
648 EOS : EOS_OFF,
649 SREF : SREF_0,
650 INCH : INCH_0
651 };
652
653 /*! ADC12MCTL14 Register */
654 config ADC12MCTL_t ADC12MCTL14 = {
655 EOS : EOS_OFF,
656 SREF : SREF_0,
657 INCH : INCH_0
658 };
659
660 /*! ADC12MCTL15 Register */
661 config ADC12MCTL_t ADC12MCTL15 = {
662 EOS : EOS_OFF,
663 SREF : SREF_0,
664 INCH : INCH_0
665 };
666
667 /*! ADC12 Interrupt Enable Register */
668 config ADC12IE_t ADC12IE = {
669 ADC12IE15 : ADC12IE15_OFF,
670 ADC12IE14 : ADC12IE14_OFF,
671 ADC12IE13 : ADC12IE13_OFF,
672 ADC12IE12 : ADC12IE12_OFF,
673 ADC12IE11 : ADC12IE11_OFF,
674 ADC12IE10 : ADC12IE10_OFF,
675 ADC12IE9 : ADC12IE9_OFF,
676 ADC12IE8 : ADC12IE8_OFF,
677 ADC12IE7 : ADC12IE7_OFF,
678 ADC12IE6 : ADC12IE6_OFF,
679 ADC12IE5 : ADC12IE5_OFF,
680 ADC12IE4 : ADC12IE4_OFF,
681 ADC12IE3 : ADC12IE3_OFF,
682 ADC12IE2 : ADC12IE2_OFF,
683 ADC12IE1 : ADC12IE1_OFF,
684 ADC12IE0 : ADC12IE0_OFF
685 };
686
687
688 /*! ADC12MEM0 Register */
689 config Bits16 ADC12MEM0 = 0;
690
691 /*! ADC12MEM1 Register */
692 config Bits16 ADC12MEM1 = 0;
693
694 /*! ADC12MEM2 Register */
695 config Bits16 ADC12MEM2 = 0;
696
697 /*! ADC12MEM3 Register */
698 config Bits16 ADC12MEM3 = 0;
699
700 /*! ADC12MEM4 Register */
701 config Bits16 ADC12MEM4 = 0;
702
703 /*! ADC12MEM5 Register */
704 config Bits16 ADC12MEM5 = 0;
705
706 /*! ADC12MEM6 Register */
707 config Bits16 ADC12MEM6 = 0;
708
709 /*! ADC12MEM7 Register */
710 config Bits16 ADC12MEM7 = 0;
711
712 /*! ADC12MEM8 Register */
713 config Bits16 ADC12MEM8 = 0;
714
715 /*! ADC12MEM9 Register */
716 config Bits16 ADC12MEM9 = 0;
717
718 /*! ADC12MEM10 Register */
719 config Bits16 ADC12MEM10 = 0;
720
721 /*! ADC12MEM11 Register */
722 config Bits16 ADC12MEM11 = 0;
723
724 /*! ADC12MEM12 Register */
725 config Bits16 ADC12MEM12 = 0;
726
727 /*! ADC12MEM13 Register */
728 config Bits16 ADC12MEM13 = 0;
729
730 /*! ADC12MEM14 Register */
731 config Bits16 ADC12MEM14 = 0;
732
733 /*! ADC12MEM15 Register */
734 config Bits16 ADC12MEM15 = 0;
735
736 /*! ADC12IV Register */
737 config Bits16 ADC12IV = ADC12IV_NONE;
738
739 /*! ADC12IFG Register */
740 config Bits16 ADC12IFG = 0;
741
742 /*! ADC12 has 16 interrupt enable */
743 config regIntVect_t interruptSource[16];
744
745 /*! Determine if each Register needs to be forced set or not */
746 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
747 [
748 { register : "ADC12CTL0" , regForceSet : false },
749 { register : "ADC12CTL1" , regForceSet : false },
750 { register : "ADC12IFG" , regForceSet : false },
751 { register : "ADC12IV" , regForceSet : false },
752 { register : "ADC12IE" , regForceSet : false },
753 { register : "ADC12MCTL0" , regForceSet : false },
754 { register : "ADC12MCTL1" , regForceSet : false },
755 { register : "ADC12MCTL2" , regForceSet : false },
756 { register : "ADC12MCTL3" , regForceSet : false },
757 { register : "ADC12MCTL4" , regForceSet : false },
758 { register : "ADC12MCTL5" , regForceSet : false },
759 { register : "ADC12MCTL6" , regForceSet : false },
760 { register : "ADC12MCTL7" , regForceSet : false },
761 { register : "ADC12MCTL8" , regForceSet : false },
762 { register : "ADC12MCTL9" , regForceSet : false },
763 { register : "ADC12MCTL10" , regForceSet : false },
764 { register : "ADC12MCTL11" , regForceSet : false },
765 { register : "ADC12MCTL12" , regForceSet : false },
766 { register : "ADC12MCTL13" , regForceSet : false },
767 { register : "ADC12MCTL14" , regForceSet : false },
768 { register : "ADC12MCTL15" , regForceSet : false },
769 { register : "ADC12MEM0" , regForceSet : false },
770 { register : "ADC12MEM1" , regForceSet : false },
771 { register : "ADC12MEM2" , regForceSet : false },
772 { register : "ADC12MEM3" , regForceSet : false },
773 { register : "ADC12MEM4" , regForceSet : false },
774 { register : "ADC12MEM5" , regForceSet : false },
775 { register : "ADC12MEM6" , regForceSet : false },
776 { register : "ADC12MEM7" , regForceSet : false },
777 { register : "ADC12MEM8" , regForceSet : false },
778 { register : "ADC12MEM9" , regForceSet : false },
779 { register : "ADC12MEM10" , regForceSet : false },
780 { register : "ADC12MEM11" , regForceSet : false },
781 { register : "ADC12MEM12" , regForceSet : false },
782 { register : "ADC12MEM13" , regForceSet : false },
783 { register : "ADC12MEM14" , regForceSet : false },
784 { register : "ADC12MEM15" , regForceSet : false },
785 ];
786 }