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32
33 34 35
36 package ti.catalog.c2800;
37
38 /*!
39 * ======== ITMS320F28065 ========
40 */
41 metaonly interface ITMS320F28065 inherits ITMS320C283xx
42 {
43 instance:
44 override config string cpuCoreRevision = "1.0";
45
46 /*!
47 * ======== memMap ========
48 * The default memory map for this device
49 */
50 config xdc.platform.IPlatform.Memory memMap[string] = [
51 ["MSARAM", {
52 comment: "On-Chip RAM Memory",
53 name: "MSARAM",
54 base: 0x0,
55 len: 0x800,
56 page: 0,
57 space: "code/data"
58 }],
59
60 ["PIEVECT", {
61 comment: "On-Chip PIEVECT RAM Memory",
62 name: "PIEVECT",
63 base: 0xD00,
64 len: 0x100,
65 page: 1,
66 space: "data"
67 }],
68
69 ["L03DPSARAM", {
70 comment: "L0-L3 DPSARAM (8K x 16)",
71 name: "L03DPSARAM",
72 base: 0x8000,
73 len: 0x2000,
74 page: 0,
75 space: "code/data"
76 }],
77
78 ["L4SARAM", {
79 comment: "L4 SARAM (8K x 16)",
80 name: "L4SARAM",
81 base: 0xA000,
82 len: 0x2000,
83 page: 0,
84 space: "code/data"
85 }],
86
87 88 89
90 ["L56DPSARAM", {
91 comment: "L5-L6 DPSARAM (16K x 16)",
92 name: "L56DPSARAM",
93 base: 0xC000,
94 len: 0x4000,
95 page: 0,
96 space: "code/data"
97 }],
98
99 ["L78DPSARAM", {
100 comment: "L7-L8 DPSARAM (16K x 16)",
101 name: "L78DPSARAM",
102 base: 0x10000,
103 len: 0x04000,
104 page: 0,
105 space: "code/data"
106 }],
107
108 ["OTP", {
109 comment: "1K X 16 OTP memory",
110 name: "OTP",
111 base: 0x3D7800,
112 len: 0x0003FA,
113 page: 0,
114 space: "code"
115 }],
116
117 ["FLASH", {
118 comment: "64K X 16 Flash memory",
119 name: "FLASH",
120 base: 0x3E8000,
121 len: 0x00FF80,
122 page: 0,
123 space: "code"
124 }],
125
126 ["BEGIN", {
127 comment: "FLASH boot entry point",
128 name: "BEGIN",
129 base: 0x3f7ff6,
130 len: 0x000002,
131 page: 0,
132 space: "code"
133 }],
134
135 ["BOOTROM", {
136 comment: "On-Chip Boot ROM",
137 name: "BOOTROM",
138 base: 0x3F8000,
139 len: 0x007FC0,
140 page: 0,
141 space: "code"
142 }],
143 ];
144 }