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37
38 /*!
39 * ======== ITMS320CDRA44x ========
40 * An interface implemented by all DRA44x devices
41 *
42 * This interface is defined to factor common data about all DRA44x devices
43 * into a single place; they are all the same from the configuration point of
44 * view.
45 */
46 metaonly interface ITMS320CDRA44x inherits ti.catalog.ICpuDataSheet
47 {
48 config long cacheSizeL1[string] = [
49 ["0k", 0x0000],
50 ["4k", 0x1000],
51 ["8k", 0x2000],
52 ["16k", 0x4000],
53 ["32k", 0x8000],
54 ];
55
56 config long cacheSizeL2[string] = [
57 ["0k", 0x00000],
58 ["32k", 0x08000],
59 ["64k", 0x10000]
60 ];
61
62 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
63 ['l1PMode',{desc:"L1P Cache",
64 base: 0x11E08000,
65 map : [["0k",0x0000],
66 ["4k",0x1000],
67 ["8k",0x2000],
68 ["16k",0x4000],
69 ["32k",0x8000]],
70 defaultValue: "32k",
71 memorySection: "L1PSRAM"}],
72
73 ['l1DMode',{desc:"L1D Cache",
74 base:0x11F04000,
75 map : [["0k",0x0000],
76 ["4k",0x1000],
77 ["8k",0x2000],
78 ["16k",0x4000],
79 ["32k",0x8000]],
80 defaultValue: "32k",
81 memorySection: "L1DSRAM"}],
82
83 ['l2Mode',{desc:"L2 Cache",
84 base:0x11800000,
85 map : [["0k",0x0000],
86 ["32k",0x8000],
87 ["64k",0x10000]],
88 defaultValue: "0k",
89 memorySection: "IRAM"}]
90
91 ];
92
93 instance:
94
95 override config string cpuCore = "64x+";
96 override config string isa = "64P";
97 override config string cpuCoreRevision = "1.0";
98
99 override config int minProgUnitSize = 1;
100 override config int minDataUnitSize = 1;
101 override config int dataWordSize = 4;
102
103 /*!
104 * ======== memMap ========
105 * The default memory map for this device
106 */
107 config xdc.platform.IPlatform.Memory memMap[string] = [
108 ["IRAM", {
109 comment: "Internal 64KB UMAP0 memory",
110 name: "IRAM",
111 base: 0x11800000,
112 len: 0x00010000,
113 space: "code/data",
114 access: "RWX"
115 }],
116
117 ["L1PSRAM", {
118 comment: "Internal 32KB RAM/CACHE L1 program memory",
119 name: "L1PSRAM",
120 base: 0x11E08000,
121 len: 0x00008000,
122 space: "code",
123 access: "RWX"
124 }],
125
126 ["L1DSRAM", {
127 comment: "Internal 80KB RAM/CACHE L1 data memory",
128 name: "L1DSRAM",
129 base: 0x11F04000,
130 len: 0x00014000,
131 space: "data",
132 access: "RW"
133 }],
134
135 ["ARM_RAM", {
136 comment: "Internal ARM RAM memory",
137 name: "ARM_RAM",
138 base: 0x10008000,
139 len: 0x00004000,
140 space: "data",
141 access: "RW"
142 }],
143 ];
144 };