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32
33 import ti.catalog.msp430.peripherals.communication.USI as USI;
34
35 /*!
36 * ======== GPIO for MSP430G2x21 ========
37 * MSP430 General Purpose Input Output Ports
38 */
39 metaonly module GPIO_MSP430G2x21 inherits IGPIO {
40 /*!
41 * ======== create ========
42 * Create an instance of this peripheral.
43 */
44 create(USI.Instance usi);
45
46 instance:
47 /*! @_nodoc */
48 config USI.Instance usi;
49
50 /*! Define an array to describe all device pins. The 1st dimension
51 * denotes the port, the second the pin on that port. On an
52 * MSP430G2x21 device, there are 8 + 2 = 10 pins total.
53 */
54
55 56
57 58
59 config DevicePin_t devicePins[2][8];
60
61 /*! Implementation of Device Pin Functional Configuration */
62 override config DevicePinFunctionSetting_t devicePinSetting[2][8];
63
64 /*! Determine if each Register needs to be forced set or not */
65 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
66 [
67 { register : "P1OUT" , regForceSet : true },
68 { register : "P1SEL" , regForceSet : false },
69 { register : "P1DIR" , regForceSet : true },
70 { register : "P1REN" , regForceSet : false },
71 { register : "P1IES" , regForceSet : true },
72 { register : "P1IFG" , regForceSet : true },
73 { register : "P1IE" , regForceSet : false },
74 { register : "P2OUT" , regForceSet : true },
75 { register : "P2SEL" , regForceSet : false },
76 { register : "P2DIR" , regForceSet : true },
77 { register : "P2REN" , regForceSet : false },
78 { register : "P2IES" , regForceSet : true },
79 { register : "P2IFG" , regForceSet : true },
80 { register : "P2IE" , regForceSet : false }
81 ];
82
83 84 85 86 87 88
89
90 /*! Port 1 Output Register */
91 config GpioBits8PxOut_t P1OUT = {
92 Bit0 : BIT0_OFF,
93 Bit1 : BIT1_OFF,
94 Bit2 : BIT2_OFF,
95 Bit3 : BIT3_OFF,
96 Bit4 : BIT4_OFF,
97 Bit5 : BIT5_OFF,
98 Bit6 : BIT6_OFF,
99 Bit7 : BIT7_OFF
100 };
101
102 /*! Port 1 Port Select Register */
103 config GpioBits8PxSel_t P1SEL = {
104 Bit0 : BIT0_OFF,
105 Bit1 : BIT1_OFF,
106 Bit2 : BIT2_OFF,
107 Bit3 : BIT3_OFF,
108 Bit4 : BIT4_OFF,
109 Bit5 : BIT5_OFF,
110 Bit6 : BIT6_OFF,
111 Bit7 : BIT7_OFF
112 };
113
114 /*! Port 1 Direction Register */
115 config GpioBits8PxDir_t P1DIR = {
116 Bit0 : BIT0_OFF,
117 Bit1 : BIT1_OFF,
118 Bit2 : BIT2_OFF,
119 Bit3 : BIT3_OFF,
120 Bit4 : BIT4_OFF,
121 Bit5 : BIT5_OFF,
122 Bit6 : BIT6_OFF,
123 Bit7 : BIT7_OFF
124 };
125
126 /*! Port 1 Resistor Enable Register */
127 config GpioBits8PxRen_t P1REN = {
128 Bit0 : BIT0_OFF,
129 Bit1 : BIT1_OFF,
130 Bit2 : BIT2_OFF,
131 Bit3 : BIT3_OFF,
132 Bit4 : BIT4_OFF,
133 Bit5 : BIT5_OFF,
134 Bit6 : BIT6_OFF,
135 Bit7 : BIT7_OFF
136 };
137
138 /*! Port 2 Output Register */
139 config GpioBits8PxOut_t P2OUT = {
140 Bit0 : BIT0_OFF,
141 Bit1 : BIT1_OFF,
142 Bit2 : BIT2_OFF,
143 Bit3 : BIT3_OFF,
144 Bit4 : BIT4_OFF,
145 Bit5 : BIT5_OFF,
146 Bit6 : BIT6_OFF,
147 Bit7 : BIT7_OFF
148 };
149
150 /*! Port 2 Port Select Register */
151 config GpioBits8PxSel_t P2SEL = {
152 Bit0 : BIT0_OFF,
153 Bit1 : BIT1_OFF,
154 Bit2 : BIT2_OFF,
155 Bit3 : BIT3_OFF,
156 Bit4 : BIT4_OFF,
157 Bit5 : BIT5_OFF,
158 Bit6 : BIT6,
159 Bit7 : BIT7
160 };
161
162 /*! Port 2 Direction Register */
163 config GpioBits8PxDir_t P2DIR = {
164 Bit0 : BIT0_OFF,
165 Bit1 : BIT1_OFF,
166 Bit2 : BIT2_OFF,
167 Bit3 : BIT3_OFF,
168 Bit4 : BIT4_OFF,
169 Bit5 : BIT5_OFF,
170 Bit6 : BIT6_OFF,
171 Bit7 : BIT7_OFF
172 };
173
174 /*! Port 2 Resistor Enable Register */
175 config GpioBits8PxRen_t P2REN = {
176 Bit0 : BIT0_OFF,
177 Bit1 : BIT1_OFF,
178 Bit2 : BIT2_OFF,
179 Bit3 : BIT3_OFF,
180 Bit4 : BIT4_OFF,
181 Bit5 : BIT5_OFF,
182 Bit6 : BIT6_OFF,
183 Bit7 : BIT7_OFF
184 };
185 }