1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*!
    34     *  ======== IPinMux ========
    35     */
    36    metaonly interface IPinMux inherits xdc.platform.IPeripheral {
    37    
    38        struct ForceSetDefaultRegister_t {
    39            String     register;
    40            Bool       regForceSet;
    41        }
    42    
    43    instance:
    44        /*! Port 1 Output Register */
    45        config Bits8 p1out = 0;
    46    
    47        /*! Port 1 Port Select Register 0 */
    48        config Bits8 p1sel0 = 0;
    49    
    50        /*! Port 1 Port Select Register 1 */
    51        config Bits8 p1sel1 = 0;
    52    
    53        /*! Port 1 Direction Register */
    54        config Bits8 p1dir = 0;
    55    
    56        /*! Port 1 Resistor Enable Register */
    57        config Bits8 p1ren = 0;
    58    
    59        /*! Port 2 Output Register */
    60        config Bits8 p2out = 0;
    61    
    62        /*! Port 2 Port Select Register 0 */
    63        config Bits8 p2sel0 = 0;
    64    
    65        /*! Port 2 Port Select Register 1 */
    66        config Bits8 p2sel1 = 0;
    67    
    68        /*! Port 2 Direction Register */
    69        config Bits8 p2dir = 0;
    70    
    71        /*! Port 2 Resistor Enable Register */
    72        config Bits8 p2ren = 0;
    73    
    74        /*! Port 3 Output Register */
    75        config Bits8 p3out = 0;
    76    
    77        /*! Port 3 Port Select Register 0 */
    78        config Bits8 p3sel0 = 0;
    79    
    80        /*! Port 3 Port Select Register 1 */
    81        config Bits8 p3sel1 = 0;
    82    
    83        /*! Port 3 Direction Register */
    84        config Bits8 p3dir = 0;
    85    
    86        /*! Port 3 Resistor Enable Register */
    87        config Bits8 p3ren = 0;
    88    
    89        /*! Port 4 Output Register */
    90        config Bits8 p4out = 0;
    91    
    92        /*! Port 4 Port Select Register 0 */
    93        config Bits8 p4sel0 = 0;
    94    
    95        /*! Port 4 Port Select Register 1 */
    96        config Bits8 p4sel1 = 0;
    97    
    98        /*! Port 4 Direction Register */
    99        config Bits8 p4dir = 0;
   100    
   101        /*! Port 4 Resistor Enable Register */
   102        config Bits8 p4ren = 0;
   103    
   104        /*! Port J Output Register */
   105        config Bits8 pjout = 0;
   106    
   107        /*! Port J Port Select Register 0 */
   108        config Bits8 pjsel0 = 0;
   109    
   110        /*! Port J Port Select Register 1 */
   111        config Bits8 pjsel1 = 0;
   112    
   113        /*! Port J Direction Register */
   114        config Bits8 pjdir = 0;
   115    
   116        /*! Port J Resistor Enable Register */
   117        config Bits8 pjren = 0;
   118    
   119        /*! Port 1 Interrupt Enable */
   120        config Bits8 p1ie = 0;
   121    
   122        /*! Port 1 Interrupt Edge Select */
   123        config Bits8 p1ies = 0;
   124    
   125        /*! Port 2 Interrupt Enable */
   126        config Bits8 p2ie = 0;
   127    
   128        /*! Port 2 Interrupt Edge Select */
   129        config Bits8 p2ies = 0;
   130    
   131        /*! Port 3 Interrupt Enable */
   132        config Bits8 p3ie = 0;
   133    
   134        /*! Port 3 Interrupt Edge Select */
   135        config Bits8 p3ies = 0;
   136    
   137        /*! Port 4 Interrupt Enable */
   138        config Bits8 p4ie = 0;
   139    
   140        /*! Port 4 Interrupt Edge Select */
   141        config Bits8 p4ies = 0;
   142    
   143        /*! Port 1 Interrupt Flag Register */
   144        config Bits8 p1ifg = 0;
   145    
   146        /*! Port 2 Interrupt Flag Register */
   147        config Bits8 p2ifg = 0;
   148    
   149        /*! Port 3 Interrupt Flag Register */
   150        config Bits8 p3ifg = 0;
   151    
   152        /*! Port 4 Interrupt Flag Register */
   153        config Bits8 p4ifg = 0;
   154    
   155        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[length];
   156    }