1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*!
    34     *  ======== ADC10 ========
    35     *  MSP430 10-bit Analog to Digital Converter
    36     */
    37    metaonly module ADC10 inherits IADC {
    38    
    39        /*! ADC10 Start Conversion */
    40        enum ADC10SC_t {
    41            ADC10SC_OFF     = 0x000,        /*! No conversion. */
    42            ADC10SC         = 0x001         /*! Start ADC conversion manually. */
    43        };
    44    
    45        /*! ADC10 Enable Conversion */
    46        enum ENC_t {
    47            ENC_OFF         = 0x000,        /*! Disable ADC. */
    48            ENC             = 0x002         /*! Enable ADC. */
    49        };
    50    
    51        /*! ADC10 Interrupt Flag */
    52        enum ADC10IFG_t {
    53            ADC10IFG_OFF    = 0x000,        /*! Clear ADC interrupt flag. */
    54            ADC10IFG        = 0x004         /*! Set ADC interrupt flag. */
    55        };
    56    
    57        /*! ADC10 Interrupt Enable */
    58        enum ADC10IE_t {
    59            ADC10IE_OFF = 0x000,            /*! Disable ADC interrupt. */
    60            ADC10IE     = 0x008             /*! Enable ADC interrupt. */
    61        };
    62    
    63        /*! ADC10 On/Enable */
    64        enum ADC10ON_t {
    65            ADC10ON_OFF = 0x000,            /*! Switch Off ADC10. */
    66            ADC10ON     = 0x010             /*! Switch On ADC10. */
    67        };
    68    
    69        /*! ADC10 Reference on */
    70        enum REFON_t {
    71            REFON_OFF   = 0x000,            /*! Disable ADC reference generator. */
    72            REFON       = 0x020             /*! Enable ADC reference generator. */
    73        };
    74    
    75        /*! ADC10 Ref 0:1.5V / 1:2.5V */
    76        enum REF2_5V_t {
    77            REF2_5V_OFF = 0x000,            /*! Set reference voltage generator = 1.5V. */
    78            REF2_5V     = 0x040             /*! Set reference voltage generator = 2.5V. */
    79        };
    80    
    81        /*! ADC10 Multiple SampleConversion */
    82        enum MSC_t {
    83            MSC_OFF = 0x000,                /*! Disable multiple sample and conversion. */
    84            MSC     = 0x080                 /*! Enable multiple sample and conversion. */
    85        };
    86    
    87        /*! ADC10 Reference Burst Mode */
    88        enum REFBURST_t {
    89            REFBURST_OFF = 0x000,           /*! Reference buffer on continuously. */
    90            REFBURST     = 0x100            /*! Reference buffer on only during sample-and-conversion. */
    91        };
    92    
    93        /*! ADC10 Enable output of Ref. */
    94        enum REFOUT_t {
    95            REFOUT_OFF      = 0x000,        /*! Reference output off. */
    96            REFOUT          = 0x200         /*! Reference output on. */
    97        };
    98    
    99        /*! ADC10 Sampling Rate 0:200ksps / 1:50ksps */
   100        enum ADC10SR_t {
   101            ADC10SR_OFF = 0x000,            /*! Reference buffer supports up to ~200 ksps. */
   102            ADC10SR     = 0x400             /*! Reference buffer supports up to ~50 ksps. */
   103        };
   104    
   105        /*! ADC10 Sample Hold Select 0 */
   106        enum ADC10SHT_t {
   107            ADC10SHT_0      = (0*0x800u),   /*! 4 x ADC10CLKs. */
   108            ADC10SHT_1      = (1*0x800u),   /*! 8 x ADC10CLKs. */
   109            ADC10SHT_2      = (2*0x800u),   /*! 16 x ADC10CLKs. */
   110            ADC10SHT_3      = 3*0x800u      /*! 64 x ADC10CLKs. */
   111        };
   112    
   113        /*! ADC10 Reference Select 0 */
   114        enum SREF_t {
   115            SREF_0 = (0*0x2000u),           /*! VR+ = VCC and VR- = VSS. */
   116            SREF_1 = (1*0x2000u),           /*! VR+ = VREF+ and VR- = VSS. */
   117            SREF_2 = (2*0x2000u),           /*! VR+ = VeREF+ and VR- = VSS. */
   118            SREF_3 = (3*0x2000u),           /*! VR+ = Buffered VeREF+ and VR- = VSS. */
   119            SREF_4 = (4*0x2000u),           /*! VR+ = VCC and VR- = VREF-/ VeREF-. */
   120            SREF_5 = (5*0x2000u),           /*! VR+ = VREF+ and VR- = VREF-/ VeREF-. */
   121            SREF_6 = (6*0x2000u),           /*! VR+ = VeREF+ and VR- = VREF-/ VeREF-. */
   122            SREF_7 = 7*0x2000u              /*! VR+ = Buffered VeREF+ and VR- = VREF-/ VeREF-. */
   123        };
   124    
   125        enum ADC10BUSY_t {
   126            ADC10BUSY_OFF = 0x0000,         /*! No operation is active. */
   127            ADC10BUSY     = 0x0001          /*! A sequence, sample, or conversion is active. */
   128        };
   129    
   130        /*! Types of conversion */
   131        enum CONSEQ_t {
   132            CONSEQ_0 = (0*2u),              /*! Single channel single conversion. */
   133            CONSEQ_1 = (1*2u),              /*! Sequence of channels. */
   134            CONSEQ_2 = (2*2u),              /*! Repeat single channel. */
   135            CONSEQ_3 = 3*2u                 /*! Repeat sequence of channels. */
   136        };
   137    
   138        /*! ADC10 Clock Source */
   139        enum ADC10SSEL_t {
   140            ADC10SSEL_0 = (0*8u),           /*! ADC10OSC. */
   141            ADC10SSEL_1 = (1*8u),           /*! ACLK. */
   142            ADC10SSEL_2 = (2*8u),           /*! MCLK.*/
   143            ADC10SSEL_3 = 3*8u              /*! SMCLK. */
   144        };
   145    
   146        /*! ADC10 Clock Divider */
   147        enum ADC10DIV_t {
   148            ADC10DIV_0 = (0*0x20u),         /*! Divide by 1. */
   149            ADC10DIV_1 = (1*0x20u),         /*! Divide by 2. */
   150            ADC10DIV_2 = (2*0x20u),         /*! Divide by 3. */
   151            ADC10DIV_3 = (3*0x20u),         /*! Divide by 4. */
   152            ADC10DIV_4 = (4*0x20u),         /*! Divide by 5. */
   153            ADC10DIV_5 = (5*0x20u),         /*! Divide by 6. */
   154            ADC10DIV_6 = (6*0x20u),         /*! Divide by 7. */
   155            ADC10DIV_7 = 7*0x20u            /*! Divide by 8. */
   156        };
   157    
   158        /*! ADC10 input signal inversion */
   159        enum ISSH_t {
   160            ISSH_OFF = 0x0000,              /*! Input signal not inverted. */
   161            ISSH     = 0x0100               /*! Input signal inverted. */
   162        };
   163    
   164        /*! ADC10 output as 2's complement */
   165        enum ADC10DF_t {
   166            ADC10DF_OFF = 0x0000,           /*! ADC10 Data Format as binary. */
   167            ADC10DF     = 0x0200            /*! ADC10 Data Format as 2's complement */
   168        };
   169    
   170        /*! ADC10 trigger */
   171        enum SHS_t {
   172            SHS_0 = (0*0x400u),             /*! ADC10SC. */
   173            SHS_1 = (1*0x400u),             /*! Timer_A OUT1. */
   174            SHS_2 = (2*0x400u),             /*! Timer_A OUT0. */
   175            SHS_3 = 3*0x400u                /*! Timer_A OUT2. */
   176        };
   177    
   178        /*! ADC10 Channel Selection */
   179        enum INCH_t {
   180            INCH_0 = (0*0x1000u),           /*! ADC Channel 0. */
   181            INCH_1 = (1*0x1000u),           /*! ADC Channel 1. */
   182            INCH_2 = (2*0x1000u),           /*! ADC Channel 2. */
   183            INCH_3 = (3*0x1000u),           /*! ADC Channel 3. */
   184            INCH_4 = (4*0x1000u),           /*! ADC Channel 4. */
   185            INCH_5 = (5*0x1000u),           /*! ADC Channel 5. */
   186            INCH_6 = (6*0x1000u),           /*! ADC Channel 6. */
   187            INCH_7 = (7*0x1000u),           /*! ADC Channel 7. */
   188            INCH_8 = (8*0x1000u),           /*! ADC VeRef+. */
   189            INCH_9 = (9*0x1000u),           /*! ADC VeRef-. */
   190            INCH_10 = (10*0x1000u),         /*! Temperature Sensor. */
   191            INCH_11 = (11*0x1000u),         /*! ADC convert VCC. */
   192            INCH_12 = (12*0x1000u),         /*! ADC Channel 12. */
   193            INCH_13 = (13*0x1000u),         /*! ADC Channel 13. */
   194            INCH_14 = (14*0x1000u),         /*! ADC Channel 14. */
   195            INCH_15 = 15*0x1000u            /*! ADC Channel 15. */
   196        };
   197    
   198        /*!
   199         *  ======== ADC10CT_t ========
   200         *  Data transfer modes
   201         *
   202         *  @see #ADC10DTC0
   203         */
   204        enum ADC10CT_t {
   205            ADC10CT_OFF = 0x000,            /*! Data is transferred is stopped after every conversion. */
   206            ADC10CT     = 0x004             /*! Data is transferred continuously after every conversion. */
   207        }
   208    
   209        /*!
   210         *  ======== ADC10TB_t ========
   211         *  Block data transfer modes
   212         *
   213         *  @see #ADC10DTC0
   214         */
   215        enum ADC10TB_t {
   216            ADC10TB_OFF = 0x000,            /*! One-block transfer mode. */
   217            ADC10TB     = 0x008             /*! Two-block transfer mode. */
   218        }
   219        /* End of ADC10DTC0 Register Definitions */
   220    
   221        /*!
   222         *  ======== ADC10CTL0_t ========
   223         *  ADC10 Control Register 0
   224         *
   225         *  @see #ADC10CTL0
   226         */
   227        struct ADC10CTL0_t {
   228            ADC10SC_t   ADC10SC;        /*! Start conversion. Software-controlled sample-and-conversion start.
   229                                          * ADC10SC and ENC may be set together with one instruction. ADC10SC is
   230                                          * reset automatically.
   231                                          *  0  No sample-and-conversion start
   232                                          *  1  Start sample-and-conversion */
   233            ENC_t       ENC;            /*! Enable conversion
   234                                          *  0  ADC10 disabled
   235                                          *  1  ADC10 enabled */
   236            ADC10IFG_t  ADC10IFG;       /*! ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion
   237                                          * result. It is automatically reset when the interrupt request is accepted, or it may
   238                                          * be reset by software. When using the DTC this flag is set when a block of
   239                                          * transfers is completed.
   240                                          *  0  No interrupt pending
   241                                          *  1  Interrupt pending */
   242            ADC10IE_t   ADC10IE;        /*! ADC10 interrupt enable
   243                                          *  0  Interrupt disabled
   244                                          *  1  Interrupt enabled */
   245            ADC10ON_t   ADC10ON;        /*! ADC10 on
   246                                          *  0  ADC10 off
   247                                          *  1  ADC10 on */
   248            REFON_t     REFON;          /*! Reference generator on
   249                                          *  0  Reference off
   250                                          *  1  Reference on */
   251            REF2_5V_t   REF2_5V;        /*! Reference-generator voltage. REFON must also be set.
   252                                          *  0  1.5 V
   253                                          *  1  2.5 V */
   254            MSC_t       MSC;            /*! Multiple sample and conversion. Valid only for sequence or repeated modes.
   255                                          *  0  The sampling requires a rising edge of the SHI signal to trigger each
   256                                          *     sample-and-conversion.
   257                                          *  1  The first rising edge of the SHI signal triggers the sampling timer, but
   258                                          *     further sample-and-conversions are performed automatically as soon
   259                                          *     as the prior conversion is completed */
   260            REFBURST_t  REFBURST;       /*! Reference burst.
   261                                          *  0  Reference buffer on continuously
   262                                          *  1  Reference buffer on only during sample-and-conversion */
   263            REFOUT_t    REFOUT;         /*! Reference output
   264                                          *  0  Reference output off
   265                                          *  1  Reference output on, use internal reference
   266                                                voltage externally on pin VREF+ */
   267            ADC10SR_t   ADC10SR;        /*! ADC10 sampling rate. This bit selects the reference buffer drive capability for
   268                                          * the maximum sampling rate. Setting ADC10SR reduces the current
   269                                          * consumption of the reference buffer.
   270                                          *  0  Reference buffer supports up to ~200 ksps
   271                                          *  1  Reference buffer supports up to ~50 ksps */
   272            ADC10SHT_t  ADC10SHT;       /*! ADC10 sample-and-hold time
   273                                          *  00  4 x ADC10CLKs
   274                                          *  01  8 x ADC10CLKs
   275                                          *  10  16 x ADC10CLKs
   276                                          *  11  64 x ADC10CLKs */
   277            SREF_t      SREF;           /*! Select reference
   278                                          *  000  VR+ = VCC and VR- = VSS
   279                                          *  001  VR+ = VREF+ and VR- = VSS
   280                                          *  010  VR+ = VeREF+ and VR- = VSS
   281                                          *  011  VR+ = Buffered VeREF+ and VR- = VSS
   282                                          *  100  VR+ = VCC and VR- = VREF-/ VeREF-
   283                                          *  101  VR+ = VREF+ and VR- = VREF-/ VeREF-
   284                                          *  110  VR+ = VeREF+ and VR- = VREF-/ VeREF-
   285                                          *  111  VR+ = Buffered VeREF+ and VR- = VREF-/ VeREF- */
   286        }
   287    
   288        /*!
   289         *  ======== ADC10CTL1_t ========
   290         *  ADC10 Control Register 1
   291         *
   292         *  @see #ADC10CTL1
   293         */
   294        struct ADC10CTL1_t {
   295            ADC10BUSY_t ADC10BUSY;      /*! ADC10 busy. This bit indicates an active sample or conversion operation
   296                                          *  0  No operation is active.
   297                                          *  1  A sequence, sample, or conversion is active. */
   298            CONSEQ_t    CONSEQ;         /*! Conversion sequence mode select
   299                                          *  00  Single-channel-single-conversion
   300                                          *  01  Sequence-of-channels
   301                                          *  10  Repeat-single-channel
   302                                          *  11  Repeat-sequence-of-channels */
   303            ADC10SSEL_t ADC10SSEL;      /*! ADC10 clock source select
   304                                          *  00  ADC10OSC
   305                                          *  01  ACLK
   306                                          *  10  MCLK
   307                                          *  11  SMCLK */
   308            ADC10DIV_t  ADC10DIV;       /*! ADC10 clock divider
   309                                          *  000  /1
   310                                          *  001  /2
   311                                          *  010  /3
   312                                          *  011  /4
   313                                          *  100  /5
   314                                          *  101  /6
   315                                          *  110  /7
   316                                          *  111  /8 */
   317            ISSH_t      ISSH;           /*! Invert signal sample-and-hold
   318                                          *  0  The sample-input signal is not inverted.
   319                                          *  1  The sample-input signal is inverted. */
   320            ADC10DF_t   ADC10DF;        /*! ADC10 data format
   321                                          *  0  Straight binary
   322                                          *  1  2s complement */
   323            SHS_t       SHS;            /*! Sample-and-hold source select
   324                                          *  00  ADC10SC bit
   325                                          *  01  Timer_A.OUT1
   326                                          *  10  Timer_A.OUT0
   327                                          *  11  Timer_A.OUT2 (Timer_A.OUT1 on MSP430x20x2 devices) */
   328            INCH_t      INCH;           /*! Input channel select. These bits select the channel for a single-conversion or
   329                                          * the highest channel for a sequence of conversions.
   330                                          *  0000  A0
   331                                          *  0001  A1
   332                                          *  0010  A2
   333                                          *  0011  A3
   334                                          *  0100  A4
   335                                          *  0101  A5
   336                                          *  0110  A6
   337                                          *  0111  A7
   338                                          *  1000  VeREF+
   339                                          *  1001  VREF-/VeREF-
   340                                          *  1010  Temperature sensor
   341                                          *  1011  (VCC ??? VSS) /
   342                                          *  1100  A12
   343                                          *  1101  A13
   344                                          *  1110  A14
   345                                          *  1111  A15 */
   346        }
   347    
   348        /*!
   349         *  ======== ADC10DTC0_t ========
   350         *  Data Transfer Control Register 0
   351         *
   352         *  @see #ADC10DTC0
   353         */
   354        struct ADC10DTC0_t {
   355            ADC10TB_t   ADC10TB;        /*! ADC10 two-block mode
   356                                          *  0  One-block transfer mode
   357                                          *  1  Two-block transfer mode */
   358            ADC10CT_t   ADC10CT;        /*! ADC10 continuous transfer
   359                                          *  0  Data transfer stops when one block (one-block mode) or two blocks
   360                                          *     (two-block mode) have completed.
   361                                          *  1  Data is transferred continuously. DTC operation is stopped only if
   362                                          *     ADC10CT cleared, or ADC10SA is written to. */
   363        }
   364    
   365    instance:
   366        /*! Control Register 0 */
   367        config ADC10CTL0_t  ADC10CTL0 = {
   368            ADC10SC :   ADC10SC_OFF,
   369            ENC     :   ENC_OFF,
   370            ADC10IFG:   ADC10IFG_OFF,
   371            ADC10IE :   ADC10IE_OFF,
   372            ADC10ON :   ADC10ON_OFF,
   373            REFON   :   REFON_OFF,
   374            REF2_5V :   REF2_5V_OFF,
   375            MSC     :   MSC_OFF,
   376            REFBURST:   REFBURST_OFF,
   377            REFOUT  :   REFOUT_OFF,
   378            ADC10SR :   ADC10SR_OFF,
   379            ADC10SHT:   ADC10SHT_0,
   380            SREF    :   SREF_0
   381        };
   382    
   383        /*! Control Register 1 */
   384        config ADC10CTL1_t  ADC10CTL1 = {
   385            ADC10BUSY   :   ADC10BUSY_OFF,
   386            CONSEQ      :   CONSEQ_0,
   387            ADC10SSEL   :   ADC10SSEL_0,
   388            ADC10DIV    :   ADC10DIV_0,
   389            ISSH        :   ISSH_OFF,
   390            ADC10DF     :   ADC10DF_OFF,
   391            SHS         :   SHS_0,
   392            INCH        :   INCH_0
   393        };
   394    
   395        /*!
   396         *  Analog (Input) Enable Control Register 0
   397         *
   398         *  Bit n enables the corresponding pin for analog
   399         *  input. Bit 0 corresponds to A0, bit 1 corresponds to A1, ...
   400         */
   401        config Bits16 ADC10AE0 = 0;
   402    
   403        /*!
   404         *  Analog (Input) Enable Control Register 1
   405         *
   406         *  Bits 0, 1, 2, and 3 are reserved.
   407         *
   408         *  Starting with bit 4, bit n enables pin n+8 for analog
   409         *  input: Bit 4 corresponds to A12, bit 5 corresponds to A13, ...
   410         */
   411        config Bits16 ADC10AE1 = 0;
   412    
   413        /*! Data Transfer Control Register 0 */
   414        config ADC10DTC0_t ADC10DTC0 = {
   415            ADC10TB : ADC10TB_OFF,
   416            ADC10CT : ADC10CT_OFF
   417        };
   418    
   419        /*!
   420         *  Data Transfer Control Register 1
   421         *
   422         *  This register defines the number of transfers in each block: 0
   423         *  implies DTC is disabled, 1 through 0xff are valid transfer counts.
   424         */
   425        config Bits8  ADC10DTC1 = 0;
   426    
   427        /*! Data Transfer Start Address */
   428        config Bits16 *ADC10SA = 0x200;
   429    
   430        /*! ADC10 has 1 interrupt enable */
   431        config regIntVect_t interruptSource[1];
   432    
   433        /*! Determine if each Register needs to be forced set or not */
   434        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   435        [
   436            { register : "ADC10CTL0" , regForceSet : false },
   437            { register : "ADC10CTL1" , regForceSet : false },
   438            { register : "ADC10AE0"  , regForceSet : false },
   439            { register : "ADC10AE1"  , regForceSet : false },
   440            { register : "ADC10DTC0" , regForceSet : false },
   441            { register : "ADC10DTC1" , regForceSet : false },
   442            { register : "ADC10SA"   , regForceSet : true }
   443        ];
   444    }