1 /* 2 * Copyright (c) 2016, Texas Instruments Incorporated 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * ======== ITI8168.xdc ======== 35 * 36 */ 37 38 /*! 39 * ======== ITI8168 ======== 40 * An interface implemented by all TI8168 devices 41 * 42 * This interface is defined to factor common data about all TI8168 type devices 43 * into a single place; they all have the same internal memory. 44 */ 45 metaonly interface ITI8168 inherits ti.catalog.ICpuDataSheet 46 { 47 instance: 48 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0; 49 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp1; 50 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp2; 51 52 override config string cpuCore = "CM3"; 53 override config string isa = "v7M"; 54 override config string cpuCoreRevision = "1.0"; 55 override config int minProgUnitSize = 1; 56 override config int minDataUnitSize = 1; 57 override config int dataWordSize = 4; 58 59 /*! 60 * ======== memMap ======== 61 * The memory map returned be getMemoryMap(). 62 */ 63 config xdc.platform.IPlatform.Memory memMap[string] = [ 64 65 /* 66 * AMMU mapped L2 BOOT virtual address 67 * Physical address is 0x5502_0000, virt is 0x00000000 68 * Reset vectors and other boot code is placed here. 69 * 70 * Note that actual L2 RAM is 256K starting at 0x5502_0000. 71 * The first 16K is reserved for reset vectors (i.e. L2_BOOT). 72 * The remaining 240K is placed in the L2_RAM definition. 73 */ 74 ["L2_BOOT", { 75 name: "L2_BOOT", 76 base: 0x00000000, 77 len: 0x4000 78 }], 79 80 /* 81 * AMMU mapped L2 RAM virtual address 82 * Physical address is 0x5502_4000, virt is 0x2000_4000 83 * 84 * Note that actual L2 RAM is 256K starting at 0x5502_0000. 85 * The first 16K is reserved for reset vectors (i.e. L2_BOOT). 86 * The remaining 240K is placed in the L2_RAM definition. 87 */ 88 ["L2_RAM", { 89 name: "L2_RAM", 90 base: 0x20004000, 91 len: 0x3C000 92 }], 93 94 /* 95 * OCMC (On-chip RAM) Bank 0 96 * Physical address is 0x40300000 97 * Size is 256K 98 */ 99 ["OCMC_0", { 100 name: "OCMC_0", 101 base: 0x00300000, 102 len: 0x40000 103 }], 104 105 /* 106 * OCMC (On-chip RAM) Bank 1 107 * Physical address is 0x40400000 108 * Size is 256K 109 */ 110 ["OCMC_1", { 111 name: "OCMC_1", 112 base: 0x00400000, 113 len: 0x40000 114 }], 115 ]; 116 };