1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    import ti.catalog.msp430.peripherals.clock.IClock;
    34    
    35    /*!
    36     *  ======== Flash_2xx ========
    37     *  MSP430F2xx Family Flash Module
    38     */
    39    metaonly module Flash_2xx inherits IFlash
    40    {
    41        /* FCTL1 Register */
    42        struct FCTL1_t {
    43            FWKEY_t     FWKEY;                  /*! FCTLx password Always read as 096h. Must be written as 0A5h or a PUC
    44                                                 *  will be generated. */
    45            BLKWRT_t    BLKWRT;                 /*! Block write mode */
    46            WRT_t       WRT;                    /*! Write */
    47            EEIEX_t     EEIEX;                  /*! Enable Emergency Interrupt Exit */
    48            EEI_t       EEI;                    /*! Enable Erase Interrupts */
    49            MERAS_t     MERAS;                  /*! Mass erase */
    50            ERASE_t     ERASE;                  /*! Erase */
    51        }
    52    
    53        /* FCTL2 Register */
    54        struct FCTL2_t {
    55            FWKEY_t     FWKEY;                  /*! FCTLx password Always read as 096h. Must be written as 0A5h or a PUC
    56                                                 *  will be generated. */
    57             FSSEL_t     FSSEL;                 /*! Flash controller clock source select
    58                                                 *   00  ACLK
    59                                                 *   01  MCLK
    60                                                 *   10  SMCLK
    61                                                 *   11  SMCLK */
    62            FN5_t    FN5;                       /*! Flash Controller Clock Divider Bit 5 */
    63            FN4_t    FN4;                       /*! Flash Controller Clock Divider Bit 4 */
    64            FN3_t    FN3;                       /*! Flash Controller Clock Divider Bit 3 */
    65            FN2_t    FN2;                       /*! Flash Controller Clock Divider Bit 2 */
    66            FN1_t    FN1;                       /*! Flash Controller Clock Divider Bit 1 */
    67            FN0_t    FN0;                       /*! Flash Controller Clock Divider Bit 0 */
    68        }
    69    
    70        /* FCTL3 Register */
    71        struct FCTL3_t {
    72            FWKEY_t     FWKEY;                  /*! FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC
    73                                                 *  will be generated. */
    74            FAIL_t      FAIL;                   /*!  FAIL Bit 7 Operation failure. This bit is set if the fFTG clock source fails, or a flash
    75                                                 *  operation is aborted from an interrupt when EEIEX = 1. FAIL must be reset
    76                                                 *  with software.
    77                                                 *  0  No failure
    78                                                 *  1  Failure */
    79            LOCKA_t     LOCKA;                  /*! SegmentA and Info lock. Write a 1 to this bit to change its state. Writing 0 has
    80                                                 *  no effect.
    81                                                 *  0  Segment A unlocked and all information memory is erased during a
    82                                                 *     mass erase.
    83                                                 *  1  Segment A locked and all information memory is protected from erasure
    84                                                 *     during a mass erase. */
    85            EMEX_t      EMEX;                   /*! Emergency exit
    86                                                 *  0  No emergency exit
    87                                                 *  1  Emergency exit */
    88            LOCK_t      LOCK;                   /*! Lock. This bit unlocks the flash memory for writing or erasing. The LOCK bit
    89                                                 *  can be set anytime during a byte/word write or erase operation and the
    90                                                 *  operation will complete normally. In the block write mode if the LOCK bit is set
    91                                                 *  while BLKWRT=WAIT=1, then BLKWRT and WAIT are reset and the mode
    92                                                 *  ends normally.
    93                                                 *  0  Unlocked
    94                                                 *  1  Locked */
    95            WAIT_t      WAIT;                   /*! Wait. Indicates the flash memory is being written to.
    96                                                 *  0  The flash memory is not ready for the next byte/word write
    97                                                 *  1  The flash memory is ready for the next byte/word write */
    98            ACCVIFG_t   ACCVIFG;                /*! Access violation interrupt flag
    99                                                 *  0 No interrupt pending
   100                                                 *  1 Interrupt pending */
   101            KEYV_t      KEYV;                   /*! Flash security key violation. This bit indicates an incorrect FCTLx password
   102                                                 *  was written to any flash control register and generates a PUC when set. KEYV
   103                                                 *  must be reset with software.
   104                                                 *  0  FCTLx password was written correctly
   105                                                 *  1  FCTLx password was written incorrectly */
   106            BUSY_t      BUSY;                   /*! Busy. This bit indicates the status of the flash timing generator.
   107                                                 *  0  Not Busy
   108                                                 *  1  Busy */
   109        }
   110    
   111        /*
   112         *  ======== create ========
   113         */
   114        create(IClock.Instance clock);
   115    
   116    instance:
   117        /*! Flash Memory Control Register 1 */
   118        config FCTL1_t FCTL1 = {
   119            FWKEY   : FWKEY,
   120            BLKWRT  : BLKWRT_OFF,
   121            WRT     : WRT_OFF,
   122            EEIEX   : EEIEX_OFF,
   123            EEI     : EEI_OFF,
   124            MERAS   : MERAS_OFF,
   125            ERASE   : ERASE_OFF
   126        };
   127    
   128        /*! Flash Memory Control Register 2 */
   129        config FCTL2_t FCTL2 = {
   130            FWKEY       : FWKEY,
   131            FSSEL       : FSSEL_1,
   132            FN5         : FN5_OFF,
   133            FN4         : FN4_OFF,
   134            FN3         : FN3_OFF,
   135            FN2         : FN2_OFF,
   136            FN1         : FN1,
   137            FN0         : FN0_OFF
   138        };
   139    
   140        /*! Flash Memory Control Register 3 */
   141        config FCTL3_t FCTL3 = {
   142            FAIL        : FAIL_OFF,
   143            LOCKA       : LOCKA_OFF,
   144            EMEX        : EMEX_OFF,
   145            LOCK        : LOCK,
   146            WAIT        : WAIT,
   147            ACCVIFG     : ACCVIFG_OFF,
   148            KEYV        : KEYV_OFF,
   149            BUSY        : BUSY_OFF
   150        };
   151    
   152        /*! Determine if each Register needs to be forced set or not */
   153        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] = [
   154            { register : "FCTL1" , regForceSet : false },
   155            { register : "FCTL2" , regForceSet : false },
   156            { register : "FCTL3" , regForceSet : false }
   157        ];
   158    
   159        config IClock.Instance clock;
   160    }