1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*
    34     *  ======== ICacheInfo.xdc ========
    35     */
    36    
    37    
    38    package ti.catalog.c6000;
    39    
    40    metaonly interface ICacheInfo {
    41        /*!
    42         *  ======== CacheDesc ========
    43         *  Structure used by ICpuDataSheet implementations to
    44         *  specify device cache modes.
    45         *
    46         *  A map is defined by an ICpuDataSheet implementation
    47         *  that maps a string denoting a device register setting
    48         *  to a CacheDesc structure. This maybe used in implementing
    49         *  the 'getMemoryMap' method. An example of such a map is shown below :
    50         *
    51         *   readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    52             *    ['l1PMode',{desc:"L1P Cache",
    53             *                map : [["0k",0x0000],
    54             *                       ["4k",0x1000],
    55             *                       ["8k",0x2000],
    56             *                       ["16k",0x4000],
    57             *                       ["32k",0x8000]],
    58             *                defaultValue: "32k",
    59             *                memorySection: "L1PSRAM"}],
    60             *
    61             *        ['l1DMode',{desc:"L1D Cache",
    62             *                map : [["0k",0x0000],
    63             *                       ["4k",0x1000],
    64             *                       ["8k",0x2000],
    65             *                       ["16k",0x4000],
    66             *                       ["32k",0x8000]],
    67             *                defaultValue: "32k",
    68             *                memorySection: "L1DSRAM"}],
    69             *
    70             *    ['l2Mode',{desc:"L2 Cache",
    71             *                map : [["0k",0x0000],
    72             *                       ["32k",0x8000],
    73             *                       ["64k",0x10000],
    74             *                       ["128k",0x20000],
    75             *                       ["256k",0x40000]],
    76             *                defaultValue: "0k",
    77             *                memorySection: "IRAM"}],
    78         *
    79         *   ];
    80         *
    81         *  @_nodoc
    82         */
    83        struct CacheDesc {
    84            string desc;          /*! String describing the register setting */
    85            Int base;             /*! base address of cache */
    86            unsigned map[string]; /*! A hash of cache modes to cache size*/
    87            string defaultValue;  /*! The default cache mode for the device */
    88            string memorySection; /*! The associated memory section */
    89        };
    90    
    91    
    92    }