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16
17 import xdc.runtime.Error;
18 import xdc.runtime.knl.ICacheSupport;
19
20 /*!
21 * ======== Cache ========
22 * Cache Services
23 *
24 * The Cache module provide APIs to allow applications to maintain cache
25 * coherency.
26 *
27 * This module will use an OS specific delegate (back-end) to manipulate the
28 * cache.
29 * This module has a module wide config parameter {@link #Proxy} which needs to
30 * be bound to an OS specific delegate before this module can be used.
31 *
32 * Here is an example showing how the proxy is bound to an BIOS 6.x specific
33 * delegate.
34 *
35 * @p(code)
36 * var Cache = xdc.useModule('xdc.runtime.knl.Cache');
37 * Cache.Proxy = xdc.useModule('ti.sysbios.xdcruntime.CacheSupport');
38 * @p
39 *
40 * Typically the package containing the delegates have a Settings module that
41 * will bind all {@link xdc.runtime.knl} proxies. The following
42 * example sets up all the xdc.runtime.knl proxies.
43 *
44 * @p(code)
45 * xdc.useModule("ti.sysbios.xdcruntime.Settings");
46 * @p
47 */
48 @DirectCall
49
50 module Cache
51 {
52 /*!
53 * ======== Proxy ========
54 * ICacheSupport proxy
55 *
56 * Cache will use this proxy to access the cache hardware using
57 * OS specific APIs.
58 */
59 proxy Proxy inherits ICacheSupport;
60
61 /*!
62 * ======== inv ========
63 * Invalidate range of memory for all cache(s)
64 *
65 * Invalidate the range of memory within the specified starting
66 * address and byte count. The range of addresses operated on
67 * gets quantized to whole cache lines in each cache. All lines
68 * in range are invalidated for all cache types.
69 *
70 * @param(blockPtr) start address of range to be invalidated
71 * @param(byteCnt) number of bytes to be invalidated
72 * @param(wait) wait until the operation is completed
73 * @param(eb) error block
74 * @a(returns) true for success; false for error.
75 */
76 Bool inv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
77
78 /*!
79 * ======== wb ========
80 * Writes back a range of memory from all cache(s)
81 *
82 * Writes back the range of memory within the specified starting
83 * address and byte count. The range of addresses operated on
84 * gets quantized to whole cache lines in each cache. All lines
85 * within the range are left valid in all caches and the data
86 * within the range will be written back to the source memory.
87 *
88 * @param(blockPtr) start address of range to be invalidated
89 * @param(byteCnt) number of bytes to be invalidated
90 * @param(wait) wait until the operation is completed
91 * @param(eb) error block
92 * @a(returns) true for success; false for error.
93 */
94 Bool wb(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
95
96 /*!
97 * ======== wbInv ========
98 * Write back and invalidate range of memory.
99 *
100 * Writes back and invalidates the range of memory within the
101 * specified starting address and byte count. The range of
102 * addresses operated on gets quantized to whole cache lines in
103 * each cache. All lines within the range are written back to the
104 * source memory and then invalidated for all cache types.
105 *
106 * @param(blockPtr) start address of range to be invalidated
107 * @param(byteCnt) number of bytes to be invalidated
108 * @param(wait) wait until the operation is completed
109 * @param(eb) error block
110 * @a(returns) true for success; false for error.
111 */
112 Bool wbInv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
113
114 /*!
115 * ======== wait ========
116 * Wait for a previous cache operation to complete
117 *
118 * Wait for the cache wb/wbInv/inv operation to complete. A cache
119 * operation is not truly complete until it has worked its way
120 * through all buffering and all memory writes have landed in the
121 * source memory.
122 *
123 * @param(eb) error block
124 * @a(returns) true for success; false for error.
125 */
126 Bool wait(Error.Block *eb);
127 }
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131