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32
33 /*!
34 * Universal Serial Communication Interface
35 */
36 metaonly interface IUSCI_UART inherits IUSCI {
37
38
39
40
41
42 /*! Parity enable */
43 enum UCPEN_t {
44 UCPEN_OFF = 0x00, /*! Parity Disabled */
45 UCPEN = 0x02 /*! Parity Enabled */
46 };
47
48 /*! Parity select. UCPAR is not used when parity is disabled. */
49 enum UCPAR_t {
50 UCPAR_OFF = 0x00, /*! Odd parity */
51 UCPAR = 0x02 /*! Even parity */
52 };
53
54 /*! Stop bit select. Number of stop bits. */
55 enum UCSPB_t {
56 UCSPB_OFF = 0x00, /*! One stop bit */
57 UCSPB = 0x02 /*! Two stop bits */
58 };
59
60 /*! First modulation stage select */
61 enum UCBRF_t {
62 UCBRF_0 = 0x00, /*! First stage 0 */
63 UCBRF_1 = 0x10, /*! First stage 1 */
64 UCBRF_2 = 0x20, /*! First stage 2 */
65 UCBRF_3 = 0x30, /*! First stage 3 */
66 UCBRF_4 = 0x40, /*! First stage 4 */
67 UCBRF_5 = 0x50, /*! First stage 5 */
68 UCBRF_6 = 0x60, /*! First stage 6 */
69 UCBRF_7 = 0x70, /*! First stage 7 */
70 UCBRF_8 = 0x80, /*! First stage 8 */
71 UCBRF_9 = 0x90, /*! First stage 9 */
72 UCBRF_10 = 0xA0, /*! First stage 10 */
73 UCBRF_11 = 0xB0, /*! First stage 11 */
74 UCBRF_12 = 0xC0, /*! First stage 12 */
75 UCBRF_13 = 0xD0, /*! First stage 13 */
76 UCBRF_14 = 0xE0, /*! First stage 14 */
77 UCBRF_15 = 0xF0 /*! First stage 15 */
78 };
79
80 /*! Second modulation stage select */
81 enum UCBRS_t {
82 UCBRS_0 = 0x00, /*! Second stage 0 */
83 UCBRS_1 = 0x02, /*! Second stage 1 */
84 UCBRS_2 = 0x04, /*! Second stage 2 */
85 UCBRS_3 = 0x06, /*! Second stage 3 */
86 UCBRS_4 = 0x08, /*! Second stage 4 */
87 UCBRS_5 = 0x0A, /*! Second stage 5 */
88 UCBRS_6 = 0x0C, /*! Second stage 6 */
89 UCBRS_7 = 0x0E /*! Second stage 7 */
90 };
91
92 /*! Oversampling mode enabled */
93 enum UCOS16_t {
94 UCOS16_OFF = 0x00, /*! Disabled. */
95 UCOS16 = 0x02 /*! Enabled. */
96 };
97
98
99 /*! IRDA Transmit Pulse Length Bit 5 */
100 enum UCIRTXPL5_t {
101 UCIRTXPL5_OFF = 0x00, /*! Bit 5 OFF */
102 UCIRTXPL5 = 0x80 /*! Bit 5 ON */
103 };
104
105 /*! IRDA Transmit Pulse Length Bit 4 */
106 enum UCIRTXPL4_t {
107 UCIRTXPL4_OFF = 0x00, /*! Bit 4 OFF */
108 UCIRTXPL4 = 0x40 /*! Bit 4 ON */
109 };
110
111 /*! IRDA Transmit Pulse Length Bit 3 */
112 enum UCIRTXPL3_t {
113 UCIRTXPL3_OFF = 0x00, /*! Bit 3 OFF */
114 UCIRTXPL3 = 0x20 /*! Bit 3 ON */
115 };
116
117 /*! IRDA Transmit Pulse Length Bit 2 */
118 enum UCIRTXPL2_t {
119 UCIRTXPL2_OFF = 0x00, /*! Bit 2 OFF */
120 UCIRTXPL2 = 0x10 /*! Bit 2 ON */
121 };
122
123 /*! IRDA Transmit Pulse Length Bit 1 */
124 enum UCIRTXPL1_t {
125 UCIRTXPL1_OFF = 0x00, /*! Bit 1 OFF */
126 UCIRTXPL1 = 0x08 /*! Bit 1 ON */
127 };
128
129 /*! IRDA Transmit Pulse Length Bit 0 */
130 enum UCIRTXPL0_t {
131 UCIRTXPL0_OFF = 0x00, /*! Bit 0 OFF */
132 UCIRTXPL0 = 0x04 /*! Bit 0 ON */
133 };
134
135 /*! IrDA transmit pulse clock select. */
136 enum UCIRTXCLK_t {
137 UCIRTXCLK_OFF = 0x00, /*! BRCLK. */
138 UCIRTXCLK = 0x02 /*! BITCLK16 when UCOS16 = 1. Otherwise, BRCLK. */
139 };
140
141 /*! IrDA encoder/decoder enable. */
142 enum UCIREN_t {
143 UCIREN_OFF = 0x00, /*! IrDA encoder/decoder disabled. */
144 UCIREN = 0x02 /*! IrDA encoder/decoder enabled. */
145 };
146
147 /*! IRDA Receive Filter Length Bit 5 */
148 enum UCIRRXFL5_t {
149 UCIRRXFL5_OFF = 0x00, /*! Bit 5 OFF */
150 UCIRRXFL5 = 0x80 /*! Bit 5 ON */
151 };
152
153 /*! IRDA Receive Filter Length Bit 4 */
154 enum UCIRRXFL4_t {
155 UCIRRXFL4_OFF = 0x00, /*! Bit 4 OFF */
156 UCIRRXFL4 = 0x40 /*! Bit 4 ON */
157 };
158
159 /*! IRDA Receive Filter Length Bit 3 */
160 enum UCIRRXFL3_t {
161 UCIRRXFL3_OFF = 0x00, /*! Bit 3 OFF */
162 UCIRRXFL3 = 0x20 /*! Bit 3 ON */
163 };
164
165 /*! IRDA Receive Filter Length Bit 2 */
166 enum UCIRRXFL2_t {
167 UCIRRXFL2_OFF = 0x00, /*! Bit 2 OFF */
168 UCIRRXFL2 = 0x10 /*! Bit 2 ON */
169 };
170
171 /*! IRDA Receive Filter Length Bit 1 */
172 enum UCIRRXFL1_t {
173 UCIRRXFL1_OFF = 0x00, /*! Bit 1 OFF */
174 UCIRRXFL1 = 0x08 /*! Bit 1 ON */
175 };
176
177 /*! IRDA Receive Filter Length Bit 0 */
178 enum UCIRRXFL0_t {
179 UCIRRXFL0_OFF = 0x00, /*! Bit 0 OFF */
180 UCIRRXFL0 = 0x04 /*! Bit 0 ON */
181 };
182
183 /*! IrDA receive input UCAxRXD polarity. */
184 enum UCIRRXPL_t {
185 UCIRRXPL_OFF = 0x00, /*! IrDA transceiver delivers a high pulse when a light pulse is seen. */
186 UCIRRXPL = 0x02 /*! IrDA transceiver delivers a low pulse when a light pulse is seen. */
187 };
188
189 /*! IrDA receive filter enabled. */
190 enum UCIRRXFE_t {
191 UCIRRXFE_OFF = 0x00, /*! Receive filter disabled. */
192 UCIRRXFE = 0x02 /*! Receive filter enabled. */
193 };
194
195 /*! Break/synch delimiter length bit 0 */
196 enum UCDELIM0_t {
197 UCDELIM0_OFF = 0x00, /*! Break Sync Delimiter bit 0 Off */
198 UCDELIM0 = 0x02 /*! Break Sync Delimiter bit 0 On */
199 };
200
201 /*! Break/synch delimiter length bit 1 */
202 enum UCDELIM1_t {
203 UCDELIM1_OFF = 0x00, /*! Break Sync Delimiter bit 1 Off */
204 UCDELIM1 = 0x02 /*! Break Sync Delimiter bit 1 On */
205 };
206
207 /*! Synch field time out error. */
208 enum UCSTOE_t {
209 UCSTOE_OFF = 0x00, /*! No error. */
210 UCSTOE = 0x02 /*! Length of synch field exceeded measurable time. */
211 };
212
213 /*! Break time out error. */
214 enum UCBTOE_t {
215 UCBTOE_OFF = 0x00, /*! No error. */
216 UCBTOE = 0x02 /*! Length of break field exceeded 22 bit times. */
217 };
218
219 /*! Automatic baud rate detect enable. */
220 enum UCABDEN_t {
221 UCABDEN_OFF = 0x00, /*! Baud rate detection disabled. Length of break and synch field is not
222 * measured. */
223 UCABDEN = 0x02 /*! Baud rate detection enabled. Length of break and synch field is
224 * measured and baud rate settings are changed accordingly. */
225 };
226
227 /*! USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0. */
228 enum UCMODE_ASYNC_t {
229 UCMODE_0 = 0x00, /*! UART Mode. */
230 UCMODE_1 = 0x01, /*! Idle-Line Multiprocessor Mode. */
231 UCMODE_2 = 0x02, /*! Address-Bit Multiprocessor Mode. */
232 UCMODE_3 = 0x04 /*! UART Mode with automatic baud rate detection. */
233 };
234
235 /*! USCI clock source select. These bits select the BRCLK source clock. */
236 enum UCSSEL_UART_t {
237 UCSSEL_0 = 0x00, /*! UCLK */
238 UCSSEL_1 = 0x01, /*! ACLK */
239 UCSSEL_2 = 0x02 /*! SMCLK */
240
241 };
242
243 struct UCxCTL0_t {
244 UCPEN_t UCPEN; /*! Parity enable
245 * 0 Parity disabled.
246 * 1 Parity enabled. Parity bit is generated (UCAxTXD) and expected
247 * (UCAxRXD). In address-bit multiprocessor mode, the address bit is
248 * included in the parity calculation. */
249 UCPAR_t UCPAR; /*! Parity select. UCPAR is not used when parity is disabled.
250 * 0 Odd parity
251 * 1 Even parity */
252 UCMSB_t UCMSB; /*! MSB first select. Controls the direction of the receive and transmit shift
253 *register.
254 * 0 LSB first
255 * 1 MSB first */
256 UC7BIT_t UC7BIT; /*! Character length. Selects 7-bit or 8-bit character length.
257 * 0 8-bit data
258 * 1 7-bit data */
259 UCSPB_t UCSPB; /*! Stop bit select. Number of stop bits.
260 * 0 One stop bit
261 * 1 Two stop bits */
262 UCMODE_ASYNC_t UCMODE; /*! USCI mode. The UCMODEx bits select the asynchronous mode when
263 *UCSYNC = 0.
264 * 00 UART Mode.
265 * 01 Idle-Line Multiprocessor Mode.
266 * 10 Address-Bit Multiprocessor Mode.
267 * 11 UART Mode with automatic baud rate detection. */
268 UCSYNC_t UCSYNC; /*!Synchronous mode enable
269 * 0 Asynchronous mode
270 * 1 Synchronous Mode */
271 }
272
273 struct UCxCTL1_t {
274 UCSSEL_UART_t UCSSEL; /*! USCI clock source select. These bits select the BRCLK source clock.
275 * 00 UCLK
276 * 01 ACLK
277 * 10 SMCLK
278 * 11 SMCLK */
279 UCRXEIE_t UCRXEIE; /*! Receive erroneous-character interrupt-enable
280 * 0 Erroneous characters rejected and UCAxRXIFG is not set
281 * 1 Erroneous characters received will set UCAxRXIFG */
282 UCBRKIE_t UCBRKIE; /*! Receive break character interrupt-enable
283 * 0 Received break characters do not set UCAxRXIFG.
284 * 1 Received break characters set UCAxRXIFG. */
285 UCDORM_t UCDORM; /*! Dormant. Puts USCI into sleep mode.
286 * 0 Not dormant. All received characters will set UCAxRXIFG.
287 * 1 Dormant. Only characters that are preceded by an idle-line or with
288 * address bit set will set UCAxRXIFG. In UART mode with automatic baud
289 * rate detection only the combination of a break and synch field will set
290 * UCAxRXIFG. */
291 UCTXADDR_t UCTXADDR; /*! Transmit address. Next frame to be transmitted will be marked as address
292 *depending on the selected multiprocessor mode.
293 * 0 Next frame transmitted is data
294 * 1 Next frame transmitted is an address */
295 UCTXBRK_t UCTXBRK; /*! Transmit break. Transmits a break with the next write to the transmit buffer.
296 *In UART mode with automatic baud rate detection 055h must be written
297 *into UCAxTXBUF to generate the required break/synch fields. Otherwise
298 *0h must be written into the transmit buffer.
299 * 0 Next frame transmitted is not a break
300 * 1 Next frame transmitted is a break or a break/synch */
301 UCSWRST_t UCSWRST; /*! Software reset enable
302 * 0 Disabled. USCI reset released for operation.
303 * 1 Enabled. USCI logic held in reset state. */
304 }
305
306 struct UCxMCTL_t {
307 UCBRF_t UCBRF; /*! First modulation stage select. These bits determine the modulation pattern
308 *for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0. */
309 UCBRS_t UCBRS; /*! Second modulation stage select. These bits determine the modulation
310 *pattern for BITCLK. */
311 UCOS16_t UCOS16; /*! Oversampling mode enabled
312 * 0 Disabled
313 * 1 Enabled */
314 }
315
316 struct UCxSTAT_t {
317 UCLISTEN_t UCLISTEN; /*! Listen enable. The UCLISTEN bit selects loopback mode.
318 * 0 Disabled
319 * 1 Enabled. UCAxTXD is internally fed back to the receiver. */
320 UCFE_t UCFE; /*! Framing error flag
321 * 0 No error
322 * 1 Character received with low stop bit */
323 UCOE_t UCOE; /*! Overrun error flag. This bit is set when a character is transferred into
324 *UCAxRXBUF before the previous character was read. UCOE is cleared
325 *automatically when UCxRXBUF is read, and must not be cleared by
326 *software. Otherwise, it will not function correctly.
327 * 0 No error
328 * 1 Overrun error occurred */
329 UCPE_t UCPE; /*! Parity error flag. When UCPEN = 0, UCPE is read as 0.
330 * 0 No error
331 * 1 Character received with parity error */
332 UCBRK_t UCBRK; /*! Break detect flag
333 * 0 No break condition
334 * 1 Break condition occurred */
335 UCRXERR_t UCRXERR; /*! Receive error flag. This bit indicates a character was received with error(s).
336 *When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also
337 *set. UCRXERR is cleared when UCAxRXBUF is read.
338 * 0 No receive errors detected
339 * 1 Receive error detected */
340 UCADDR_t UCADDR; /*! Address received in address-bit multiprocessor mode.
341 * 0 Received character is data
342 * 1 Received character is an address */
343 UCIDLE_t UCIDLE; /*! Idle line detected in idle-line multiprocessor mode.
344 * 0 No idle line detected
345 * 1 Idle line detected */
346 UCBUSY_t UCBUSY; /*! USCI busy. This bit indicates if a transmit or receive operation is in
347 *progress.
348 * 0 USCI inactive
349 * 1 USCI transmitting or receiving */
350 }
351
352 struct UCxIRTCTL_t {
353 UCIRTXPL5_t UCIRTXPL5; /*! IRDA Transmit Pulse Length Bit 5 */
354 UCIRTXPL4_t UCIRTXPL4; /*! IRDA Transmit Pulse Length Bit 4 */
355 UCIRTXPL3_t UCIRTXPL3; /*! IRDA Transmit Pulse Length Bit 3 */
356 UCIRTXPL2_t UCIRTXPL2; /*! IRDA Transmit Pulse Length Bit 2 */
357 UCIRTXPL1_t UCIRTXPL1; /*! IRDA Transmit Pulse Length Bit 1 */
358 UCIRTXPL0_t UCIRTXPL0; /*! IRDA Transmit Pulse Length Bit 0 */
359 UCIRTXCLK_t UCIRTXCLK; /*! IrDA transmit pulse clock select
360 * 0 BRCLK
361 * 1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK */
362 UCIREN_t UCIREN; /*! IrDA encoder/decoder enable.
363 * 0 IrDA encoder/decoder disabled
364 * 1 IrDA encoder/decoder enabled */
365 }
366
367 struct UCxIRRCTL_t {
368 UCIRRXFL5_t UCIRRXFL5; /*! IRDA Receive Filter Length Bit 5 */
369 UCIRRXFL4_t UCIRRXFL4; /*! IRDA Receive Filter Length Bit 4 */
370 UCIRRXFL3_t UCIRRXFL3; /*! IRDA Receive Filter Length Bit 3 */
371 UCIRRXFL2_t UCIRRXFL2; /*! IRDA Receive Filter Length Bit 2 */
372 UCIRRXFL1_t UCIRRXFL1; /*! IRDA Receive Filter Length Bit 1 */
373 UCIRRXFL0_t UCIRRXFL0; /*! IRDA Receive Filter Length Bit 0 */
374 UCIRRXPL_t UCIRRXPL; /*! IrDA receive input UCAxRXD polarity
375 * 0 IrDA transceiver delivers a high pulse when a light pulse is seen
376 * 1 IrDA transceiver delivers a low pulse when a light pulse is seen */
377 UCIRRXFE_t UCIRRXFE; /*! IrDA receive filter enabled
378 * 0 Receive filter disabled
379 * 1 Receive filter enabled */
380 }
381
382 struct UCxABCTL_t {
383 UCDELIM1_t UCDELIM1; /*! Break/synch delimiter length
384 * 00 1 bit time
385 * 01 2 bit times
386 * 10 3 bit times
387 * 11 4 bit times */
388 UCDELIM0_t UCDELIM0; /*! Break/synch delimiter length
389 * 00 1 bit time
390 * 01 2 bit times
391 * 10 3 bit times
392 * 11 4 bit times */
393 UCSTOE_t UCSTOE; /*! Synch field time out error
394 * 0 No error
395 * 1 Length of synch field exceeded measurable time */
396 UCBTOE_t UCBTOE; /*! Break time out error
397 * 0 No error
398 * 1 Length of break field exceeded 22 bit times */
399 UCABDEN_t UCABDEN; /*! Automatic baud rate detect enable
400 * 0 Baud rate detection disabled. Length of break and synch field is not
401 * measured.
402 * 1 Baud rate detection enabled. Length of break and synch field is
403 * measured and baud rate settings are changed accordingly. */
404 }
405 }