1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*!
    34     *  ======== Timer0_A5 ========
    35     *  MSP430 Timer0_A5 timer
    36     */
    37    metaonly module Timer0_A5 inherits ITimer_A {
    38    
    39    instance:
    40    
    41        override config string name = "TimerA5";
    42    
    43        /*! Timer A5 Control Register */
    44        config TACTL_t TA0CTL = {
    45            TASSEL : TASSEL_0,
    46            ID : ID_0,
    47            MC : MC_0,
    48            TACLR : TACLR_OFF,
    49            TAIE : TAIE_OFF,
    50            TAIFG : TAIFG_OFF
    51        };
    52    
    53        /*! Capture/Compare Control 0 */
    54        config TACCTLx_t TA0CCTL0 = {
    55            CM : CM_0,
    56            CCIS : CCIS_0,
    57            SCS : SCS_OFF,
    58            SCCI : SCCI_OFF,
    59            CAP : CAP_OFF,
    60            OUTMOD : OUTMOD_0,
    61            CCIE : CCIE_OFF,
    62            CCI : CCI_OFF,
    63            OUT : OUT_OFF,
    64            COV : COV_OFF,
    65            CCIFG : CCIFG_OFF
    66        };
    67    
    68        /*! Capture/Compare Control 1 */
    69        config TACCTLx_t TA0CCTL1 = {
    70            CM : CM_0,
    71            CCIS : CCIS_0,
    72            SCS : SCS_OFF,
    73            SCCI : SCCI_OFF,
    74            CAP : CAP_OFF,
    75            OUTMOD : OUTMOD_0,
    76            CCIE : CCIE_OFF,
    77            CCI : CCI_OFF,
    78            OUT : OUT_OFF,
    79            COV : COV_OFF,
    80            CCIFG : CCIFG_OFF
    81        };
    82    
    83        /*! Capture/Compare Control 2 */
    84        config TACCTLx_t TA0CCTL2 = {
    85            CM : CM_0,
    86            CCIS : CCIS_0,
    87            SCS : SCS_OFF,
    88            SCCI : SCCI_OFF,
    89            CAP : CAP_OFF,
    90            OUTMOD : OUTMOD_0,
    91            CCIE : CCIE_OFF,
    92            CCI : CCI_OFF,
    93            OUT : OUT_OFF,
    94            COV : COV_OFF,
    95            CCIFG : CCIFG_OFF
    96        };
    97    
    98        /*! Capture/Compare Control 3 */
    99        config TACCTLx_t TA0CCTL3 = {
   100            CM : CM_0,
   101            CCIS : CCIS_0,
   102            SCS : SCS_OFF,
   103            SCCI : SCCI_OFF,
   104            CAP : CAP_OFF,
   105            OUTMOD : OUTMOD_0,
   106            CCIE : CCIE_OFF,
   107            CCI : CCI_OFF,
   108            OUT : OUT_OFF,
   109            COV : COV_OFF,
   110            CCIFG : CCIFG_OFF
   111        };
   112    
   113        /*! Capture/Compare Control 4 */
   114        config TACCTLx_t TA0CCTL4 = {
   115            CM : CM_0,
   116            CCIS : CCIS_0,
   117            SCS : SCS_OFF,
   118            SCCI : SCCI_OFF,
   119            CAP : CAP_OFF,
   120            OUTMOD : OUTMOD_0,
   121            CCIE : CCIE_OFF,
   122            CCI : CCI_OFF,
   123            OUT : OUT_OFF,
   124            COV : COV_OFF,
   125            CCIFG : CCIFG_OFF
   126        };
   127    
   128        config Bits16 TA0CCR0 = 0;                         /*! Capture/Compare 0 */
   129        config Bits16 TA0CCR1 = 0;                         /*! Capture/Compare 1 */
   130        config Bits16 TA0CCR2 = 0;                         /*! Capture/Compare 2 */
   131        config Bits16 TA0CCR3 = 0;                         /*! Capture/Compare 3 */
   132        config Bits16 TA0CCR4 = 0;                         /*! Capture/Compare 4 */
   133    
   134        /*! Timer interrupt enables */
   135        config regIntVect_t interruptSource[6];
   136    
   137        /*! Determine if each Register needs to be forced set or not */
   138        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   139        [
   140            { register : "TA0CTL"   , regForceSet : false },
   141            { register : "TA0CCTL0" , regForceSet : false },
   142            { register : "TA0CCTL1" , regForceSet : false },
   143            { register : "TA0CCTL2" , regForceSet : false },
   144            { register : "TA0CCTL3" , regForceSet : false },
   145            { register : "TA0CCTL4" , regForceSet : false },
   146            { register : "TA0CCR0"  , regForceSet : false },
   147            { register : "TA0CCR1"  , regForceSet : false },
   148            { register : "TA0CCR2"  , regForceSet : false },
   149            { register : "TA0CCR3"  , regForceSet : false },
   150            { register : "TA0CCR4"  , regForceSet : false }
   151        ];
   152    }