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32
33 import ti.catalog.msp430.peripherals.clock.CS as CS;
34
35 /*!
36 * ======== GPIO for P430FR5736_32_26_22 ========
37 * MSP430 General Purpose Input Output Ports
38 */
39 metaonly module GPIO_MSP430FR5736_32_26_22 inherits IGPIO {
40 /*!
41 * ======== create ========
42 * Create an instance of this peripheral. Use a customized
43 * init function so that we can get access to the CS
44 * instances.
45 */
46 create(CS.Instance clock);
47
48 instance:
49 /*! @_nodoc */
50 config CS.Instance clock;
51
52 /*! Define an array to describe all device pins. The 1st dimension
53 * denotes the port, the second the pin on that port. On an
54 * MSP430FR57xx device, there are 3 + 2 = 10 pins total.
55 */
56
57 58
59 config DevicePin_t devicePins[3][8];
60
61 /*! Implementation of Device Pin Functional Configuration */
62 override config DevicePinFunctionSetting_t devicePinSetting[3][8];
63
64 /*! Determine if each Register needs to be forced set or not */
65 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
66 [
67 { register : "P1OUT" , regForceSet : true },
68 { register : "P1SEL0" , regForceSet : false },
69 { register : "P1SEL1" , regForceSet : false },
70 { register : "P1DIR" , regForceSet : true },
71 { register : "P1REN" , regForceSet : false },
72 { register : "P1IES" , regForceSet : true },
73 { register : "P1IFG" , regForceSet : true },
74 { register : "P1IE" , regForceSet : false },
75 { register : "P2OUT" , regForceSet : true },
76 { register : "P2SEL0" , regForceSet : false },
77 { register : "P2SEL1" , regForceSet : false },
78 { register : "P2DIR" , regForceSet : true },
79 { register : "P2REN" , regForceSet : false },
80 { register : "P2IES" , regForceSet : true },
81 { register : "P2IFG" , regForceSet : true },
82 { register : "P2IE" , regForceSet : false },
83 { register : "PJOUT" , regForceSet : true },
84 { register : "PJSEL0" , regForceSet : false },
85 { register : "PJSEL1" , regForceSet : false },
86 { register : "PJDIR" , regForceSet : true },
87 { register : "PJREN" , regForceSet : false }
88 ];
89
90 91 92 93 94 95
96
97 /*! Port 1 Output Register */
98 config GpioBits8PxOut_t P1OUT = {
99 Bit0 : BIT0_OFF,
100 Bit1 : BIT1_OFF,
101 Bit2 : BIT2_OFF,
102 Bit3 : BIT3_OFF,
103 Bit4 : BIT4_OFF,
104 Bit5 : BIT5_OFF,
105 Bit6 : BIT6_OFF,
106 Bit7 : BIT7_OFF
107 };
108
109 /*! Port 1 Port Select Register 0 */
110 config GpioBits8PxSel_t P1SEL0 = {
111 Bit0 : BIT0_OFF,
112 Bit1 : BIT1_OFF,
113 Bit2 : BIT2_OFF,
114 Bit3 : BIT3_OFF,
115 Bit4 : BIT4_OFF,
116 Bit5 : BIT5_OFF,
117 Bit6 : BIT6_OFF,
118 Bit7 : BIT7_OFF
119 };
120
121 /*! Port 1 Port Select Register 1 */
122 config GpioBits8PxSel_t P1SEL1 = {
123 Bit0 : BIT0_OFF,
124 Bit1 : BIT1_OFF,
125 Bit2 : BIT2_OFF,
126 Bit3 : BIT3_OFF,
127 Bit4 : BIT4_OFF,
128 Bit5 : BIT5_OFF,
129 Bit6 : BIT6_OFF,
130 Bit7 : BIT7_OFF
131 };
132
133 /*! Port 1 Direction Register */
134 config GpioBits8PxDir_t P1DIR = {
135 Bit0 : BIT0_OFF,
136 Bit1 : BIT1_OFF,
137 Bit2 : BIT2_OFF,
138 Bit3 : BIT3_OFF,
139 Bit4 : BIT4_OFF,
140 Bit5 : BIT5_OFF,
141 Bit6 : BIT6_OFF,
142 Bit7 : BIT7_OFF
143 };
144
145 /*! Port 1 Resistor Enable Register */
146 config GpioBits8PxRen_t P1REN = {
147 Bit0 : BIT0_OFF,
148 Bit1 : BIT1_OFF,
149 Bit2 : BIT2_OFF,
150 Bit3 : BIT3_OFF,
151 Bit4 : BIT4_OFF,
152 Bit5 : BIT5_OFF,
153 Bit6 : BIT6_OFF,
154 Bit7 : BIT7_OFF
155 };
156
157 /*! Port 2 Output Register */
158 config GpioBits8PxOut_t P2OUT = {
159 Bit0 : BIT0_OFF,
160 Bit1 : BIT1_OFF,
161 Bit2 : BIT2_OFF,
162 Bit3 : BIT3_OFF,
163 Bit4 : BIT4_OFF,
164 Bit5 : BIT5_OFF,
165 Bit6 : BIT6_OFF,
166 Bit7 : BIT7_OFF
167 };
168
169 /*! Port 2 Port Select Register 0 */
170 config GpioBits8PxSel_t P2SEL0 = {
171 Bit0 : BIT0_OFF,
172 Bit1 : BIT1_OFF,
173 Bit2 : BIT2_OFF,
174 Bit3 : BIT3_OFF,
175 Bit4 : BIT4_OFF,
176 Bit5 : BIT5_OFF,
177 Bit6 : BIT6_OFF,
178 Bit7 : BIT7_OFF
179 };
180
181 /*! Port 2 Port Select Register 1 */
182 config GpioBits8PxSel_t P2SEL1 = {
183 Bit0 : BIT0_OFF,
184 Bit1 : BIT1_OFF,
185 Bit2 : BIT2_OFF,
186 Bit3 : BIT3_OFF,
187 Bit4 : BIT4_OFF,
188 Bit5 : BIT5_OFF,
189 Bit6 : BIT6_OFF,
190 Bit7 : BIT7_OFF
191 };
192
193 /*! Port 2 Direction Register */
194 config GpioBits8PxDir_t P2DIR = {
195 Bit0 : BIT0_OFF,
196 Bit1 : BIT1_OFF,
197 Bit2 : BIT2_OFF,
198 Bit3 : BIT3_OFF,
199 Bit4 : BIT4_OFF,
200 Bit5 : BIT5_OFF,
201 Bit6 : BIT6_OFF,
202 Bit7 : BIT7_OFF
203 };
204
205 /*! Port 2 Resistor Enable Register */
206 config GpioBits8PxRen_t P2REN = {
207 Bit0 : BIT0_OFF,
208 Bit1 : BIT1_OFF,
209 Bit2 : BIT2_OFF,
210 Bit3 : BIT3_OFF,
211 Bit4 : BIT4_OFF,
212 Bit5 : BIT5_OFF,
213 Bit6 : BIT6_OFF,
214 Bit7 : BIT7_OFF
215 };
216
217 /*! Port J Output Register */
218 config GpioBits8PxOut_t PJOUT = {
219 Bit0 : BIT0_OFF,
220 Bit1 : BIT1_OFF,
221 Bit2 : BIT2_OFF,
222 Bit3 : BIT3_OFF,
223 Bit4 : BIT4_OFF,
224 Bit5 : BIT5_OFF,
225 Bit6 : BIT6_OFF,
226 Bit7 : BIT7_OFF
227 };
228
229 /*! Port J Port Select Register 0 */
230 config GpioBits8PxSel_t PJSEL0 = {
231 Bit0 : BIT0_OFF,
232 Bit1 : BIT1_OFF,
233 Bit2 : BIT2_OFF,
234 Bit3 : BIT3_OFF,
235 Bit4 : BIT4_OFF,
236 Bit5 : BIT5_OFF,
237 Bit6 : BIT6_OFF,
238 Bit7 : BIT7_OFF
239 };
240
241 /*! Port J Port Select Register 1 */
242 config GpioBits8PxSel_t PJSEL1 = {
243 Bit0 : BIT0_OFF,
244 Bit1 : BIT1_OFF,
245 Bit2 : BIT2_OFF,
246 Bit3 : BIT3_OFF,
247 Bit4 : BIT4_OFF,
248 Bit5 : BIT5_OFF,
249 Bit6 : BIT6_OFF,
250 Bit7 : BIT7_OFF
251 };
252
253 /*! Port J Direction Register */
254 config GpioBits8PxDir_t PJDIR = {
255 Bit0 : BIT0_OFF,
256 Bit1 : BIT1_OFF,
257 Bit2 : BIT2_OFF,
258 Bit3 : BIT3_OFF,
259 Bit4 : BIT4_OFF,
260 Bit5 : BIT5_OFF,
261 Bit6 : BIT6_OFF,
262 Bit7 : BIT7_OFF
263 };
264
265 /*! Port J Resistor Enable Register */
266 config GpioBits8PxRen_t PJREN = {
267 Bit0 : BIT0_OFF,
268 Bit1 : BIT1_OFF,
269 Bit2 : BIT2_OFF,
270 Bit3 : BIT3_OFF,
271 Bit4 : BIT4_OFF,
272 Bit5 : BIT5_OFF,
273 Bit6 : BIT6_OFF,
274 Bit7 : BIT7_OFF
275 };
276 }