1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    
    34    /*!
    35     *  ======== BSCplus ========
    36     *  MSP430 Basic Clock System
    37     */
    38    metaonly module BCSplus inherits IClock
    39    {
    40        /*! MOD0 Bit */
    41        enum MOD0_t {
    42            MOD0_OFF = 0x00,    /*! Disable MOD0 bit */
    43            MOD0 = 0x01         /*! Enable MOD0 bit */
    44        };
    45    
    46        /*! MOD1 Bit */
    47        enum MOD1_t {
    48            MOD1_OFF = 0x00,    /*! Disable MOD1 bit */
    49            MOD1 = 0x02         /*! Enable MOD1 bit */
    50        };
    51    
    52        /*! MOD2 Bit */
    53        enum MOD2_t {
    54            MOD2_OFF = 0x00,    /*! Disable MOD2 bit */
    55            MOD2 = 0x04         /*! Enable MOD2 bit */
    56        };
    57    
    58        /*! MOD3 Bit */
    59        enum MOD3_t {
    60            MOD3_OFF = 0x00,    /*! Disable MOD3 bit */
    61            MOD3 = 0x08         /*! Enable MOD3 bit */
    62        };
    63    
    64        /*! MOD4 Bit */
    65        enum MOD4_t {
    66            MOD4_OFF = 0x00,    /*! Disable MOD4 bit */
    67            MOD4 = 0x10         /*! Enable MOD4 bit */
    68        };
    69    
    70        /*! DCO0 Bit */
    71        enum DCO0_t {
    72            DCO0_OFF = 0x00,    /*! Disable DCO0 bit */
    73            DCO0 = 0x20         /*! Enable DCO0 bit */
    74        };
    75    
    76        /*! DCO1 Bit */
    77        enum DCO1_t {
    78            DCO1_OFF = 0x00,    /*! Disable DCO1 bit */
    79            DCO1 = 0x40         /*! Enable DCO1 bit */
    80        };
    81    
    82        /*! DCO2 Bit */
    83        enum DCO2_t {
    84            DCO2_OFF = 0x00,    /*! Disable DCO2 bit */
    85            DCO2 = 0x80         /*! Enable DCO2 bit */
    86        };
    87    
    88        enum XT2OFF_t {
    89            XT2OFF_OFF = 0x00,  /*! Enable XT2CLK */
    90            XT2OFF = 0x80       /*! Disable XT2CLK */
    91        };
    92    
    93        enum XTS_t {
    94            XTS_OFF = 0x00,     /*! Low Frequency */
    95            XTS = 0x40          /*! High Frequency */
    96        };
    97    
    98        enum RSEL0_t {
    99            RSEL0_OFF = 0x00,   /*! Disable RSEL0 bit */
   100            RSEL0 = 0x01        /*! Enable RSEL0 bit */
   101        };
   102    
   103        enum RSEL1_t {
   104            RSEL1_OFF = 0x00,   /*! Disable RSEL1 bit */
   105            RSEL1 = 0x02        /*! Enable RSEL1 bit */
   106        };
   107    
   108        enum RSEL2_t {
   109            RSEL2_OFF = 0x00,   /*! Disable RSEL2 bit */
   110            RSEL2 = 0x04        /*! Enable RSEL2 bit */
   111        };
   112    
   113        enum RSEL3_t {
   114            RSEL3_OFF = 0x00,   /*! Disable RSEL3 bit */
   115            RSEL3 = 0x08        /*! Enable RSEL3 bit */
   116        };
   117    
   118        /*! MCLK Source Select */
   119        enum SELM_t {
   120            SELM_0 = 0x00,      /*! DCOCLK */
   121    /*        SELM_1 = 0x40,       DCOCLK */
   122            SELM_2 = 0x80,      /*! XT2CLK/LFXTCLK */
   123            SELM_3 = 0xC0       /*! LFXTCLK */
   124        };
   125    
   126        /*! ACLK Divider values */
   127        enum DIVA_t {
   128            DIVA_0 = 0x00,      /*! Divide by 1 */
   129            DIVA_1 = 0x10,      /*! Divide by 2 */
   130            DIVA_2 = 0x20,      /*! Divide by 4 */
   131            DIVA_3 = 0x30       /*! Divide by 8 */
   132        };
   133    
   134        /*! MCLK Divider values */
   135        enum DIVM_t {
   136            DIVM_0 = 0x00,      /*! Divide by 1 */
   137            DIVM_1 = 0x10,      /*! Divide by 2 */
   138            DIVM_2 = 0x20,      /*! Divide by 4 */
   139            DIVM_3 = 0x30       /*! Divide by 8 */
   140        };
   141    
   142        /*! SMCLK Divider values */
   143        enum DIVS_t {
   144            DIVS_0 = 0x00,      /*! Divide by 1 */
   145            DIVS_1 = 0x02,      /*! Divide by 2 */
   146            DIVS_2 = 0x04,      /*! Divide by 4 */
   147            DIVS_3 = 0x06       /*! Divide by 8 */
   148        };
   149    
   150        enum SELS_t {
   151            SELS_OFF = 0x00,    /*! DCOCLK */
   152            SELS = 0x08         /*! XT2CLK when XT2 oscillator present. LFXT1CLK or VLOCLK when XT2 oscillator not present */
   153        };
   154    
   155        enum DCOR_t {
   156            DCOR_OFF = 0x00,    /*! DCO uses internal resistor */
   157            DCOR = 0x01         /*! DCO uses external resistor */
   158        };
   159    
   160        /*! XT2 frequency range select */
   161        enum XT2S_t {
   162            XT2S_0 = 0x00,      /*! 0.4 - 1 MHz */
   163            XT2S_1 = 0x40,      /*! 1 - 3 MHz */
   164            XT2S_2 = 0x80,      /*! 3 - 16 MHz */
   165            XT2S_3 = 0xC0       /*! Digital input signal */
   166        };
   167    
   168        enum LFXT1S_t {
   169            LFXT1S_0 = 0x00,    /*! If XTS = 0, XT1 = 32768kHz Crystal ; If XTS = 1, XT1 = 0.4 - 1-MHz crystal or resonator */
   170            LFXT1S_1 = 0x10,    /*! If XTS = 0, XT1 = Reserved ; If XTS = 1, XT1 = 1 - 3-MHz crystal or resonator */
   171            LFXT1S_2 = 0x20,    /*! If XTS = 0, XT1 = VLOCLK ; If XTS = 1, XT1 = 3 - 16-MHz crystal or resonator */
   172            LFXT1S_3 = 0x30     /*! If XTS = 0, XT1 = Digital External ; If XTS = 1, XT1 = 0.4 - 16-MHz Digital External */
   173        };
   174    
   175        enum XCAP_t {
   176            XCAP_0 = 0x00,      /*! ~1 pF */
   177            XCAP_1 = 0x04,      /*! ~6 pF */
   178            XCAP_2 = 0x08,      /*! ~10 pF */
   179            XCAP_3 = 0x0C       /*! ~12.5 pF */
   180        };
   181    
   182        enum XT2OF_t {
   183            XT2OF_OFF = 0x00,   /*! No fault condition present */
   184            XT2OF = 0x02        /*! XT2 fault condition present */
   185        };
   186    
   187        enum LFXT1OF_t {
   188            LFXT1OF_OFF = 0x00, /*! No fault condition present */
   189            LFXT1OF = 0x01      /*! LFXT1 fault condition present */
   190        };
   191    
   192        struct DCOCTL_t {
   193            MOD0_t    MOD0;     /*! Modulation Bit 0 */
   194            MOD1_t    MOD1;     /*! Modulation Bit 1 */
   195            MOD2_t    MOD2;     /*! Modulation Bit 2 */
   196            MOD3_t    MOD3;     /*! Modulation Bit 3 */
   197            MOD4_t    MOD4;     /*! Modulation Bit 4 */
   198            DCO0_t    DCO0;     /*! DCO Select Bit 0 */
   199            DCO1_t    DCO1;     /*! DCO Select Bit 1 */
   200            DCO2_t    DCO2;     /*! DCO Select Bit 2 */
   201        }
   202    
   203        /*!
   204         *  ======== BCSCTL1_t ========
   205         *  BCS Control Register 1
   206         *
   207         *  @field(XT2OFF)  This bit turns off the XT2 oscillator: 0 - XT2 is on,
   208         *                  1 - XT2 is off if it is not used for MCLK or SMCLK
   209         *
   210         *  @field(XTS)     0 - Low frequency mode; 1 - High frequency mode
   211         */
   212        struct BCSCTL1_t {
   213            XT2OFF_t  XT2OFF;       /*! XT2 off. This bit turns off the XT2 oscillator
   214                                      *  0  XT2 is on
   215                                      *  1  XT2 is off if it is not used for MCLK or SMCLK. */
   216            XTS_t     XTS;          /*! LFXT1 mode select.
   217                                       *  0  Low frequency mode
   218                                       *  1  High frequency mode */
   219            DIVA_t    DIVA;         /*! Divider for ACLK
   220                                      *  00  /1
   221                                      *  01  /2
   222                                      *  10  /4
   223                                      *  11  /8 */
   224            RSEL0_t   RSEL0;        /*! Range select bit 0 */
   225            RSEL1_t   RSEL1;        /*! Range select bit 1 */
   226            RSEL2_t   RSEL2;        /*! Range select bit 2 */
   227            RSEL3_t   RSEL3;        /*! Range select bit 3 */
   228        }
   229    
   230        /*!
   231         *  ======== BCSCTL2_t ========
   232         *  BCS Control Register 2
   233         *
   234         *  @field(SELM) These bits select the MCLK source.
   235         *  @field(SELS) These bits select the SMCLK source. When
   236         *               XT2 oscillator present, 0 selects DCOCLK and
   237         *               1 selects XT2CLK; otherwise 0 selects LFXT1CLK and
   238         *               1 selects VLOCLK.
   239         *  @field(DCOR) 0 - Internal resistor, 1 - external resistor
   240         */
   241        struct BCSCTL2_t {
   242            SELM_t    SELM;         /*! Select MCLK. These bits select the MCLK source.
   243                                      *  00  DCOCLK
   244                                      *  01  DCOCLK
   245                                      *  10  XT2CLK when XT2 oscillator present on-chip. LFXT1CLK or VLOCLK
   246                                      *      when XT2 oscillator not present on-chip.
   247                                      *  11  LFXT1CLK or VLOCLK */
   248            DIVM_t    DIVM;         /*! Divider for MCLK
   249                                      *  00  /1
   250                                      *  01  /2
   251                                      *  10  /4
   252                                      *  11  /8 */
   253            SELS_t    SELS;         /*! Select SMCLK. This bit selects the SMCLK source.
   254                                      *  0  DCOCLK
   255                                      *  1  XT2CLK when XT2 oscillator present. LFXT1CLK or VLOCLK when
   256                                      *     XT2 oscillator not present */
   257            DIVS_t    DIVS;         /*! Divider for SMCLK
   258                                      *  00  /1
   259                                      *  01  /2
   260                                      *  10  /4
   261                                      *  11  /8 */
   262            DCOR_t    DCOR;         /*! DCO resistor select
   263                                      *  0  Internal resistor
   264                                      *  1  External resistor */
   265        }
   266    
   267        /*!
   268         *  ======== BCSCTL3_t ========
   269         *  BCS Control register 3
   270         *
   271         *  @field(LFXT1S)  These bits select between LFXT1 and VLO and XTS = 0,
   272         *                  and select the frequency range for LFXT1 when XTS = 1
   273         *  @field(XCAP)    These bits select the effective capacitance seen by
   274         *                  the LFXT1 crystal when XTS = 0. If XTS = 1 or if
   275         *                  LFCT1Sx = 11, then XCAPx should be 00.
   276         */
   277        struct BCSCTL3_t {
   278            XT2S_t    XT2S;         /*! XT2 range select. These bits select the frequency range for XT2.
   279                                      *  00  0.4 - 1-MHz crystal or resonator
   280                                      *  01  1 - 3-MHz crystal or resonator
   281                                      *  10  3 - 16-MHz crystal or resonator
   282                                      *  11  Digital external 0.4 - 16-MHz clock source */
   283            LFXT1S_t  LFXT1S;       /*! Low-frequency clock select and LFXT1 range select. These bits select
   284                                      * between LFXT1 and VLO when XTS = 0, and select the frequency range
   285                                      * for LFXT1 when XTS = 1
   286                                      *
   287                                      *  When XTS = 0:
   288                                      *  00  32768 Hz Crystal on LFXT1
   289                                      *  01  Reserved
   290                                      *  10  VLOCLK (Reserved in MSP430x21x1 devices)
   291                                      *  11  Digital external clock source
   292                                      *
   293                                      *  When XTS = 1 (Not applicable for MSP430x20xx devices)
   294                                      *  00  0.4 - 1-MHz crystal or resonator
   295                                      *  01  1 - 3-MHz crystal or resonator
   296                                      *  10  3 - 16-MHz crystal or resonator
   297                                      *  11  Digital external 0.4 - 16-MHz clock source */
   298            XCAP_t    XCAP;         /*! Oscillator capacitor selection. These bits select the effective capacitance
   299                                      * seen by the LFXT1 crystal when XTS = 0. If XTS = 1 or if LFCT1Sx = 11
   300                                      * XCAPx should be 00.
   301                                      *  00  ~1 pF
   302                                      *  01  ~6 pF
   303                                      *  10  ~10 pF
   304                                      *  11  ~12.5 pF */
   305            XT2OF_t   XT2OF;        /*! XT2 oscillator fault
   306                                      *  0  No fault condition present
   307                                      *  1  Fault condition present */
   308            LFXT1OF_t LFXT1OF;      /*! LFXT1 oscillator fault
   309                                      *  0  No fault condition present
   310                                      *  1  Fault condition present */
   311        }
   312    
   313    instance:
   314    
   315        /*! DCO Clock Frequency Control */
   316        config DCOCTL_t DCOCTL = {
   317            MOD0        : MOD0_OFF,
   318            MOD1        : MOD1_OFF,
   319            MOD2        : MOD2_OFF,
   320            MOD3        : MOD3_OFF,
   321            MOD4        : MOD4_OFF,
   322            DCO0        : DCO0,
   323            DCO1        : DCO1,
   324            DCO2        : DCO2_OFF,
   325        };
   326    
   327        /*! Basic Clock System Control 1 */
   328        config BCSCTL1_t  BCSCTL1 = {
   329            XT2OFF      : XT2OFF,
   330            XTS         : XTS_OFF,
   331            DIVA        : DIVA_0,
   332            RSEL0       : RSEL0,
   333            RSEL1       : RSEL1,
   334            RSEL2       : RSEL2,
   335            RSEL3       : RSEL3_OFF
   336        };
   337    
   338        /*! Basic Clock System Control 2 */
   339        config BCSCTL2_t  BCSCTL2 = {
   340            SELM        : SELM_0,
   341            DIVM        : DIVM_0,
   342            SELS        : SELS_OFF,
   343            DIVS        : DIVS_0,
   344            DCOR        : DCOR_OFF
   345        };
   346    
   347        /*! Basic Clock System Control 3 */
   348        config BCSCTL3_t  BCSCTL3 = {
   349            XT2S        : XT2S_0,
   350            LFXT1S      : LFXT1S_0,
   351            XCAP        : XCAP_1
   352        };
   353    
   354        /*! Determine if each Register needs to be forced set or not */
   355        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   356        [
   357            { register : "DCOCTL"  , regForceSet : false },
   358            { register : "BCSCTL1" , regForceSet : false },
   359            { register : "BCSCTL2" , regForceSet : false },
   360            { register : "BCSCTL3" , regForceSet : false }
   361        ];
   362    
   363        /*! Basic Clock System + pre-calibrated system frequency */
   364        config UInt preCalibratedValues = 0;
   365    
   366        /*!
   367         *  ======== preCalibratedValues truth table ========
   368         *
   369         *  hasAllCal = false
   370         *    UInt - Description
   371         *       0 - 1 MHz
   372         *       1 - Custom
   373         *
   374         *  hasAllCal = true
   375         *    UInt - Description
   376         *       0 - 1 MHz
   377         *       1 - 8 MHz
   378         *       2 - 12 MHz
   379         *       3 - 16 MHz
   380         *       4 - Custom
   381         */
   382        config String preCalibratedValuesItems[length];
   383    
   384        config float VLOCLKHz = 12000;
   385        config float WATCHCRYSTALCLKHz = 32768;
   386        config float LFXT1CLKHz = 0;
   387        config float XT2CLKHz = 0;
   388    
   389        /*!
   390         *  ======== enableXT2 ========
   391         *  Set whether XT2 is used on the device. This is different than hasXT2
   392         *  variable.
   393         */
   394        config Bool enableXT2 = false;
   395    }