1    /* 
     2     *  Copyright (c) 2008 Texas Instruments. All rights reserved.
     3     *  This program and the accompanying materials are made available under the
     4     *  terms of the Eclipse Public License v1.0 and Eclipse Distribution License
     5     *  v. 1.0 which accompanies this distribution. The Eclipse Public License is
     6     *  available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse
     7     *  Distribution License is available at
     8     *  http://www.eclipse.org/org/documents/edl-v10.php.
     9     *
    10     *  Contributors:
    11     *      Texas Instruments - initial implementation
    12     * */
    13    /*
    14     *  ======== ICacheSupport.xdc ========
    15     */
    16    
    17    import xdc.runtime.Error;
    18    
    19    /*!
    20     *  ======== ICacheSupport ========
    21     *  Interface for OS specific back-end.
    22     *
    23     *  The {@link xdc.runtime.knl} package contains modules that provide typical
    24     *  OS services. These xdc.runtime.knl modules require proxies to be
    25     *  bound to an OS specific delegate. This specifies the interface to
    26     *  be implemented by the OS specific delegate for
    27     *  {@link xdc.runtime.knl#Cache} module.
    28     *
    29     */
    30    @DirectCall
    31    
    32    interface ICacheSupport
    33    {
    34        /*!
    35         *  ======== inv ========
    36         *  Invalidates range of memory.
    37         *
    38         *  Invalidate the range of memory within the specified starting
    39         *  address and byte count.  The range of addresses operated on
    40         *  gets quantized to whole cache lines in each cache.  All lines
    41         *  in range are invalidated for all the 'type' caches.
    42         *
    43         *  @param(blockPtr) start address of range to be invalidated
    44         *  @param(byteCnt)  number of bytes to be invalidated
    45         *  @param(wait)     wait until the operation is completed
    46         *  @param(eb)       error block
    47         *  @a(returns)  true for success; false for error.
    48         */
    49        Bool inv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
    50    
    51        /*!
    52         *  ======== wb ========
    53         *  Writes a range of memory from all cache(s)
    54         *
    55         *  Writes the range of memory within the specified starting
    56         *  address and byte count.  The range of addresses operated on
    57         *  gets quantized to whole cache lines in each cache.  All lines
    58         *  within the range are left valid in the 'type' caches and the data
    59         *  within the range will be written      to the source memory.
    60         *
    61         *  @param(blockPtr) start address of range to be invalidated
    62         *  @param(byteCnt)  number of bytes to be invalidated
    63         *  @param(wait)     wait until the operation is completed
    64         *  @param(eb)       error block
    65         *  @a(returns)  true for success; false for error.
    66         */
    67        Bool wb(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
    68    
    69        /*!
    70         *  ======== wbInv ========
    71         *  Writes back and invalidates range fo memory.
    72         *
    73         *  Writes and invalidates the range of memory within the
    74         *  specified starting address and byte count.  The range of
    75         *  addresses operated on gets quantized to whole cache lines in
    76         *  each cache.  All lines within the range are written      to the
    77         *  source memory and then invalidated for all 'type' caches.
    78         *
    79         *  @param(blockPtr) start address of range to be invalidated
    80         *  @param(byteCnt)  number of bytes to be invalidated
    81         *  @param(wait)     wait until the operation is completed
    82         *  @param(eb)       error block
    83         *  @a(returns)  true for success; false for error.
    84         */
    85        Bool wbInv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
    86    
    87        /*!
    88         *  ======== wait ========
    89         *  Wait for a previous cache operation to complete
    90         *
    91         *  Wait for the cache wb/wbInv/inv operation to complete.  A cache
    92         *  operation is not truly complete until it has worked its way
    93         *  through all buffering and all memory writes have landed in the
    94         *  source memory.
    95         *
    96         *  @a(returns)  true for success; false for error.
    97         */
    98        Bool wait(Error.Block *eb);
    99    
   100    }
   101    /*
   102     *  @(#) xdc.runtime.knl; 1, 0, 0,0; 2-20-2019 10:22:55; /db/ztree/library/trees/xdc/xdc-F09/src/packages/
   103     */
   104