1 /* 2 * Copyright (c) 2016, Texas Instruments Incorporated 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 import ti.catalog.msp430.peripherals.clock.IClock; 34 35 /*! 36 * Enhanced Univerisal Serial Communication Interface A1 37 */ 38 metaonly module EUSCI_A1 inherits IEUSCI { 39 40 /* 41 * ======== create ======== 42 */ 43 create(IClock.Instance clock); 44 45 instance: 46 /*! @_nodoc */ 47 config IClock.Instance clock; 48 49 /*! 50 * ======== baseAddr ======== 51 * Address of the peripheral's control register. 52 * 53 * A peripheral's registers are commonly accessed through a structure 54 * that defines the offsets of a particular register from the lowest 55 * address mapped to a peripheral. That lowest address is specified by 56 * this parameter. 57 */ 58 config UInt baseAddr; 59 60 /*! USI interrupt enables */ 61 config regIntVect_t interruptSource[2]; 62 63 /*! Determine if each Register needs to be forced set or not */ 64 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] = 65 [ 66 ]; 67 }