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32
33 /*!
34 * ======== ITimer_B ========
35 * MSP430 ITimer_B interface
36 */
37 metaonly interface ITimer_B inherits ITimer {
38
39 enum TBCLGRP_t {
40 TBCLGRP_0 = (0*0x100u),
41 TBCLGRP_1 = (1*0x100u),
42 TBCLGRP_2 = (2*0x100u),
43 TBCLGRP_3 = 3*0x100u
44 };
45
46 enum CNTL_t {
47 CNTL_0 = (0*0x100u), /*! 16-bit, TBR(max) = 0FFFFh */
48 CNTL_1 = (1*0x100u), /*! 12-bit, TBR(max) = 0FFFh */
49 CNTL_2 = (2*0x100u), /*! 10-bit, TBR(max) = 03FFh */
50 CNTL_3 = 3*0x100u /*! 8-bit, TBR(max) = 0FFh */
51 };
52
53 enum TBSSEL_t {
54 TBSSEL_0 = (0*0x100u), /*! TBCLK */
55 TBSSEL_1 = (1*0x100u), /*! ACLK */
56 TBSSEL_2 = (2*0x100u), /*! SMCLK */
57 TBSSEL_3 = 3*0x100u /*! INCLK */
58 };
59
60 enum TBCLR_t {
61 TBCLR_OFF = (0x0000),
62 TBCLR = 0x0004
63 };
64
65 enum TBIE_t {
66 TBIE_OFF = (0x0000),
67 TBIE = 0x0002
68 };
69
70 enum TBIFG_t {
71 TBIFG_OFF = (0x000),
72 TBIFG = (0x0001)
73 };
74
75 enum MC_t {
76 MC_0 = (0*0x10u), /*! Stop Mode */
77 MC_1 = (1*0x10u), /*! Up Mode */
78 MC_2 = (2*0x10u), /*! Continuous Mode */
79 MC_3 = 3*0x10u /*! Up/Down Mode */
80 };
81
82 enum ID_t {
83 ID_0 = (0*0x40u), /*! Divider - /1 */
84 ID_1 = (1*0x40u), /*! Divider - /2 */
85 ID_2 = (2*0x40u), /*! Divider - /4 */
86 ID_3 = 3*0x40u /*! Divider - /8 */
87 };
88
89 enum CM_t {
90 CM_0 = (0*0x4000u), /*! No Capture */
91 CM_1 = (1*0x4000u), /*! Rising Edge */
92 CM_2 = (2*0x4000u), /*! Falling Edge */
93 CM_3 = 3*0x4000u /*! Both Edges */
94 };
95
96 enum CCIS_t {
97 CCIS_0 = (0*0x1000u), /*! CCIxA */
98 CCIS_1 = (1*0x1000u), /*! CCIxB */
99 CCIS_2 = (2*0x1000u), /*! GND */
100 CCIS_3 = 3*0x1000u /*! Vcc */
101 };
102
103 enum SCS_t {
104 SCS_OFF = (0x0000),
105 SCS = 0x0800
106 };
107
108 enum CLLD_t {
109 CLLD_0 = (0*0x1000u),
110 CLLD_1 = (1*0x1000u),
111 CLLD_2 = (2*0x1000u),
112 CLLD_3 = 3*0x1000u
113 };
114
115 enum SCCI_t {
116 SCCI_OFF = (0x0000),
117 SCCI = 0x0400
118 };
119
120 enum CAP_t {
121 CAP_OFF = (0x0000),
122 CAP = 0x0100
123 };
124
125 enum CCIE_t {
126 CCIE_OFF = (0x0000),
127 CCIE = (0x0010)
128 };
129
130 enum CCI_t {
131 CCI_OFF = (0x0008),
132 CCI = (0x0008)
133 };
134
135 enum OUT_t {
136 OUT_OFF = (0x0000),
137 OUT = (0x0004)
138 };
139
140 enum COV_t {
141 COV_OFF = (0x0000),
142 COV = (0x0002)
143 };
144
145 enum CCIFG_t {
146 CCIFG_OFF = (0x0000),
147 CCIFG = (0x0001)
148 };
149
150 enum OUTMOD_t {
151 OUTMOD_0 = (0*0x20u), /*! PWM output mode: 0 - OUT bit value */
152 OUTMOD_1 = (1*0x20u), /*! PWM output mode: 1 - Set */
153 OUTMOD_2 = (2*0x20u), /*! PWM output mode: 2 - PWM toggle/reset */
154 OUTMOD_3 = (3*0x20u), /*! PWM output mode: 3 - PWM set/reset */
155 OUTMOD_4 = (4*0x20u), /*! PWM output mode: 4 - Toggle */
156 OUTMOD_5 = (5*0x20u), /*! PWM output mode: 5 - Reset */
157 OUTMOD_6 = (6*0x20u), /*! PWM output mode: 6 - PWM toggle/set */
158 OUTMOD_7 = 7*0x20u /*! PWM output mode: 7 - PWM reset/set */
159 };
160
161 /*!
162 * ======== TBCTL_t ========
163 * Timer_B Control Register
164 *
165 * @see #TBCTL_t
166 */
167 struct TBCTL_t {
168 TBCLGRP_t TBCLGRP; /*! TBCLx group
169 * 00 Each TBCLx latch loads independently
170 * 01 TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update)
171 * TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update)
172 * TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update)
173 * TBCL0 independent
174 * 10 TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update)
175 * TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update)
176 * TBCL0 independent
177 * 11 TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6
178 * (TBCCR1 CLLDx bits control the update) */
179 CNTL_t CNTL; /*! Counter Length
180 * 00 16-bit, TBR(max) = 0FFFFh
181 * 01 12-bit, TBR(max) = 0FFFh
182 * 10 10-bit, TBR(max) = 03FFh
183 * 11 8-bit, TBR(max) = 0FFh */
184 TBSSEL_t TBSSEL; /*! Timer_B clock source select.
185 * 00 TBCLK
186 * 01 ACLK
187 * 10 SMCLK
188 * 11 Inverted TBCLK */
189 ID_t ID; /*! Input divider. These bits select the divider for the input clock.
190 * 00 /1
191 * 01 /2
192 * 10 /4
193 * 11 /8 */
194 MC_t MC; /*! Mode control. Setting MCx = 00h when Timer_B is not in use conserves
195 * power.
196 * 00 Stop mode: the timer is halted
197 * 01 Up mode: the timer counts up to TBCL0
198 * 10 Continuous mode: the timer counts up to the value set by CNTLx
199 * 11 Up/down mode: the timer counts up to TBCL0 and down to 0000h */
200 TBCLR_t TBCLR; /*! Timer_B clear. Setting this bit resets TBR, the clock divider, and the count
201 * direction. The TBCLR bit is automatically reset and is always read as zero. */
202 TBIE_t TBIE; /*! Timer_B interrupt enable. This bit enables the TBIFG interrupt request.
203 * 0 Interrupt disabled
204 * 1 Interrupt enabled */
205 TBIFG_t TBIFG; /*! Timer_B interrupt flag.
206 * 0 No interrupt pending
207 * 1 Interrupt pending */
208 }
209
210
211 struct TBCCTLx_t {
212 CM_t CM; /*! Capture mode
213 * 00 No capture
214 * 01 Capture on rising edge
215 * 10 Capture on falling edge
216 * 11 Capture on both rising and falling edges */
217 CCIS_t CCIS; /*! Capture/compare input select. These bits select the TBCCRx input signal.
218 * See the device-specific data sheet for specific signal connections.
219 * 00 CCIxA
220 * 01 CCIxB
221 * 10 GND
222 * 11 VCC */
223 SCS_t SCS; /*! Synchronize capture source. This bit is used to synchronize the capture input
224 * signal with the timer clock.
225 * 0 Asynchronous capture
226 * 1 Synchronous capture */
227 CLLD_t CLLD; /*! Compare latch load. These bits select the compare latch load event.
228 * 00 TBCLx loads on write to TBCCRx
229 * 01 TBCLx loads when TBR counts to 0
230 * 10 TBCLx loads when TBR counts to 0 (up or continuous mode)
231 * TBCLx loads when TBR counts to TBCL0 or to 0 (up/down mode)
232 * 11 TBCLx loads when TBR counts to TBCLx */
233 CAP_t CAP; /*! Capture mode
234 * 0 Compare mode
235 * 1 Capture mode */
236 OUTMOD_t OUTMOD; /*! Output mode. Modes 2, 3, 6, and 7 are not useful for TBCL0 because EQUx
237 * = EQU0.
238 * 000 OUT bit value
239 * 001 Set
240 * 010 Toggle/reset
241 * 011 Set/reset
242 * 100 Toggle
243 * 101 Reset
244 * 110 Toggle/set
245 * 111 Reset/set */
246 CCIE_t CCIE; /*! Capture/compare interrupt enable. This bit enables the interrupt request of
247 * the corresponding CCIFG flag.
248 * 0 Interrupt disabled
249 * 1 Interrupt enabled */
250 CCI_t CCI; /*! Capture/compare input. The selected input signal can be read by this bit. */
251 OUT_t OUT; /*! Output. For output mode 0, this bit directly controls the state of the output.
252 * 0 Output low
253 * 1 Output high */
254 COV_t COV; /*! Capture overflow. This bit indicates a capture overflow occurred. COV must
255 * be reset with software.
256 * 0 No capture overflow occurred
257 * 1 Capture overflow occurred */
258 CCIFG_t CCIFG; /*! Capture/compare interrupt flag
259 * 0 No interrupt pending
260 * 1 Interrupt pending */
261 }
262
263 instance:
264
265 /*! Timer_B TBCLK */
266 config float TBCLK = 0;
267
268 /*! Timer_B INCLK */
269 config float INCLK = 0;
270 }