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32
33 /*!
34 * ======== Timer_B7 ========
35 * MSP430 Timer_B7 timer
36 */
37 metaonly module Timer_B7 inherits ITimer_B {
38
39 /*! TBIV Definitions */
40 enum IVValues {
41 TBIV_NONE = 0x0000, /*! No Interrupt pending */
42 TBIV_TBCCR1 = 0x0002, /*! TBCCR1_CCIFG */
43 TBIV_TBCCR2 = 0x0004, /*! TBCCR2_CCIFG */
44 TBIV_TBCCR3 = 0x0006, /*! TBCCR3_CCIFG */
45 TBIV_TBCCR4 = 0x0008, /*! TBCCR4_CCIFG */
46 TBIV_TBCCR5 = 0x000A, /*! TBCCR5_CCIFG */
47 TBIV_TBCCR6 = 0x000C, /*! TBCCR6_CCIFG */
48 TBIV_TBIFG = 0x000E /*! TBIFG */
49 };
50
51 instance:
52 /*! TBCTL, Timer_B7 Control Register */
53 config TBCTL_t TBCTL = {
54 TBCLGRP : TBCLGRP_0,
55 CNTL : CNTL_0,
56 TBSSEL : TBSSEL_0,
57 ID : ID_0,
58 MC : MC_0,
59 TBCLR : TBCLR_OFF,
60 TBIE : TBIE_OFF,
61 TBIFG : TBIFG_OFF
62 };
63
64 /*! TBCCTL0, Capture/Compare Control Register 0 */
65 config TBCCTLx_t TBCCTL0 = {
66 CM : CM_0,
67 CCIS : CCIS_0,
68 SCS : SCS_OFF,
69 CLLD : CLLD_0,
70 CAP : CAP_OFF,
71 OUTMOD : OUTMOD_0,
72 CCIE : CCIE_OFF,
73 CCI : CCI_OFF,
74 OUT : OUT_OFF,
75 COV : COV_OFF,
76 CCIFG : CCIFG_OFF
77 };
78
79 /*! TBCCTL1, Capture/Compare Control Register 1 */
80 config TBCCTLx_t TBCCTL1 = {
81 CM : CM_0,
82 CCIS : CCIS_0,
83 SCS : SCS_OFF,
84 CLLD : CLLD_0,
85 CAP : CAP_OFF,
86 OUTMOD : OUTMOD_0,
87 CCIE : CCIE_OFF,
88 CCI : CCI_OFF,
89 OUT : OUT_OFF,
90 COV : COV_OFF,
91 CCIFG : CCIFG_OFF
92 };
93
94 /*! TBCCTL2, Capture/Compare Control Register 2 */
95 config TBCCTLx_t TBCCTL2 = {
96 CM : CM_0,
97 CCIS : CCIS_0,
98 SCS : SCS_OFF,
99 CLLD : CLLD_0,
100 CAP : CAP_OFF,
101 OUTMOD : OUTMOD_0,
102 CCIE : CCIE_OFF,
103 CCI : CCI_OFF,
104 OUT : OUT_OFF,
105 COV : COV_OFF,
106 CCIFG : CCIFG_OFF
107 };
108
109 /*! TBCCTL3, Capture/Compare Control Register 3 */
110 config TBCCTLx_t TBCCTL3 = {
111 CM : CM_0,
112 CCIS : CCIS_0,
113 SCS : SCS_OFF,
114 CLLD : CLLD_0,
115 CAP : CAP_OFF,
116 OUTMOD : OUTMOD_0,
117 CCIE : CCIE_OFF,
118 CCI : CCI_OFF,
119 OUT : OUT_OFF,
120 COV : COV_OFF,
121 CCIFG : CCIFG_OFF
122 };
123
124 /*! TBCCTL4, Capture/Compare Control Register 4 */
125 config TBCCTLx_t TBCCTL4 = {
126 CM : CM_0,
127 CCIS : CCIS_0,
128 SCS : SCS_OFF,
129 CLLD : CLLD_0,
130 CAP : CAP_OFF,
131 OUTMOD : OUTMOD_0,
132 CCIE : CCIE_OFF,
133 CCI : CCI_OFF,
134 OUT : OUT_OFF,
135 COV : COV_OFF,
136 CCIFG : CCIFG_OFF
137 };
138
139 /*! TBCCTL5, Capture/Compare Control Register 5 */
140 config TBCCTLx_t TBCCTL5 = {
141 CM : CM_0,
142 CCIS : CCIS_0,
143 SCS : SCS_OFF,
144 CLLD : CLLD_0,
145 CAP : CAP_OFF,
146 OUTMOD : OUTMOD_0,
147 CCIE : CCIE_OFF,
148 CCI : CCI_OFF,
149 OUT : OUT_OFF,
150 COV : COV_OFF,
151 CCIFG : CCIFG_OFF
152 };
153
154 /*! TBCCTL6, Capture/Compare Control Register 6 */
155 config TBCCTLx_t TBCCTL6 = {
156 CM : CM_0,
157 CCIS : CCIS_0,
158 SCS : SCS_OFF,
159 CLLD : CLLD_0,
160 CAP : CAP_OFF,
161 OUTMOD : OUTMOD_0,
162 CCIE : CCIE_OFF,
163 CCI : CCI_OFF,
164 OUT : OUT_OFF,
165 COV : COV_OFF,
166 CCIFG : CCIFG_OFF
167 };
168
169 /*! TBCCR0, Timer_B Capture/Compare Register 0 */
170 config Bits16 TBCCR0 = 0;
171 /*! TBCCR1, Timer_B Capture/Compare Register 1 */
172 config Bits16 TBCCR1 = 0;
173 /*! TBCCR2, Timer_B Capture/Compare Register 2 */
174 config Bits16 TBCCR2 = 0;
175 /*! TBCCR3, Timer_B Capture/Compare Register 3 */
176 config Bits16 TBCCR3 = 0;
177 /*! TBCCR4, Timer_B Capture/Compare Register 4 */
178 config Bits16 TBCCR4 = 0;
179 /*! TBCCR5, Timer_B Capture/Compare Register 5 */
180 config Bits16 TBCCR5 = 0;
181 /*! TBCCR6, Timer_B Capture/Compare Register 6 */
182 config Bits16 TBCCR6 = 0;
183
184 /*! Timer interrupt enables */
185 config regIntVect_t interruptSource[8];
186
187 /*! Determine if each Register needs to be forced set or not */
188 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
189 [
190 { register : "TBCTL" , regForceSet : false },
191 { register : "TBCCTL0" , regForceSet : false },
192 { register : "TBCCTL1" , regForceSet : false },
193 { register : "TBCCTL2" , regForceSet : false },
194 { register : "TBCCTL3" , regForceSet : false },
195 { register : "TBCCTL4" , regForceSet : false },
196 { register : "TBCCTL5" , regForceSet : false },
197 { register : "TBCCTL6" , regForceSet : false },
198 { register : "TBCCR0" , regForceSet : false },
199 { register : "TBCCR1" , regForceSet : false },
200 { register : "TBCCR2" , regForceSet : false },
201 { register : "TBCCR3" , regForceSet : false },
202 { register : "TBCCR4" , regForceSet : false },
203 { register : "TBCCR5" , regForceSet : false },
204 { register : "TBCCR6" , regForceSet : false }
205 ];
206 }