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32
33 34 35 36
37 package ti.catalog.c6000;
38
39 /*!
40 * ======== TNETV107X ========
41 */
42 metaonly module TNETV107X inherits ti.catalog.ICpuDataSheet
43 {
44
45 config long cacheSizeL1[string] = [
46 ["0k", 0x0000],
47 ["4k", 0x1000],
48 ["8k", 0x2000],
49 ["16k", 0x4000],
50 ["32k", 0x8000],
51 ];
52
53 config long cacheSizeL2[string] = [
54 ["0k", 0x00000],
55 ["32k", 0x08000],
56 ["64k", 0x10000],
57 ["128k", 0x20000]
58 ];
59
60 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
61 ['l1PMode',
62 {desc: "L1P Cache",
63 base: 0x11E08000,
64 map: [["0k", 0x0000],
65 ["4k", 0x1000],
66 ["8k", 0x2000],
67 ["16k", 0x4000],
68 ["32k", 0x8000]],
69 defaultValue: "32k",
70 memorySection: "L1PSRAM"}
71 ],
72
73 ['l1DMode',
74 {desc: "L1D Cache",
75 base: 0x11F04000,
76 map: [["0k", 0x0000],
77 ["4k", 0x1000],
78 ["8k", 0x2000],
79 ["16k", 0x4000],
80 ["32k", 0x8000]],
81 defaultValue: "32k",
82 memorySection: "L1DSRAM"}
83 ],
84
85 ['l2Mode',
86 {desc: "L2 Cache",
87 base: 0x11800000,
88 map: [["0k", 0x0000],
89 ["32k", 0x8000],
90 ["64k", 0x10000],
91 ["128k", 0x20000]],
92 defaultValue: "0k",
93 memorySection: "L2RAM"}
94 ],
95
96 ];
97
98 instance:
99 override config int minProgUnitSize = 1;
100 override config int minDataUnitSize = 1;
101 override config int dataWordSize = 4;
102
103 override config string cpuCore = "64x+";
104 override config string isa = "64P";
105
106 config xdc.platform.IPlatform.Memory memMap[string] = [
107 ["L2RAM", {
108 comment: "Internal 128KB L2 memory",
109 name: "L2RAM",
110 base: 0x11800000,
111 len: 0x00020000,
112 space: "code/data",
113 access: "RWX"
114 }],
115
116 ["L1PSRAM", {
117 comment: "Internal 32KB L1 program memory",
118 name: "L1PSRAM",
119 base: 0x11E08000,
120 len: 0x00008000,
121 space: "code",
122 access: "RWX"
123 }],
124
125 ["L1DSRAM", {
126 comment: "Internal 80KB L1 data memory",
127 name: "L1DSRAM",
128 base: 0x11F04000,
129 len: 0x00014000,
130 space: "data",
131 access: "RW"
132 }],
133 ];
134 };