1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*!
    34     * Universal Serial Communication Interface
    35     */
    36    metaonly interface IUSCI_SPI inherits IUSCI {
    37    
    38        //*****************************************************************
    39        //* REGISTER BIT DEFINITIONS                                      *
    40        //*****************************************************************
    41    
    42        /*! Clock phase select. */
    43        enum UCCKPH_t {
    44            UCCKPH_OFF = 0x00,      /*! Data is changed on the first UCLK edge and captured on the following edge. */
    45            UCCKPH = 0x80           /*! Data is captured on the first UCLK edge and changed on the following edge. */
    46        };
    47    
    48        /*! Clock polarity select. */
    49        enum UCCKPL_t {
    50            UCCKPL_OFF = 0x00,      /*! Inactive state is low */
    51            UCCKPL = 0x40           /*! Inactive state is high */
    52        };
    53    
    54        /*! Master mode select */
    55        enum UCMST_t {
    56            UCMST_OFF = 0x00,       /*! Slave mode */
    57            UCMST = 0x40            /*! Master mode */
    58        };
    59    
    60        /*! USCI clock source select. These bits select the BRCLK source clock. */
    61        enum UCSSEL_SPI_t {
    62            UCSSEL_0 = 0x00,        /*! NA */
    63            UCSSEL_1 = 0x01,        /*! ACLK */
    64            UCSSEL_2 = 0x02         /*! SMCLK */
    65    /*        UCSSEL_3 = 0x04      /*! SMCLK */
    66        };
    67    
    68        struct UCxCTL0_t {
    69            UCCKPH_t    UCCKPH;     /*! Clock phase select.
    70                                     *  0  Data is changed on the first UCLK edge and captured on the
    71                                     *     following edge.
    72                                     *  1  Data is captured on the first UCLK edge and changed on the
    73                                     *     following edge. */
    74            UCCKPL_t    UCCKPL;     /*! Clock polarity select
    75                                     *  0  The inactive state is low
    76                                     *  1  The inactive state is high */
    77            UCMSB_t     UCMSB;      /*! MSB first select. Controls the direction of the receive and transmit shift
    78                                     *register.
    79                                     *  0  LSB first
    80                                     *  1  MSB first */
    81            UC7BIT_t    UC7BIT;     /*! Character length. Selects 7-bit or 8-bit character length.
    82                                     *  0  8-bit data
    83                                     *  1  7-bit data */
    84            UCMST_t     UCMST;      /*! Master mode select
    85                                     *  0  Slave mode
    86                                     *  1  Master mode */
    87            UCMODE_SYNC_t UCMODE;   /*! USCI mode. The UCMODEx bits select the synchronous mode when
    88                                     *UCSYNC = 1.
    89                                     *  00  3-Pin SPI
    90                                     *  01  4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
    91                                     *  10  4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
    92                                     *  11  I2C Mode */
    93            UCSYNC_t    UCSYNC;     /*! Synchronous mode enable
    94                                     *  0  Asynchronous mode
    95                                     *  1  Synchronous Mode */
    96        }
    97    
    98        struct UCxCTL1_t {
    99            UCSSEL_SPI_t UCSSEL;    /*! USCI clock source select. These bits select the BRCLK source clock in
   100                                     *master mode. UCxCLK is always used in slave mode.
   101                                     *  00  NA
   102                                     *  01  ACLK
   103                                     *  10  SMCLK
   104                                     *  11  SMCLK */
   105            UCSWRST_t    UCSWRST;   /*! Software reset enable
   106                                     *  0  Disabled. USCI reset released for operation.
   107                                     *  1  Enabled. USCI logic held in reset state. */
   108        }
   109    
   110        struct UCxSTAT_t {
   111            UCLISTEN_t  UCLISTEN;   /*! Listen enable. The UCLISTEN bit selects loopback mode.
   112                                     *  0  Disabled
   113                                     *  1  Enabled. UCAxTXD is internally fed back to the receiver. */
   114            UCFE_t      UCFE;       /*! Framing error flag. This bit indicates a bus conflict in 4-wire master mode.
   115                                     *UCFE is not used in 3-wire master or any slave mode.
   116                                     *  0  No error
   117                                     *  1  Bus conflict occurred */
   118            UCOE_t      UCOE;       /*! Overrun error flag. This bit is set when a character is transferred into
   119                                     *UCAxRXBUF before the previous character was read. UCOE is cleared
   120                                     *automatically when UCxRXBUF is read, and must not be cleared by
   121                                     *software. Otherwise, it will not function correctly.
   122                                     *  0  No error
   123                                     *  1  Overrun error occurred */
   124            UCBUSY_t    UCBUSY;     /*! USCI busy. This bit indicates if a transmit or receive operation is in
   125                                     *progress.
   126                                     *  0  USCI inactive
   127                                     *  1  USCI transmitting or receiving */
   128        }
   129    }