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32
33
34 /*!
35 * ======== IDAC ========
36 * MSP430 Digital to Analog Converter Interface
37 */
38 metaonly interface IDAC inherits xdc.platform.IPeripheral {
39
40
41 /*! DAC12OPS Bit */
42 enum DAC12OPS_t {
43 DAC12OPS_OFF = 0x0000,
44 DAC12OPS = 0x8000
45 };
46
47 /*! DAC12SREFx Bits */
48 enum DAC12SREF_t {
49 DAC12SREF_0 = (0*0x2000u),
50 DAC12SREF_1 = (1*0x2000u),
51 DAC12SREF_2 = (2*0x2000u),
52 DAC12SREF_3 = (3*0x2000u)
53 };
54
55 /*! DAC12RES Bit */
56 enum DAC12RES_t {
57 DAC12RES_OFF = 0x0000,
58 DAC12RES = 0x1000
59 };
60
61 /*! DAC12LSELx Bits */
62 enum DAC12LSEL_t {
63 DAC12LSEL_0 = (0*0x0400u),
64 DAC12LSEL_1 = (1*0x0400u),
65 DAC12LSEL_2 = (2*0x0400u),
66 DAC12LSEL_3 = (3*0x0400u)
67 };
68
69 /*! DAC12CALON Bit */
70 enum DAC12CALON_t {
71 DAC12CALON_OFF = 0x0000,
72 DAC12CALON = 0x0200
73 };
74
75 /*! DAC12IR Bit */
76 enum DAC12IR_t {
77 DAC12IR_OFF = 0x0000,
78 DAC12IR = 0x0100
79 };
80
81 /*! DAC12AMPx Bits */
82 enum DAC12AMP_t {
83 DAC12AMP_0 = (0*0x0020u),
84 DAC12AMP_1 = (1*0x0020u),
85 DAC12AMP_2 = (2*0x0020u),
86 DAC12AMP_3 = (3*0x0020u),
87 DAC12AMP_4 = (4*0x0020u),
88 DAC12AMP_5 = (5*0x0020u),
89 DAC12AMP_6 = (6*0x0020u),
90 DAC12AMP_7 = (7*0x0020u)
91 };
92
93 /*! DAC12DF Bit */
94 enum DAC12DF_t {
95 DAC12DF_OFF = 0x0000,
96 DAC12DF = 0x0010
97 };
98
99 /*! DAC12IE Bit */
100 enum DAC12IE_t {
101 DAC12IE_OFF = 0x0000,
102 DAC12IE = 0x0008
103 };
104
105 /*! DAC12IFG Bit */
106 enum DAC12IFG_t {
107 DAC12IFG_OFF = 0x0000,
108 DAC12IFG = 0x0004
109 };
110
111 /*! DAC12ENC Bit */
112 enum DAC12ENC_t {
113 DAC12ENC_OFF = 0x0000,
114 DAC12ENC = 0x0002
115 };
116
117 /*! DAC12GRP Bit */
118 enum DAC12GRP_t {
119 DAC12GRP_OFF = 0x0000,
120 DAC12GRP = 0x0001
121 };
122
123 /*!
124 * ======== ForceSetDefaultRegister_t ========
125 * Force Set Default Register
126 *
127 * Type to store if each register needs to be forced initialized
128 * even if the register is in default state.
129 *
130 * @see #ForceSetDefaultRegister_t
131 */
132 struct ForceSetDefaultRegister_t {
133 String register;
134 Bool regForceSet;
135 }
136
137 /*!
138 * ======== regIntVect_t ========
139 * Interrupt vector description
140 *
141 * Type to describe a single interrupt vector pin and all its possible
142 * configurations.
143 *
144 * @see #regIntVect_t
145 */
146 struct regIntVect_t {
147 String registerName;
148 String registerDescription;
149 String isrToggleString;
150 String priorityName;
151 Bool interruptEnable;
152 Bool interruptHandler;
153 Int priority;
154 }
155 instance:
156
157 }