1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*!
    34     *  ======== Comparator_D ========
    35     *  MSP430FR5xx Family Comparator_D Module
    36     */
    37    metaonly module Comparator_D inherits IComparator {
    38    
    39        enum CDIE_t{
    40            CDIE_OFF    = 0x0000,       /*! Interrupt not enabled */
    41            CDIE        = 0x0100        /*! Interrupt enabled */
    42        };
    43    
    44        enum CDIIE_t{
    45            CDIIE_OFF   = 0x0000,       /*! Interrupt not enabled inverted polarity*/
    46            CDIIE       = 0x0200        /*! Interrupt enabled inverted polarity */
    47        };
    48    
    49        enum CDIFG_t{
    50            CDIFG_OFF   = 0x00,         /*! No interrupt pending */
    51            CDIFG       = 0x01          /*! Interrupt pending */
    52        };
    53    
    54        enum CDIIFG_t{
    55            CDIIFG_OFF  = 0x00,         /*! No inverted interrupt pending */
    56            CDIIFG      = 0x02          /*! Inverted interrupt pending */
    57        };
    58    
    59        struct CDIEALL_t {
    60            CDIE_t      CDIE;          /*!  Comparator D interrupt enable. This
    61                                        *   bit enables the CDIFG interrupt for
    62                                        *   comparator mode.
    63                                        *   0  Interrupt disabled
    64                                        *   1  Interrupt enabled */
    65    
    66            CDIIE_t      CDIIE;         /*! Comparator D interrupt enable inverted polarity. This
    67                                        *   bit enables the CDIIFG interrupt for
    68                                        *   comparator mode.
    69                                        *   0  Interrupt disabled
    70                                        *   1  Interrupt enabled */
    71        }
    72    
    73        struct CDIFGALL_t {
    74            CDIFG_t      CDIFG;         /*! Comparator D interrupt flag.
    75                                         *  0  No interrupt pending
    76                                         *  1  Interrupt pending */
    77    
    78            CDIIFG_t     CDIIFG;         /*! Comparator D interrupt flag.
    79                                         *  0  No inverted interrupt pending
    80                                         *  1  Inverted interrupt pending */
    81        }
    82    instance:
    83        /*!
    84         *  ======== baseAddr ========
    85         *  Address of the peripheral's control register.
    86         *
    87         *  A peripheral's registers are commonly accessed through a structure
    88         *  that defines the offsets of a particular register from the lowest
    89         *  address mapped to a peripheral. That lowest address is specified by
    90         *  this parameter.
    91         */
    92        config UInt baseAddr;
    93    
    94         /*!
    95         *  ======== interruptSource ========
    96         *  Comparator_D has own interrupt enables
    97         *  thus interruptSource is defined here
    98         */
    99        config regIntVect_t interruptSource[2];
   100    
   101        /*!
   102         *  ======== CDIEALL ========
   103         * All the Interrupt Enables in Comparator_D
   104         */
   105        config CDIEALL_t CDIEALL = {
   106            CDIE        : CDIE_OFF,
   107            CDIIE       : CDIIE_OFF
   108        };
   109    
   110        /*!
   111         *  ======== CDIFGALL ========
   112         * All the Interrupt Flags in Comparator_D
   113         */
   114        config CDIFGALL_t CDIFGALL = {
   115            CDIFG       : CDIFG_OFF,
   116            CDIIFG      : CDIIFG_OFF
   117        };
   118    
   119        /*!
   120        *   ======== forceSetDefaultRegister ========
   121        * Determine if each Register needs to be forced set or not
   122        */
   123        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   124        [
   125            { register : "CDIEALL" , regForceSet : false },
   126            { register : "CDIFGALL" , regForceSet : false },
   127        ];
   128    }