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32
33 /*!
34 * ======== IFlash ========
35 * MSP430 IFlash interface
36 */
37 metaonly interface IFlash inherits xdc.platform.IPeripheral {
38
39 enum FWKEY_t {
40 FWKEY_OFF = 0x00,
41 FWKEY = 0xA500
42 };
43
44 /*! Block write mode */
45 enum BLKWRT_t {
46 BLKWRT_OFF = (0x0000), /*! Block-write mode is off */
47 BLKWRT = 0x0080 /*! Block-write mode is on */
48 };
49
50 /*! Write */
51 enum WRT_t {
52 WRT_OFF = (0x0000), /*! Write mode is off */
53 WRT = 0x0040 /*! Write mode is on */
54 };
55
56 /*! Enable Emergency Interrupt Exit */
57 enum EEIEX_t {
58 EEIEX_OFF = (0x0000), /*! Exit interrupt disabled */
59 EEIEX = 0x0010 /*! Exit interrupt enabled */
60 };
61
62 /*! Enable Erase Interrupts */
63 enum EEI_t {
64 EEI_OFF = (0x0000), /*! Interrupts during segment erase disabled */
65 EEI = 0x0008 /*! Interrupts during segment erase enabled */
66 };
67
68 /*! Mass erase */
69 enum MERAS_t {
70 MERAS_OFF = (0x0000), /*! Mass erase disabled */
71 MERAS = 0x0004 /*! Mass erase enabled */
72 };
73
74 /*! Erase */
75 enum ERASE_t {
76 ERASE_OFF = (0x0000), /*! Erase disabled */
77 ERASE = 0x0002 /*! Erase enabled */
78 };
79
80 enum FSSEL_t {
81 FSSEL_0 = 0x0000, /*! ACLK */
82 FSSEL_1 = 0x0040, /*! MCLK */
83 FSSEL_2 = 0x0080 /*! SMCLK */
84 };
85
86 /*! Flash controller clock divider bit 0 */
87 enum FN0_t {
88 FN0_OFF = (0x0000), /*! Flash controller clock divider bit 0 */
89 FN0 = 0x0001 /*! Flash controller clock divider bit 0 */
90 };
91
92 /*! Flash controller clock divider bit 1 */
93 enum FN1_t {
94 FN1_OFF = (0x0000), /*! Flash controller clock divider bit 1 */
95 FN1 = 0x0002 /*! Flash controller clock divider bit 1 */
96 };
97
98 /*! Flash controller clock divider bit 2 */
99 enum FN2_t {
100 FN2_OFF = (0x0000), /*! Flash controller clock divider bit 2 */
101 FN2 = 0x0004 /*! Flash controller clock divider bit 2 */
102 };
103
104 /*! Flash controller clock divider bit 3 */
105 enum FN3_t {
106 FN3_OFF = (0x0000), /*! Flash controller clock divider bit 3 */
107 FN3 = 0x0008 /*! Flash controller clock divider bit 3 */
108 };
109
110 /*! Flash controller clock divider bit 4 */
111 enum FN4_t {
112 FN4_OFF = (0x0000), /*! Flash controller clock divider bit 4 */
113 FN4 = 0x0010 /*! Flash controller clock divider bit 4 */
114 };
115
116 /*! Flash controller clock divider bit 5 */
117 enum FN5_t {
118 FN5_OFF = (0x0000), /*! Flash controller clock divider bit 5 */
119 FN5 = 0x0020 /*! Flash controller clock divider bit 5 */
120 };
121
122 /*! Operation failure */
123 enum FAIL_t {
124 FAIL_OFF = (0x0000), /*! No failure */
125 FAIL = 0x0080 /*! Failure */
126 };
127
128 /*! SegmentA and Info lock */
129 enum LOCKA_t {
130 LOCKA_OFF = (0x0000), /*! Segment A unlocked and all information memory is erased during a mass erase */
131 LOCKA = 0x0040 /*! Segment A locked and all information memory is protected from erasure during a mass erase */
132 };
133
134 /*! Emergency exit */
135 enum EMEX_t {
136 EMEX_OFF = (0x0000), /*! No emergency exit */
137 EMEX = 0x0020 /*! Emergency exit */
138 };
139
140 /*! Lock */
141 enum LOCK_t {
142 LOCK_OFF = (0x0000), /*! Unlocked */
143 LOCK = 0x0010 /*! Locked */
144 };
145
146 /*! Wait */
147 enum WAIT_t {
148 WAIT_OFF = (0x0000), /*! The flash memory is not ready for the next byte/word write */
149 WAIT = 0x0008 /*! The flash memory is ready for the next byte/word write */
150 };
151
152 /*! Access violation interrupt flag */
153 enum ACCVIFG_t {
154 ACCVIFG_OFF = (0x0000), /*! No interrupt pending */
155 ACCVIFG = 0x0004 /*! Interrupt pending */
156 };
157
158 /*! Flash security key violation */
159 enum KEYV_t {
160 KEYV_OFF = (0x0000), /*! FCTLx password was written correctly */
161 KEYV = 0x0002 /*! FCTLx password was written incorrectly */
162 };
163
164 /*! Busy */
165 enum BUSY_t {
166 BUSY_OFF = (0x0000), /*! Not Busy */
167 BUSY = 0x0001 /*! Busy */
168 };
169
170 /*!
171 * ======== ForceSetDefaultRegister_t ========
172 * Force Set Default Register
173 *
174 * Type to store if each register needs to be forced initialized
175 * even if the register is in default state.
176 *
177 * @see #ForceSetDefaultRegister_t
178 */
179 struct ForceSetDefaultRegister_t {
180 String register;
181 Bool regForceSet;
182 }
183
184
185 instance:
186 /*! Max Flash Timing Generator Value from Datasheet */
187 config UInt8 uMaxFtg;
188
189 /*! Min Flash Timing Generator Value from Datasheet */
190 config UInt8 uMinFtg;
191
192 }