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32
33 /*!
34 * ======== Timer0_B3 ========
35 * MSP430 Timer0_B3 timer
36 */
37 metaonly module Timer0_B3 inherits ITimer_B {
38
39 instance:
40 /*! TB0CTL, Timer_B3 Control Register */
41 config TBCTL_t TB0CTL = {
42 TBCLGRP : TBCLGRP_0,
43 CNTL : CNTL_0,
44 TBSSEL : TBSSEL_0,
45 ID : ID_0,
46 MC : MC_0,
47 TBCLR : TBCLR_OFF,
48 TBIE : TBIE_OFF,
49 TBIFG : TBIFG_OFF
50 };
51
52
53 /*! TB0CCTL0, Capture/Compare Control Register 0 */
54 config TBCCTLx_t TB0CCTL0 = {
55 CM : CM_0,
56 CCIS : CCIS_0,
57 SCS : SCS_OFF,
58 CLLD : CLLD_0,
59 CAP : CAP_OFF,
60 OUTMOD : OUTMOD_0,
61 CCIE : CCIE_OFF,
62 CCI : CCI_OFF,
63 OUT : OUT_OFF,
64 COV : COV_OFF,
65 CCIFG : CCIFG_OFF
66 };
67
68 /*! TB0CCTL1, Capture/Compare Control Register 1 */
69 config TBCCTLx_t TB0CCTL1 = {
70 CM : CM_0,
71 CCIS : CCIS_0,
72 SCS : SCS_OFF,
73 CLLD : CLLD_0,
74 CAP : CAP_OFF,
75 OUTMOD : OUTMOD_0,
76 CCIE : CCIE_OFF,
77 CCI : CCI_OFF,
78 OUT : OUT_OFF,
79 COV : COV_OFF,
80 CCIFG : CCIFG_OFF
81 };
82
83 /*! TB0CCTL2, Capture/Compare Control Register 2 */
84 config TBCCTLx_t TB0CCTL2 = {
85 CM : CM_0,
86 CCIS : CCIS_0,
87 SCS : SCS_OFF,
88 CLLD : CLLD_0,
89 CAP : CAP_OFF,
90 OUTMOD : OUTMOD_0,
91 CCIE : CCIE_OFF,
92 CCI : CCI_OFF,
93 OUT : OUT_OFF,
94 COV : COV_OFF,
95 CCIFG : CCIFG_OFF
96 };
97
98 /*! TB0CCR0, Timer_B Capture/Compare Register 0 */
99 config Bits16 TB0CCR0 = 0;
100 /*! TB0CCR1, Timer_B Capture/Compare Register 1 */
101 config Bits16 TB0CCR1 = 0;
102 /*! TB0CCR2, Timer_B Capture/Compare Register 2 */
103 config Bits16 TB0CCR2 = 0;
104
105 /*! Timer interrupt enables */
106 config regIntVect_t interruptSource[4];
107
108 /*! Determine if each Register needs to be forced set or not */
109 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
110 [
111 { register : "TB0CTL" , regForceSet : false },
112 { register : "TB0CCTL0" , regForceSet : false },
113 { register : "TB0CCTL1" , regForceSet : false },
114 { register : "TB0CCTL2" , regForceSet : false },
115 { register : "TB0CCR0" , regForceSet : false },
116 { register : "TB0CCR1" , regForceSet : false },
117 { register : "TB0CCR2" , regForceSet : false }
118 ];
119 }