1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*!
    34     *  ======== Timer3_A5 ========
    35     *  MSP430 Timer3_A5 timer
    36     */
    37    metaonly module Timer3_A5 inherits ITimer_A {
    38    
    39    instance:
    40        /*! TA3CTL, Timer3_A5 Control Register */
    41        config TACTL_t TA3CTL = {
    42            TASSEL : TASSEL_0,
    43            ID : ID_0,
    44            MC : MC_0,
    45            TACLR : TACLR_OFF,
    46            TAIE : TAIE_OFF,
    47            TAIFG : TAIFG_OFF
    48        };
    49    
    50        /*! TA3CCTL0, Capture/Compare Control Register 0 */
    51        config TACCTLx_t TA3CCTL0 = {
    52            CM : CM_0,
    53            CCIS : CCIS_0,
    54            SCS : SCS_OFF,
    55            SCCI : SCCI_OFF,
    56            CAP : CAP_OFF,
    57            OUTMOD : OUTMOD_0,
    58            CCIE : CCIE_OFF,
    59            CCI : CCI_OFF,
    60            OUT : OUT_OFF,
    61            COV : COV_OFF,
    62            CCIFG : CCIFG_OFF
    63        };
    64    
    65        /*! TA3CCTL1, Capture/Compare Control Register 1 */
    66        config TACCTLx_t TA3CCTL1 = {
    67            CM : CM_0,
    68            CCIS : CCIS_0,
    69            SCS : SCS_OFF,
    70            SCCI : SCCI_OFF,
    71            CAP : CAP_OFF,
    72            OUTMOD : OUTMOD_0,
    73            CCIE : CCIE_OFF,
    74            CCI : CCI_OFF,
    75            OUT : OUT_OFF,
    76            COV : COV_OFF,
    77            CCIFG : CCIFG_OFF
    78        };
    79    
    80        /*! TA3CCTL2, Capture/Compare Control Register 2 */
    81        config TACCTLx_t TA3CCTL2 = {
    82            CM : CM_0,
    83            CCIS : CCIS_0,
    84            SCS : SCS_OFF,
    85            SCCI : SCCI_OFF,
    86            CAP : CAP_OFF,
    87            OUTMOD : OUTMOD_0,
    88            CCIE : CCIE_OFF,
    89            CCI : CCI_OFF,
    90            OUT : OUT_OFF,
    91            COV : COV_OFF,
    92            CCIFG : CCIFG_OFF
    93        };
    94    
    95        /*! TA3CCTL3, Capture/Compare Control Register 3 */
    96        config TACCTLx_t TA3CCTL3 = {
    97            CM : CM_0,
    98            CCIS : CCIS_0,
    99            SCS : SCS_OFF,
   100            SCCI : SCCI_OFF,
   101            CAP : CAP_OFF,
   102            OUTMOD : OUTMOD_0,
   103            CCIE : CCIE_OFF,
   104            CCI : CCI_OFF,
   105            OUT : OUT_OFF,
   106            COV : COV_OFF,
   107            CCIFG : CCIFG_OFF
   108        };
   109    
   110        /*! TA3CCTL4, Capture/Compare Control Register 4 */
   111        config TACCTLx_t TA3CCTL4 = {
   112            CM : CM_0,
   113            CCIS : CCIS_0,
   114            SCS : SCS_OFF,
   115            SCCI : SCCI_OFF,
   116            CAP : CAP_OFF,
   117            OUTMOD : OUTMOD_0,
   118            CCIE : CCIE_OFF,
   119            CCI : CCI_OFF,
   120            OUT : OUT_OFF,
   121            COV : COV_OFF,
   122            CCIFG : CCIFG_OFF
   123        };
   124    
   125        /*! TA3CCR0, Timer_A Capture/Compare Register 0 */
   126        config Bits16 TA3CCR0 = 0;
   127        /*! TA3CCR1, Timer_A Capture/Compare Register 1 */
   128        config Bits16 TA3CCR1 = 0;
   129        /*! TA3CCR2, Timer_A Capture/Compare Register 2 */
   130        config Bits16 TA3CCR2 = 0;
   131        /*! TA3CCR3, Timer_A Capture/Compare Register 3 */
   132        config Bits16 TA3CCR3 = 0;
   133        /*! TA3CCR4, Timer_A Capture/Compare Register 4 */
   134        config Bits16 TA3CCR4 = 0;
   135    
   136        /*! Timer interrupt enables */
   137        config regIntVect_t interruptSource[6];
   138    
   139        /*! Determine if each Register needs to be forced set or not */
   140        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   141        [
   142            { register : "TA3CTL"   , regForceSet : false },
   143            { register : "TA3CCTL0" , regForceSet : false },
   144            { register : "TA3CCTL1" , regForceSet : false },
   145            { register : "TA3CCR0"  , regForceSet : false },
   146            { register : "TA3CCR1"  , regForceSet : false },
   147            { register : "TA3CCR2"  , regForceSet : false },
   148            { register : "TA3CCR3"  , regForceSet : false },
   149            { register : "TA3CCR4"  , regForceSet : false }
   150        ];
   151    }