1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    import ti.catalog.msp430.peripherals.clock.IClock;
    34    
    35    /*!
    36     * Universal Serial Communication Interface
    37     */
    38    metaonly module USCI_A1_UART_2xx inherits IUSCI_A1_UART {
    39        /* Add 2xx-specific stuff here */
    40    
    41        /*
    42         *  ======== create ========
    43         */
    44        create(IClock.Instance clock);
    45    
    46        /*! USCI_A1 transmit interrupt enable */
    47        enum UCA1TXIE_t {
    48            UCA1TXIE_OFF = 0x00,    /*! Interrupt disabled */
    49            UCA1TXIE = 0x02         /*! Interrupt enabled */
    50        };
    51    
    52        /*! USCI_A1 receive interrupt enable */
    53        enum UCA1RXIE_t {
    54            UCA1RXIE_OFF = 0x00,     /*! Interrupt disabled */
    55            UCA1RXIE = 0x01          /*! Interrupt enabled */
    56        };
    57    
    58        /*! USCI_Ax UART Interrupt Enable Register */
    59        struct UC1IE_t {
    60            UCA1TXIE_t  UCA1TXIE;   /*! USCI_A1 transmit interrupt enable
    61                                     *  0  Interrupt disabled
    62                                     *  1  Interrupt enabled */
    63            UCA1RXIE_t  UCA1RXIE;   /*! USCI_A1 receive interrupt enable
    64                                     *  0  Interrupt disabled
    65                                     *  1  Interrupt enabled */
    66        }
    67    
    68    instance:
    69        /*! @_nodoc */
    70        config IClock.Instance clock;
    71    
    72        /*! USCI_A1 Interrupt Enable Register */
    73        config UC1IE_t UC1IE = {
    74            UCA1TXIE    : UCA1TXIE_OFF,
    75            UCA1RXIE    : UCA1RXIE_OFF
    76        };
    77    
    78        /*! USCI_A1 UART interrupt enables */
    79        config regIntVect_t interruptSource[2];
    80    
    81        /*! Determine if each Register needs to be forced set or not */
    82        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
    83        [
    84            { register : "UCA1CTL0"   , regForceSet : false },
    85            { register : "UCA1CTL1"   , regForceSet : false },
    86            { register : "UCA1BR0"    , regForceSet : false },
    87            { register : "UCA1BR1"    , regForceSet : false },
    88            { register : "UCA1MCTL"   , regForceSet : false },
    89            { register : "UCA1STAT"   , regForceSet : false },
    90            { register : "UCA1RXBUF"  , regForceSet : false },
    91            { register : "UCA1TXBUF"  , regForceSet : false },
    92            { register : "UCA1ABCTL"  , regForceSet : false },
    93            { register : "UCA1IRTCTL" , regForceSet : false },
    94            { register : "UCA1IRRCTL" , regForceSet : false },
    95            { register : "UC1IE"      , regForceSet : false }
    96        ];
    97    }