1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*!
    34     *  ======== Timer1_A3 ========
    35     *  MSP430 Timer1_A3 timer
    36     */
    37    metaonly module Timer1_A3 inherits ITimer_A {
    38    
    39    instance:
    40        /*! TA1CTL, Timer_A3 Control Register */
    41        config TACTL_t TA1CTL = {
    42            TASSEL : TASSEL_0,
    43            ID : ID_0,
    44            MC : MC_0,
    45            TACLR : TACLR_OFF,
    46            TAIE : TAIE_OFF,
    47            TAIFG : TAIFG_OFF
    48        };
    49    
    50        /*! TA1CCTL0, Capture/Compare Control Register 0 */
    51        config TACCTLx_t TA1CCTL0 = {
    52            CM : CM_0,
    53            CCIS : CCIS_0,
    54            SCS : SCS_OFF,
    55            SCCI : SCCI_OFF,
    56            CAP : CAP_OFF,
    57            OUTMOD : OUTMOD_0,
    58            CCIE : CCIE_OFF,
    59            CCI : CCI_OFF,
    60            OUT : OUT_OFF,
    61            COV : COV_OFF,
    62            CCIFG : CCIFG_OFF
    63        };
    64    
    65        /*! TA1CCTL1, Capture/Compare Control Register 1 */
    66        config TACCTLx_t TA1CCTL1 = {
    67            CM : CM_0,
    68            CCIS : CCIS_0,
    69            SCS : SCS_OFF,
    70            SCCI : SCCI_OFF,
    71            CAP : CAP_OFF,
    72            OUTMOD : OUTMOD_0,
    73            CCIE : CCIE_OFF,
    74            CCI : CCI_OFF,
    75            OUT : OUT_OFF,
    76            COV : COV_OFF,
    77            CCIFG : CCIFG_OFF
    78        };
    79    
    80        /*! TA1CCTL2, Capture/Compare Control Register 2 */
    81        config TACCTLx_t TA1CCTL2 = {
    82            CM : CM_0,
    83            CCIS : CCIS_0,
    84            SCS : SCS_OFF,
    85            SCCI : SCCI_OFF,
    86            CAP : CAP_OFF,
    87            OUTMOD : OUTMOD_0,
    88            CCIE : CCIE_OFF,
    89            CCI : CCI_OFF,
    90            OUT : OUT_OFF,
    91            COV : COV_OFF,
    92            CCIFG : CCIFG_OFF
    93        };
    94    
    95        /*! TA1CCR0, Timer_A Capture/Compare Register 0 */
    96        config Bits16 TA1CCR0 = 0;
    97        /*! TA1CCR1, Timer_A Capture/Compare Register 1 */
    98        config Bits16 TA1CCR1 = 0;
    99        /*! TA1CCR2, Timer_A Capture/Compare Register 2 */
   100        config Bits16 TA1CCR2 = 0;
   101    
   102        /*! Timer interrupt enables */
   103        config regIntVect_t interruptSource[4];
   104    
   105        /*! Determine if each Register needs to be forced set or not */
   106        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   107        [
   108            { register : "TA1CTL"   , regForceSet : false },
   109            { register : "TA1CCTL0" , regForceSet : false },
   110            { register : "TA1CCTL1" , regForceSet : false },
   111            { register : "TA1CCTL2" , regForceSet : false },
   112            { register : "TA1CCR0"  , regForceSet : false },
   113            { register : "TA1CCR1"  , regForceSet : false },
   114            { register : "TA1CCR2"  , regForceSet : false }
   115        ];
   116    }