1 /* 2 * Copyright (c) 2016, Texas Instruments Incorporated 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 34 /*! 35 * ======== ISVS ======== 36 * MSP430 ISVS interface 37 */ 38 metaonly interface ISVS inherits xdc.platform.IPeripheral { 39 40 /*! VLD3 Bit */ 41 enum VLD3_t { 42 VLD3_OFF = 0x00, 43 VLD3 = 0x80 44 }; 45 /*! VLD2 Bit */ 46 enum VLD2_t { 47 VLD2_OFF = 0x00, 48 VLD2 = 0x40 49 }; 50 /*! VLD1 Bit */ 51 enum VLD1_t { 52 VLD1_OFF = 0x00, 53 VLD1 = 0x20 54 }; 55 /*! VLD0 Bit */ 56 enum VLD0_t { 57 VLD0_OFF = 0x00, 58 VLD0 = 0x10 59 }; 60 /*! PORON Bit */ 61 enum PORON_t { 62 PORON_OFF = 0x00, /*! SVSFG does not cause a POR */ 63 PORON = 0x08 /*! SVSFG causes a POR */ 64 }; 65 /*! SVSON Bit */ 66 enum SVSON_t { 67 SVSON_OFF = 0x00, 68 SVSON = 0x04 69 }; 70 /*! SVSOP Bit */ 71 enum SVSOP_t { 72 SVSOP_OFF = 0x00, 73 SVSOP = 0x02 74 }; 75 /*! SVSFG Bit */ 76 enum SVSFG_t { 77 SVSFG_OFF = 0x00, 78 SVSFG = 0x01 79 }; 80 81 /*! 82 * ======== ForceSetDefaultRegister_t ======== 83 * Force Set Default Register 84 * 85 * Type to store if each register needs to be forced initialized 86 * even if the register is in default state. 87 * 88 * @see #ForceSetDefaultRegister_t 89 */ 90 struct ForceSetDefaultRegister_t { 91 String register; 92 Bool regForceSet; 93 } 94 95 instance: 96 97 }