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32
33 /*!
34 * ======== IE2 ========
35 * MSP430 Interrupt Enable Register 2
36 */
37 metaonly module IE2 inherits xdc.platform.IPeripheral {
38
39
40 enum UCB0TXIE_t {
41 UCB0TXIE_OFF = 0x00, /*! Interrupt disabled */
42 UCB0TXIE = 0x08 /*! Interrupt enabled */
43 };
44
45
46 enum UCB0RXIE_t {
47 UCB0RXIE_OFF = 0x00, /*! Interrupt disabled */
48 UCB0RXIE = 0x04 /*! Interrupt enabled */
49 };
50
51
52 enum UCA0TXIE_t {
53 UCA0TXIE_OFF = 0x00, /*! Interrupt disabled */
54 UCA0TXIE = 0x02 /*! Interrupt enabled */
55 };
56
57
58 enum UCA0RXIE_t {
59 UCA0RXIE_OFF = 0x00, /*! Interrupt disabled */
60 UCA0RXIE = 0x01 /*! Interrupt enabled */
61 };
62
63
64 enum UCB0TXIFG_t {
65 UCB0TXIFG_OFF = 0x00, /*! No interrupt pending */
66 UCB0TXIFG = 0x08 /*! Interrupt pending */
67 };
68
69
70 enum UCB0RXIFG_t {
71 UCB0RXIFG_OFF = 0x00, /*! No interrupt pending */
72 UCB0RXIFG = 0x04 /*! Interrupt pending */
73 };
74
75
76 enum UCA0TXIFG_t {
77 UCA0TXIFG_OFF = 0x00, /*! No interrupt pending */
78 UCA0TXIFG = 0x02 /*! Interrupt pending */
79 };
80
81
82 enum UCA0RXIFG_t {
83 UCA0RXIFG_OFF = 0x00, /*! No interrupt pending */
84 UCA0RXIFG = 0x01 /*! Interrupt pending */
85 };
86
87 /*! IE2, Interrupt Enable Register 2 */
88 struct IE2_t {
89 UCB0TXIE_t UCB0TXIE; /*! USCI_B0 transmit interrupt enable
90 * 0 Interrupt disabled
91 * 1 Interrupt enabled */
92 UCB0RXIE_t UCB0RXIE; /*! USCI_B0 receive interrupt enable
93 * 0 Interrupt disabled
94 * 1 Interrupt enabled */
95 UCA0TXIE_t UCA0TXIE; /*! USCI_A0 transmit interrupt enable
96 * 0 Interrupt disabled
97 * 1 Interrupt enabled */
98 UCA0RXIE_t UCA0RXIE; /*! USCI_A0 receive interrupt enable
99 * 0 Interrupt disabled
100 * 1 Interrupt enabled */
101 }
102
103 /*! IFG2, Interrupt Flag Register 2 */
104 struct IFG2_t {
105 UCB0TXIFG_t UCB0TXIFG; /*! USCI_B0 transmit interrupt flag
106 * 0 No interrupt pending
107 * 1 Interrupt pending */
108 UCB0RXIFG_t UCB0RXIFG; /*! USCI_B0 receive interrupt flag
109 * 0 No interrupt pending
110 * 1 Interrupt pending */
111 UCA0TXIFG_t UCA0TXIFG; /*! USCI_A0 transmit interrupt flag
112 * 0 No interrupt pending
113 * 1 Interrupt pending */
114 UCA0RXIFG_t UCA0RXIFG; /*! USCI_A0 receive interrupt flag
115 * 0 No interrupt pending
116 * 1 Interrupt pending */
117 }
118
119 /*!
120 * ======== regIntVect_t ========
121 * Interrupt vector description
122 *
123 * Type to describe a single interrupt vector pin and all its possible
124 * configurations.
125 *
126 * @see #regIntVect_t
127 */
128 struct regIntVect_t {
129 String registerName;
130 String registerDescription;
131 String isrToggleString;
132 String priorityName;
133 Bool interruptEnable;
134 Bool interruptHandler;
135 Int priority;
136 }
137
138 /*!
139 * ======== ForceSetDefaultRegister_t ========
140 * Force Set Default Register
141 *
142 * Type to store if each register needs to be forced initialized
143 * even if the register is in default state.
144 *
145 * @see #ForceSetDefaultRegister_t
146 */
147 struct ForceSetDefaultRegister_t {
148 String register;
149 Bool regForceSet;
150 }
151
152 instance:
153 /*! IE2, Interrupt Enable Register 2 */
154 config IE2_t IE2 = {
155 UCB0TXIE : UCB0TXIE_OFF,
156 UCB0RXIE : UCB0RXIE_OFF,
157 UCA0TXIE : UCA0TXIE_OFF,
158 UCA0RXIE : UCA0RXIE_OFF,
159 };
160
161 /*! IFG2, Interrupt Flag Register 2 */
162 config IFG2_t IFG2 = {
163 UCB0TXIFG : UCB0TXIFG_OFF,
164 UCB0RXIFG : UCB0RXIFG_OFF,
165 UCA0TXIFG : UCA0TXIFG_OFF,
166 UCA0RXIFG : UCA0RXIFG_OFF,
167 };
168
169 /*!
170 * ======== getUCB0TXIE ========
171 * Gets UCB0TXIE bit
172 *
173 * @see #getUCB0TXIE
174 */
175 Bool getUCB0TXIE();
176
177 /*!
178 * ======== setUCB0TXIE ========
179 * Sets UCB0TXIE bit
180 *
181 * @see #setUCB0TXIE
182 */
183 Bool setUCB0TXIE(Bool set);
184
185 /*!
186 * ======== getUCB0RXIE ========
187 * Gets UCB0RXIE bit
188 *
189 * @see #getUCB0RXIE
190 */
191 Bool getUCB0RXIE();
192
193 /*!
194 * ======== setUCB0RXIE ========
195 * Sets UCB0RXIE bit
196 *
197 * @see #setUCB0RXIE
198 */
199 Bool setUCB0RXIE(Bool set);
200
201 /*!
202 * ======== getUCA0TXIE ========
203 * Gets UCA0TXIE bit
204 *
205 * @see #getUCA0TXIE
206 */
207 Bool getUCA0TXIE();
208
209 /*!
210 * ======== setUCA0TXIE ========
211 * Sets UCA0TXIE bit
212 *
213 * @see #setUCA0TXIE
214 */
215 Bool setUCA0TXIE(Bool set);
216
217 /*!
218 * ======== getUCA0RXIE ========
219 * Gets UCA0RXIE bit
220 *
221 * @see #getUCA0RXIE
222 */
223 Bool getUCA0RXIE();
224
225 /*!
226 * ======== setUCA0RXIE ========
227 * Sets UCA0RXIE bit
228 *
229 * @see #setUCA0RXIE
230 */
231 Bool setUCA0RXIE(Bool set);
232
233 /*! IE2 interrupt enables
234 */
235 config regIntVect_t interruptSource[8];
236
237 /*!
238 * ======== forceSetDefaultRegister ========
239 * Determine if each Register needs to be forced set or not
240 */
241 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
242 [
243 { register : "IE2" , regForceSet : false },
244 { register : "IFG2" , regForceSet : false },
245 ];
246 }