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38 package ti.catalog.c6000;
39
40 metaonly interface ICacheInfo {
41 /*!
42 * ======== CacheDesc ========
43 * Structure used by ICpuDataSheet implementations to
44 * specify device cache modes.
45 *
46 * A map is defined by an ICpuDataSheet implementation
47 * that maps a string denoting a device register setting
48 * to a CacheDesc structure. This maybe used in implementing
49 * the 'getMemoryMap' method. An example of such a map is shown below :
50 *
51 * readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
52 * ['l1PMode',{desc:"L1P Cache",
53 * map : [["0k",0x0000],
54 * ["4k",0x1000],
55 * ["8k",0x2000],
56 * ["16k",0x4000],
57 * ["32k",0x8000]],
58 * defaultValue: "32k",
59 * memorySection: "L1PSRAM"}],
60 *
61 * ['l1DMode',{desc:"L1D Cache",
62 * map : [["0k",0x0000],
63 * ["4k",0x1000],
64 * ["8k",0x2000],
65 * ["16k",0x4000],
66 * ["32k",0x8000]],
67 * defaultValue: "32k",
68 * memorySection: "L1DSRAM"}],
69 *
70 * ['l2Mode',{desc:"L2 Cache",
71 * map : [["0k",0x0000],
72 * ["32k",0x8000],
73 * ["64k",0x10000],
74 * ["128k",0x20000],
75 * ["256k",0x40000]],
76 * defaultValue: "0k",
77 * memorySection: "IRAM"}],
78 *
79 * ];
80 *
81 * @_nodoc
82 */
83 struct CacheDesc {
84 string desc; /*! String describing the register setting */
85 Int base; /*! base address of cache */
86 unsigned map[string]; /*! A hash of cache modes to cache size*/
87 string defaultValue; /*! The default cache mode for the device */
88 string memorySection; /*! The associated memory section */
89 };
90
91
92 }