1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*!
    34     * Universal Serial Communication Interface A1 UART 2xx
    35     */
    36    metaonly interface IUSCI_A1_UART inherits IUSCI_UART {
    37    
    38    instance:
    39        /*! Control Register 0 */
    40        config UCxCTL0_t UCA1CTL0 = {
    41            UCPEN       : UCPEN_OFF,
    42            UCPAR       : UCPAR_OFF,
    43            UCMSB       : UCMSB_OFF,
    44            UC7BIT      : UC7BIT_OFF,
    45            UCSPB       : UCSPB_OFF,
    46            UCMODE      : UCMODE_0,
    47            UCSYNC      : UCSYNC_OFF,
    48        };
    49    
    50        /*! Control Register 1 */
    51        config UCxCTL1_t UCA1CTL1 = {
    52            UCSSEL      : UCSSEL_0,
    53            UCRXEIE     : UCRXEIE_OFF,
    54            UCBRKIE     : UCBRKIE_OFF,
    55            UCDORM      : UCDORM_OFF,
    56            UCTXADDR    : UCTXADDR_OFF,
    57            UCTXBRK     : UCTXBRK_OFF,
    58            UCSWRST     : UCSWRST,
    59        };
    60    
    61        /*! Modulation Control Register */
    62        config UCxMCTL_t UCA1MCTL = {
    63            UCBRF       : UCBRF_0,
    64            UCBRS       : UCBRS_0,
    65            UCOS16      : UCOS16_OFF,
    66        };
    67    
    68        /*! Status Register */
    69        config UCxSTAT_t UCA1STAT = {
    70            UCLISTEN    : UCLISTEN_OFF,
    71            UCFE        : UCFE_OFF,
    72            UCOE        : UCOE_OFF,
    73            UCPE        : UCPE_OFF,
    74            UCBRK       : UCBRK_OFF,
    75            UCRXERR     : UCRXERR_OFF,
    76            UCADDR      : UCADDR_OFF,
    77            UCIDLE      : UCIDLE_OFF,
    78            UCBUSY      : UCBUSY,
    79        };
    80    
    81        /*! IrDA Transmit Control Register */
    82        config UCxIRTCTL_t UCA1IRTCTL = {
    83            UCIRTXPL5   : UCIRTXPL5_OFF,
    84            UCIRTXPL4   : UCIRTXPL4_OFF,
    85            UCIRTXPL3   : UCIRTXPL3_OFF,
    86            UCIRTXPL2   : UCIRTXPL2_OFF,
    87            UCIRTXPL1   : UCIRTXPL1_OFF,
    88            UCIRTXPL0   : UCIRTXPL0_OFF,
    89            UCIRTXCLK   : UCIRTXCLK_OFF,
    90            UCIREN      : UCIREN_OFF,
    91        };
    92    
    93        /*! IrDA Receive Control Register */
    94        config UCxIRRCTL_t UCA1IRRCTL = {
    95            UCIRRXFL5   : UCIRRXFL5_OFF,
    96            UCIRRXFL4   : UCIRRXFL4_OFF,
    97            UCIRRXFL3   : UCIRRXFL3_OFF,
    98            UCIRRXFL2   : UCIRRXFL2_OFF,
    99            UCIRRXFL1   : UCIRRXFL1_OFF,
   100            UCIRRXFL0   : UCIRRXFL0_OFF,
   101            UCIRRXPL    : UCIRRXPL_OFF,
   102            UCIRRXFE    : UCIRRXFE_OFF,
   103        };
   104    
   105        /*! Auto Baud Rate Control Register */
   106        config UCxABCTL_t UCA1ABCTL = {
   107            UCDELIM1    : UCDELIM1_OFF,
   108            UCDELIM0    : UCDELIM0_OFF,
   109            UCSTOE      : UCSTOE_OFF,
   110            UCBTOE      : UCBTOE_OFF,
   111            UCABDEN     : UCABDEN_OFF,
   112        };
   113    
   114        /*! Receive Buffer Register */
   115        config Bits8 UCA1RXBUF = 0;
   116    
   117        /*! Transmit Buffer Register */
   118        config Bits8 UCA1TXBUF = 0;
   119    
   120        /*! Baud rate control register 0 */
   121        config Bits8 UCA1BR0 = 0;
   122    
   123        /*! Baud rate control register 1 */
   124        config Bits8 UCA1BR1 = 0;
   125    }