1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*!
    34     *  ======== SD16_A ========
    35     *  MSP430F2xx Family SD16_A Module
    36     */
    37    metaonly module SD16_A inherits IADC {
    38    
    39         /*! SD16XDIVx Bits */
    40         enum SD16XDIV_t {
    41             SD16XDIV_0 = 0x000,  /*! Divide by 1 */
    42             SD16XDIV_1 = 0x200,  /*! Divide by 3 */
    43             SD16XDIV_2 = 0x400,  /*! Divide by 16 */
    44             SD16XDIV_3 = 0x800   /*! Divide by 48 */
    45         };
    46    
    47         /*! SD16LP Bit */
    48         enum SD16LP_t {
    49             SD16LP_OFF = 0x000,  /*! Low-power mode is disabled */
    50             SD16LP = 0x100       /*! Low-power mode is enabled. The maximum clock frequency for the SD16_A is reduced */
    51         };
    52    
    53         /*! SD16DIVx Bits */
    54         enum SD16DIV_t {
    55             SD16DIV_0 = 0x00,  /*! Divide by 1 */
    56             SD16DIV_1 = 0x40,  /*! Divide by 2 */
    57             SD16DIV_2 = 0x80,  /*! Divide by 4 */
    58             SD16DIV_3 = 0xC0   /*! Divide by 8 */
    59         };
    60    
    61         /*! SD16SSELx Bits */
    62         enum SD16SSEL_t {
    63             SD16SSEL_0 = 0x00,  /*! MCLK */
    64             SD16SSEL_1 = 0x10,  /*! SMCLK */
    65             SD16SSEL_2 = 0x20,  /*! ACLK */
    66             SD16SSEL_3 = 0x30   /*! External TACLK */
    67         };
    68    
    69         /*! SD16VMIDON Bit */
    70         enum SD16VMIDON_t {
    71             SD16VMIDON_OFF = 0x00,  /*! Off */
    72             SD16VMIDON = 0x08       /*! On */
    73         };
    74    
    75         /*! SD16REFON Bit */
    76         enum SD16REFON_t {
    77             SD16REFON_OFF = 0x00,  /*! Reference off */
    78             SD16REFON = 0x04       /*! Reference on */
    79         };
    80    
    81         /*! SD16OVIE Bit */
    82         enum SD16OVIE_t {
    83             SD16OVIE_OFF = 0x00,  /*! Overflow interrupt disabled */
    84             SD16OVIE = 0x02       /*! Overflow interrupt enabled */
    85         };
    86    
    87         /*! SD16BUFx Bits */
    88         enum SD16BUF_t {
    89             SD16BUF_0 = 0x0000,  /*! Buffer disabled */
    90             SD16BUF_1 = 0x2000,  /*! Slow speed/current */
    91             SD16BUF_2 = 0x4000,  /*! Medium speed/current */
    92             SD16BUF_3 = 0x6000   /*! High speed/current */
    93         };
    94    
    95         /*! SD16UNI Bit */
    96         enum SD16UNI_t {
    97             SD16UNI_OFF = 0x0000,  /*! Bipolar mode */
    98             SD16UNI = 0x10000      /*! Unipolar mode */
    99         };
   100    
   101         /*! SD16XOSR Bit */
   102         enum SD16XOSR_t {
   103             SD16XOSR_OFF = 0x000,  /*! Extended oversampling ratio. This bit, along with the SD16OSRx bits,
   104                                     * select the oversampling ratio. See SD16OSRx bit description for settings */
   105             SD16XOSR = 0x800       /*! Extended oversampling ratio. This bit, along with the SD16OSRx bits,
   106                                     * select the oversampling ratio. See SD16OSRx bit description for settings */
   107         };
   108    
   109         /*! SD16SNGL Bit */
   110         enum SD16SNGL_t {
   111             SD16SNGL_OFF = 0x000,  /*! Continuous conversion mode */
   112             SD16SNGL = 0x400       /*! Single conversion mode */
   113         };
   114    
   115         /*! SD16OSRx Bits */
   116         enum SD16OSR_t {
   117             SD16OSR_256 = 0x000, /*! SD16XOSR = 0 */
   118             SD16OSR_128 = 0x100, /*! SD16XOSR = 0 */
   119             SD16OSR_64 = 0x200,  /*! SD16XOSR = 0 */
   120             SD16OSR_32 = 0x300,  /*! SD16XOSR = 0 */
   121             SD16OSR_512 = 0x800, /*! SD16XOSR = 1 */
   122             SD16OSR_1024 = 0x900 /*! SD16XOSR = 1 */
   123         };
   124    
   125         /*! SD16LSBTOG Bit */
   126         enum SD16LSBTOG_t {
   127             SD16LSBTOG_OFF = 0x00,  /*! SD16LSBACC does not toggle with each SD16MEM0 read */
   128             SD16LSBTOG = 0x80       /*! SD16LSBACC toggles with each SD16MEM0 read */
   129         };
   130    
   131         /*! SD16LSBACC Bit */
   132         enum SD16LSBACC_t {
   133             SD16LSBACC_OFF = 0x00,  /*! SD16MEMx contains the most significant 16-bits of the conversion */
   134             SD16LSBACC = 0x40       /*! SD16MEMx contains the least significant 16-bits of the conversion */
   135         };
   136    
   137         /*! SD16OVIFG Bit */
   138         enum SD16OVIFG_t {
   139             SD16OVIFG_OFF = 0x00,  /*! No overflow interrupt pending */
   140             SD16OVIFG = 0x20       /*! Overflow interrupt pending */
   141         };
   142    
   143         /*! SD16DF Bit */
   144         enum SD16DF_t {
   145             SD16DF_OFF = 0x00,  /*! Offset binary */
   146             SD16DF = 0x10       /*! 2's complement */
   147         };
   148    
   149         /*! SD16IE Bit */
   150         enum SD16IE_t {
   151             SD16IE_OFF = 0x00,  /*! Disabled */
   152             SD16IE = 0x08       /*! Enabled */
   153         };
   154    
   155         /*! SD16IFG Bit */
   156         enum SD16IFG_t {
   157             SD16IFG_OFF = 0x00,  /*! No interrupt pending */
   158             SD16IFG = 0x04       /*! Interrupt pending */
   159         };
   160    
   161         /*! SD16SC Bit */
   162         enum SD16SC_t {
   163             SD16SC_OFF = 0x00,  /*! No conversino start */
   164             SD16SC = 0x02       /*! Start conversion */
   165         };
   166    
   167         /*! SD16INTDLYx Bits */
   168         enum SD16INTDLY_t {
   169             SD16INTDLY_0 = 0x00,  /*! Fourth sample causes interrupt */
   170             SD16INTDLY_1 = 0x40,  /*! Third sample causes interrupt */
   171             SD16INTDLY_2 = 0x80,  /*! Second sample causes interrupt */
   172             SD16INTDLY_3 = 0xC0   /*! First sample causes interrupt */
   173         };
   174    
   175         /*! SD16GAINx Bits */
   176         enum SD16GAIN_t {
   177             SD16GAIN_1 = 0x00,  /*! Multiply by 1 */
   178             SD16GAIN_2 = 0x08,  /*! Multiply by 2 */
   179             SD16GAIN_4 = 0x10,  /*! Multiply by 4 */
   180             SD16GAIN_8 = 0x18,  /*! Multiply by 8 */
   181             SD16GAIN_16 = 0x20,  /*! Multiply by 16 */
   182             SD16GAIN_32 = 0x28   /*! Multiply by 32 */
   183         };
   184    
   185         /*! SD16INCHx Bits */
   186         enum SD16INCH_t {
   187             SD16INCH_0 = 0x000,  /*! A0 */
   188             SD16INCH_1 = 0x001,  /*! A1 */
   189             SD16INCH_2 = 0x010,  /*! A2 */
   190             SD16INCH_3 = 0x011,  /*! A3 */
   191             SD16INCH_4 = 0x100,  /*! A4 */
   192             SD16INCH_5 = 0x101,  /*! A5 - (AVcc - AVss)/11 */
   193             SD16INCH_6 = 0x110,  /*! A6 - Temperature Sensor */
   194             SD16INCH_7 = 0x111   /*! A7 - Short PGA offset measurement */
   195         };
   196    
   197    
   198        /*! SD16_A Analog Enable Bit 7 */
   199        enum SD16AE7_t {
   200            SD16AE7_OFF = 0x0000,  /*! External input disabled. Negative inputs are internally connected to VSS. */
   201            SD16AE7     = 0x0080   /*! External input enabled */
   202        };
   203    
   204        /*! SD16_A Analog Enable Bit 6 */
   205        enum SD16AE6_t {
   206            SD16AE6_OFF = 0x0000,  /*! External input disabled. Negative inputs are internally connected to VSS. */
   207            SD16AE6     = 0x0040   /*! External input enabled */
   208        };
   209    
   210        /*! SD16_A Analog Enable Bit 5 */
   211        enum SD16AE5_t {
   212            SD16AE5_OFF = 0x0000,  /*! External input disabled. Negative inputs are internally connected to VSS. */
   213            SD16AE5     = 0x0020   /*! External input enabled */
   214        };
   215    
   216        /*! SD16_A Analog Enable Bit 4 */
   217        enum SD16AE4_t {
   218            SD16AE4_OFF = 0x0000,  /*! External input disabled. Negative inputs are internally connected to VSS. */
   219            SD16AE4     = 0x0010   /*! External input enabled */
   220        };
   221    
   222        /*! SD16_A Analog Enable Bit 3 */
   223        enum SD16AE3_t {
   224            SD16AE3_OFF = 0x0000,  /*! External input disabled. Negative inputs are internally connected to VSS. */
   225            SD16AE3     = 0x0008   /*! External input enabled */
   226        };
   227    
   228        /*! SD16_A Analog Enable Bit 2 */
   229        enum SD16AE2_t {
   230            SD16AE2_OFF = 0x0000,  /*! External input disabled. Negative inputs are internally connected to VSS. */
   231            SD16AE2     = 0x0004   /*! External input enabled */
   232        };
   233    
   234        /*! SD16_A Analog Enable Bit 1 */
   235        enum SD16AE1_t {
   236            SD16AE1_OFF = 0x0000,  /*! External input disabled. Negative inputs are internally connected to VSS. */
   237            SD16AE1     = 0x0002   /*! External input enabled */
   238        };
   239    
   240        /*! SD16_A Analog Enable Bit 0 */
   241        enum SD16AE0_t {
   242            SD16AE0_OFF = 0x0000,  /*! External input disabled. Negative inputs are internally connected to VSS. */
   243            SD16AE0     = 0x0001   /*! External input enabled */
   244        };
   245    
   246        /*! SD16_A Interrupt */
   247        enum SD16IV_SD16OVIFG_t {
   248            SD16IV_SD16OVIFG_OFF = 0x0000,  /*! No Interrupt pending */
   249            SD16IV_SD16OVIFG     = 0x0002   /*! SD16OVIFG */
   250        };
   251    
   252        /*! SD16_A SD16MEMx overflow */
   253        enum SD16IV_SD16MEM0_t {
   254            SD16IV_SD16MEM0_OFF = 0x0000,  /*! No Interrupt pending */
   255            SD16IV_SD16MEM0     = 0x0004   /*! SD16MEM0 SD16IFG */
   256        };
   257    
   258        /*! SD16CTL Register */
   259        struct SD16CTL_t {
   260            SD16XDIV_t SD16XDIV;     /*! SD16_A clock divider
   261                                      * 000 Divide by 1
   262                                      * 001 Divide by 3
   263                                      * 010 Divide by 16
   264                                      * 011 Divide by 48
   265                                      * 1xx Reserved */
   266            SD16LP_t SD16LP;         /*! Low power mode. This bit selects a reduced speed, reduced power mode
   267                                      * 0 Low-power mode is disabled
   268                                      * 1 Low-power mode is enabled. The maximum clock frequency for the
   269                                      *  SD16_A is reduced. */
   270            SD16DIV_t SD16DIV;       /*! SD16_A clock divider
   271                                      * 00 Divide by 1
   272                                      * 01 Divide by 2
   273                                      * 10 Divide by 4
   274                                      * 11 Divide by 8 */
   275            SD16SSEL_t SD16SSEL;     /*! SD16_A clock source select
   276                                      * 00 MCLK
   277                                      * 01 SMCLK
   278                                      * 10 ACLK
   279                                      * External TACLK */
   280            SD16VMIDON_t SD16VMIDON; /*! VMID buffer on
   281                                      * 0 Off
   282                                      * 1 On */
   283            SD16REFON_t SD16REFON;   /*! Reference generator on
   284                                      * 0 Reference off
   285                                      * 1 Reference on */
   286            SD16OVIE_t SD16OVIE;     /*! SD16_A overflow interrupt enable. The GIE bit must also be set to enable the
   287                                      * interrupt.
   288                                      * 0 Overflow interrupt disabled
   289                                      * 1 Overflow interrupt enabled */
   290        };
   291    
   292        /*! SD16CCTL0 Register */
   293        struct SD16CCTL0_t {
   294            SD16UNI_t SD16UNI;       /*! Unipolar mode select
   295                                      * 0 Bipolar mode
   296                                      * 1 Unipolar mode */
   297            SD16XOSR_t SD16XOSR;     /*! Extended oversampling ratio. This bit, along with the SD16OSRx bits,
   298                                      * select the oversampling ratio. See SD16OSRx bit description for settings. */
   299            SD16SNGL_t SD16SNGL;     /*! Single conversion mode select
   300                                      * 0 Continuous conversion mode
   301                                      * 1 Single conversion mode */
   302            SD16OSR_t SD16OSR;       /*! Oversampling ratio
   303                                      * When SD16XOSR = 0
   304                                      * 00 256
   305                                      * 01 128
   306                                      * 10 64
   307                                      * 11 32
   308                                      * When SD16XOSR = 1
   309                                      * 00 512
   310                                      * 01 1024
   311                                      * 10 Reserved
   312                                      * 11 Reserved */
   313            SD16LSBTOG_t SD16LSBTOG; /*! LSB toggle. This bit, when set, causes SD16LSBACC to toggle each time
   314                                      * the SD16MEM0 register is read.
   315                                      * 0 SD16LSBACC does not toggle with each SD16MEM0 read
   316                                      * 1 SD16LSBACC toggles with each SD16MEM0 read */
   317            SD16LSBACC_t SD16LSBACC; /*! LSB access. This bit allows access to the upper or lower 16-bits of the
   318                                      * SD16_A conversion result.
   319                                      * 0 SD16MEMx contains the most significant 16-bits of the conversion.
   320                                      * 1 SD16MEMx contains the least significant 16-bits of the conversion. */
   321            SD16OVIFG_t SD16OVIFG;   /*! SD16_A overflow interrupt flag
   322                                      * 0 No overflow interrupt pending
   323                                      * 1 Overflow interrupt pending */
   324            SD16DF_t SD16DF;         /*! SD16_A data format
   325                                      * 0 Offset binary
   326                                      * 1 2's complement */
   327            SD16IE_t SD16IE;         /*! SD16_A interrupt enable
   328                                      * 0 Disabled
   329                                      * 1 Enabled */
   330            SD16IFG_t SD16IFG;       /*! SD16_A interrupt flag. SD16IFG is set when new conversion results are
   331                                      * available. SD16IFG is automatically reset when the corresponding
   332                                      * SD16MEMx register is read, or may be cleared with software.
   333                                      * 0 No interrupt pending
   334                                      * 1 Interrupt pending */
   335            SD16SC_t SD16SC;         /*! SD16_A start conversion
   336                                      * 0 No conversion start
   337                                      * 1 Start conversion */
   338        };
   339    
   340        /*! SD16INCTL0 Register */
   341        struct SD16INCTL0_t {
   342            SD16INTDLY_t SD16INTDLY;  /*! Interrupt delay generation after conversion start. These bits select the
   343                                       * delay for the first interrupt after conversion start.
   344                                       * 00 Fourth sample causes interrupt
   345                                       * 01 Third sample causes interrupt
   346                                       * 10 Second sample causes interrupt
   347                                       * 11 First sample causes interrupt */
   348    
   349            SD16GAIN_t SD16GAIN;      /*! SD16_A preamplifier gain
   350                                       * 000 Multiply by 1
   351                                       * 001 Multiply by 2
   352                                       * 010 Multiply by 4
   353                                       * 011 Multiply by 8
   354                                       * 100 Multiply by 16
   355                                       * 101 Multiply by 32
   356                                       * 110 Reserved
   357                                       * 111 Reserved */
   358    
   359            SD16INCH_t SD16INCH;      /*! SD16_A channel differential pair input
   360                                       * 000 A0
   361                                       * 001 A1
   362                                       * 010 A2
   363                                       * 011 A3
   364                                       * 100 A4
   365                                       * 101 A5-- (AVCC -- AVSS) / 11
   366                                       * 110 A6 -- Temperature Sensor
   367                                       * 111 A7 -- Short for PGA offset measurement */
   368        };
   369    
   370        /*! SD16_A Analog Input Enable Register */
   371        struct SD16AE_t {
   372             SD16AE0_t SD16AE0; /*! SD16_A analog enable
   373                                 * 0 External input disabled. Negative inputs are internally connected to
   374                                 *   VSS.
   375                                 * 1 External input enabled */
   376             SD16AE1_t SD16AE1; /*! SD16_A analog enable
   377                                 * 0 External input disabled. Negative inputs are internally connected to
   378                                 *   VSS.
   379                                 * 1 External input enabled */
   380            SD16AE2_t SD16AE2; /*! SD16_A analog enable
   381                                * 0 External input disabled. Negative inputs are internally connected to
   382                                *   VSS.
   383                                * 1 External input enabled */
   384            SD16AE3_t SD16AE3; /*! SD16_A analog enable
   385                                * 0 External input disabled. Negative inputs are internally connected to
   386                                *   VSS.
   387                                * 1 External input enabled */
   388            SD16AE4_t SD16AE4; /*! SD16_A analog enable
   389                                * 0 External input disabled. Negative inputs are internally connected to
   390                                *   VSS.
   391                                * 1 External input enabled */
   392            SD16AE5_t SD16AE5; /*! SD16_A analog enable
   393                                * 0 External input disabled. Negative inputs are internally connected to
   394                                *   VSS.
   395                                * 1 External input enabled */
   396            SD16AE6_t SD16AE6; /*! SD16_A analog enable
   397                                * 0 External input disabled. Negative inputs are internally connected to
   398                                *   VSS.
   399                                * 1 External input enabled */
   400            SD16AE7_t SD16AE7; /*! SD16_A analog enable
   401                                * 0 External input disabled. Negative inputs are internally connected to
   402                                *   VSS.
   403                                * 1 External input enabled */
   404        };
   405    
   406    instance:
   407    
   408        /*! SD16CTL Register */
   409        config SD16CTL_t SD16CTL = {
   410            SD16XDIV    : SD16XDIV_0,
   411            SD16LP      : SD16LP_OFF,
   412            SD16DIV     : SD16DIV_0,
   413            SD16SSEL    : SD16SSEL_0,
   414            SD16VMIDON  : SD16VMIDON_OFF,
   415            SD16REFON   : SD16REFON_OFF,
   416            SD16OVIE    : SD16OVIE_OFF
   417        };
   418    
   419        /*! SD16CCTL0 Register */
   420        config SD16CCTL0_t SD16CCTL0 = {
   421            SD16UNI     : SD16UNI_OFF,
   422            SD16XOSR    : SD16XOSR_OFF,
   423            SD16SNGL    : SD16SNGL_OFF,
   424            SD16OSR     : SD16OSR_256,
   425            SD16LSBTOG  : SD16LSBTOG_OFF,
   426            SD16LSBACC  : SD16LSBACC_OFF,
   427            SD16OVIFG   : SD16OVIFG_OFF,
   428            SD16DF      : SD16DF_OFF,
   429            SD16IE      : SD16IE_OFF,
   430            SD16IFG     : SD16IFG_OFF,
   431            SD16SC      : SD16SC_OFF
   432        };
   433    
   434        /*! SD16INCTL0 Register */
   435        config SD16INCTL0_t SD16INCTL0 = {
   436            SD16INTDLY  : SD16INTDLY_0,
   437            SD16GAIN    : SD16GAIN_1,
   438            SD16INCH    : SD16INCH_0
   439        };
   440    
   441        /*! SD16AE Register */
   442        config SD16AE_t SD16AE = {
   443            SD16AE0 : SD16AE0_OFF,
   444            SD16AE1 : SD16AE1_OFF,
   445            SD16AE2 : SD16AE2_OFF,
   446            SD16AE3 : SD16AE3_OFF,
   447            SD16AE4 : SD16AE4_OFF,
   448            SD16AE5 : SD16AE5_OFF,
   449            SD16AE6 : SD16AE6_OFF,
   450            SD16AE7 : SD16AE7_OFF
   451        };
   452    
   453        /*! SD16IV Register */
   454        config Bits16 SD16IV = SD16IV_SD16OVIFG_OFF;
   455    
   456        /*! SD16MEM0 Register */
   457        config Bits16 SD16MEM0 = SD16IV_SD16MEM0_OFF;
   458    
   459        /*! ADC10 has 1 interrupt enable */
   460        config regIntVect_t interruptSource[2];
   461    
   462        /*! Determine if each Register needs to be forced set or not */
   463        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   464        [
   465            { register : "SD16CTL" , regForceSet : false },
   466            { register : "SD16CCTL0" , regForceSet : false },
   467            { register : "SD16INCTL0" , regForceSet : false },
   468            { register : "SD16AE" , regForceSet : false },
   469            { register : "SD16IV" , regForceSet : false },
   470            { register : "SD16MEM0" , regForceSet : false }
   471        ];
   472    }