1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*!
    34     *  ======== Timer_B3 ========
    35     *  MSP430 Timer_B timer
    36     */
    37    metaonly module Timer_B3 inherits ITimer_B {
    38    
    39        /*! TB3IV Definitions */
    40        enum IVValues {
    41            TBIV_NONE = 0x0000,                 /*! No Interrupt pending */
    42            TBIV_TBCCR1 = 0x0002,               /*! TBCCR1_CCIFG */
    43            TBIV_TBCCR2 = 0x0004,               /*! TBCCR2_CCIFG */
    44            TBIV_6 = 0x0006,                    /*! Reserved */
    45            TBIV_8 = 0x0008,                    /*! Reserved */
    46            TBIV_TBIFG = 0x000A                 /*! TBIFG */
    47        };
    48    
    49    instance:
    50        /*! TBCTL, Timer_B3 Control Register */
    51        config TBCTL_t TBCTL = {
    52            TBCLGRP : TBCLGRP_0,
    53            CNTL : CNTL_0,
    54            TBSSEL : TBSSEL_0,
    55            ID : ID_0,
    56            MC : MC_0,
    57            TBCLR : TBCLR_OFF,
    58            TBIE : TBIE_OFF,
    59            TBIFG : TBIFG_OFF
    60        };
    61    
    62        /*! TBCCTL0, Capture/Compare Control Register 0 */
    63        config TBCCTLx_t TBCCTL0 = {
    64            CM : CM_0,
    65            CCIS : CCIS_0,
    66            SCS : SCS_OFF,
    67            CLLD : CLLD_0,
    68            CAP : CAP_OFF,
    69            OUTMOD : OUTMOD_0,
    70            CCIE : CCIE_OFF,
    71            CCI : CCI_OFF,
    72            OUT : OUT_OFF,
    73            COV : COV_OFF,
    74            CCIFG : CCIFG_OFF
    75        };
    76    
    77        /*! TBCCTL1, Capture/Compare Control Register 1 */
    78        config TBCCTLx_t TBCCTL1 = {
    79            CM : CM_0,
    80            CCIS : CCIS_0,
    81            SCS : SCS_OFF,
    82            CLLD : CLLD_0,
    83            CAP : CAP_OFF,
    84            OUTMOD : OUTMOD_0,
    85            CCIE : CCIE_OFF,
    86            CCI : CCI_OFF,
    87            OUT : OUT_OFF,
    88            COV : COV_OFF,
    89            CCIFG : CCIFG_OFF
    90        };
    91    
    92        /*! TBCCTL2, Capture/Compare Control Register 2 */
    93        config TBCCTLx_t TBCCTL2 = {
    94            CM : CM_0,
    95            CCIS : CCIS_0,
    96            SCS : SCS_OFF,
    97            CLLD : CLLD_0,
    98            CAP : CAP_OFF,
    99            OUTMOD : OUTMOD_0,
   100            CCIE : CCIE_OFF,
   101            CCI : CCI_OFF,
   102            OUT : OUT_OFF,
   103            COV : COV_OFF,
   104            CCIFG : CCIFG_OFF
   105        };
   106    
   107        /*! TBCCR0, Timer_B Capture/Compare Register 0 */
   108        config Bits16 TBCCR0 = 0;
   109        /*! TBCCR1, Timer_B Capture/Compare Register 1 */
   110        config Bits16 TBCCR1 = 0;
   111        /*! TBCCR2, Timer_B Capture/Compare Register 2 */
   112        config Bits16 TBCCR2 = 0;
   113    
   114        /*! Timer interrupt enables */
   115        config regIntVect_t interruptSource[4];
   116    
   117        /*! Determine if each Register needs to be forced set or not */
   118        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   119        [
   120            { register : "TBCTL"   , regForceSet : false },
   121            { register : "TBCCTL0" , regForceSet : false },
   122            { register : "TBCCTL1" , regForceSet : false },
   123            { register : "TBCCTL2" , regForceSet : false },
   124            { register : "TBCCR0"  , regForceSet : false },
   125            { register : "TBCCR1"  , regForceSet : false },
   126            { register : "TBCCR2"  , regForceSet : false }
   127        ];
   128    }