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32
33 /*!
34 * ======== SFRIE1 ========
35 * MSP430 Interrupt Enable Register 1
36 */
37 metaonly module SFRIE1 inherits xdc.platform.IPeripheral {
38
39 enum JMBOUTIE_t {
40 JMBOUTIE_OFF = 0x00, /*! Interrupt not enabled */
41 JMBOUTIE = 0x80 /*! Interrupt enabled */
42 };
43
44 enum JMBINIE_t {
45 JMBINIE_OFF = 0x00, /*! Interrupt not enabled */
46 JMBINIE = 0x40 /*! Interrupt enabled */
47 };
48
49 enum ACCVIE_t {
50 ACCVIE_OFF = 0x00, /*! Interrupt not enabled */
51 ACCVIE = 0x20 /*! Interrupt enabled */
52 };
53
54 enum NMIIE_t {
55 NMIIE_OFF = 0x00, /*! Interrupt not enabled */
56 NMIIE = 0x10 /*! Interrupt enabled */
57 };
58
59 enum OFIE_t {
60 OFIE_OFF = 0x00, /*! Interrupt not enabled */
61 OFIE = 0x02 /*! Interrupt enabled */
62 };
63
64 enum WDTIE_t {
65 WDTIE_OFF = 0x00, /*! Interrupt not enabled */
66 WDTIE = 0x01 /*! Interrupt enabled */
67 };
68
69 enum NMIIFG_t {
70 NMIIFG_OFF = 0x00, /*! No interrupt pending */
71 NMIIFG = 0x10 /*! Interrupt pending */
72 };
73
74 enum WDTIFG_t {
75 WDTIFG_OFF = 0x00, /*! No interrupt pending */
76 WDTIFG = 0x01 /*! Interrupt pending */
77 };
78
79 enum OFIFG_t {
80 OFIFG_OFF = 0x00, /*! No interrupt pending */
81 OFIFG = 0x02 /*! Interrupt pending */
82 };
83
84 enum ACCVIFG_t {
85 ACCVIFG_OFF = 0x00, /*! No interrupt pending */
86 ACCVIFG = 0x20 /*! Interrupt pending */
87 };
88
89
90 struct IE1_t {
91 ACCVIE_t ACCVIE; /*! Flash memory access violation interrupt
92 * enable. This bit enables the ACCVIFG interrupt.
93 * 0 Interrupt disabled
94 * 1 Interrupt enabled */
95 NMIIE_t NMIIE; /*! NMI interrupt enable. This bit enables
96 *the NMI interrupt.
97 * 0 Interrupt disabled
98 * 1 Interrupt enabled */
99 OFIE_t OFIE; /*! Oscillator fault flag interrupt enable
100 *This bit enables the OFIFG interrupt.
101 * 0 Interrupt disabled
102 * 1 Interrupt enabled */
103 WDTIE_t WDTIE; /*! Watchdog timer+ interrupt enable. This
104 *bit enables the WDTIFG interrupt for
105 *interval timer mode. It is not necessary
106 *to set this bit for watchdog mode.
107 * 0 Interrupt disabled
108 * 1 Interrupt enabled */
109 }
110
111
112 struct IFG1_t {
113 ACCVIFG_t ACCVIFG; /*! Flash memory access violation interrupt
114 * flag.
115 * 0 No interrupt pending
116 * 1 Interrupt pending */
117 NMIIFG_t NMIIFG; /*! NMI interrupt flag.
118 * 0 No interrupt pending
119 * 1 Interrupt pending */
120 OFIFG_t OFIFG; /*! Oscillator fault interrupt flag
121 * 0 No interrupt pending
122 * 1 Interrupt pending */
123 WDTIFG_t WDTIFG; /*! Watchdog timer+ interrupt flag.
124 * 0 No interrupt pending
125 * 1 Interrupt pending */
126 }
127
128 /*!
129 * ======== ForceSetDefaultRegister_t ========
130 * Force Set Default Register
131 *
132 * Type to store if each register needs to be forced initialized
133 * even if the register is in default state.
134 *
135 * @see #ForceSetDefaultRegister_t
136 */
137 struct ForceSetDefaultRegister_t {
138 String register;
139 Bool regForceSet;
140 }
141
142 /*!
143 * ======== regIntVect_t ========
144 * Interrupt vector description
145 *
146 * Type to describe a single interrupt vector pin and all its possible
147 * configurations.
148 *
149 * @see #regIntVect_t
150 */
151 struct regIntVect_t {
152 String registerName;
153 String registerDescription;
154 String isrToggleString;
155 String priorityName;
156 Bool interruptEnable;
157 Bool interruptHandler;
158 Int priority;
159 }
160
161 instance:
162
163 /*! SFRIE1 interrupt enables
164 */
165 config regIntVect_t interruptSource[16];
166
167 /*! IE1, Interrupt Enable Register 1 */
168 config IE1_t SFRIE1 = {
169 ACCVIE : ACCVIE_OFF,
170 NMIIE : NMIIE_OFF,
171 OFIE : OFIE_OFF,
172 WDTIE : WDTIE_OFF
173 };
174
175 /*! IFG1, Interrupt Flag Register 1 */
176 config IFG1_t SFRIFG1 = {
177 ACCVIFG : ACCVIFG_OFF,
178 NMIIFG : NMIIFG_OFF,
179 OFIFG : OFIFG_OFF,
180 WDTIFG : WDTIFG_OFF
181 };
182
183 /*!
184 * ======== getSFRIE1 ========
185 * Gets a bit from the register in SFRIE1
186 *
187 * @see #getSFRIE1
188 */
189 Bool getSFRIE1(String register);
190
191 /*!
192 * ======== setSFRIE1 ========
193 * Sets a bit in the register SFRIE1
194 *
195 * @see #setSFRIE1
196 */
197 Bool setSFRIE1(String register, Bool set);
198
199 /*! Determine if each Register needs to be forced set or not */
200 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
201 [
202 { register : "SFRIE1" , regForceSet : false },
203 { register : "SFRIFG1" , regForceSet : false },
204 ];
205 }