1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    /*!
    34     *  ======== IE1 ========
    35     *  MSP430 Interrupt Enable Register 1
    36     */
    37    metaonly module IE1 inherits xdc.platform.IPeripheral {
    38    
    39        enum NMIIE_t {
    40            NMIIE_OFF  = 0x00,           /*! Interrupt not enabled */
    41            NMIIE      = 0x10            /*! Interrupt enabled */
    42        };
    43    
    44        enum WDTIE_t {
    45            WDTIE_OFF  = 0x00,           /*! Interrupt not enabled */
    46            WDTIE      = 0x01            /*! Interrupt enabled */
    47        };
    48    
    49        enum OFIE_t {
    50            OFIE_OFF   = 0x00,           /*! Interrupt not enabled */
    51            OFIE       = 0x02            /*! Interrupt enabled */
    52        };
    53    
    54        enum ACCVIE_t {
    55            ACCVIE_OFF = 0x00,           /*! Interrupt not enabled */
    56            ACCVIE     = 0x20            /*! Interrupt enabled */
    57        };
    58    
    59        enum NMIIFG_t {
    60            NMIIFG_OFF = 0x00,           /*! No interrupt pending */
    61            NMIIFG     = 0x10            /*! Interrupt pending */
    62        };
    63    
    64        enum WDTIFG_t {
    65            WDTIFG_OFF = 0x00,           /*! No interrupt pending */
    66            WDTIFG     = 0x01            /*! Interrupt pending */
    67        };
    68    
    69        enum OFIFG_t {
    70            OFIFG_OFF  = 0x00,           /*! No interrupt pending */
    71            OFIFG      = 0x02            /*! Interrupt pending */
    72        };
    73    
    74        enum ACCVIFG_t {
    75            ACCVIFG_OFF = 0x00,          /*! No interrupt pending */
    76            ACCVIFG     = 0x20           /*! Interrupt pending */
    77        };
    78    
    79        /* IE1 */
    80        struct IE1_t {
    81            ACCVIE_t    ACCVIE;          /*! Flash memory access violation interrupt
    82                                          * enable. This bit enables the ACCVIFG interrupt.
    83                                          *  0  Interrupt disabled
    84                                          *  1  Interrupt enabled */
    85            NMIIE_t      NMIIE;          /*! NMI interrupt enable. This bit enables
    86                                          *the NMI interrupt.
    87                                          *  0  Interrupt disabled
    88                                          *  1  Interrupt enabled */
    89            OFIE_t      OFIE;            /*! Oscillator fault flag interrupt enable
    90                                          *This bit enables the OFIFG interrupt.
    91                                          *  0  Interrupt disabled
    92                                          *  1  Interrupt enabled */
    93            WDTIE_t     WDTIE;           /*! Watchdog timer+ interrupt enable. This
    94                                          *bit enables the WDTIFG interrupt for
    95                                          *interval timer mode. It is not necessary
    96                                          *to set this bit for watchdog mode.
    97                                          *  0  Interrupt disabled
    98                                          *  1  Interrupt enabled */
    99        }
   100    
   101        /* IFG1 */
   102        struct IFG1_t {
   103            ACCVIFG_t    ACCVIFG;        /*! Flash memory access violation interrupt
   104                                          * flag.
   105                                          *  0  No interrupt pending
   106                                          *  1  Interrupt pending */
   107            NMIIFG_t     NMIIFG;         /*! NMI interrupt flag.
   108                                          *  0  No interrupt pending
   109                                          *  1  Interrupt pending */
   110            OFIFG_t      OFIFG;          /*! Oscillator fault interrupt flag
   111                                          *  0  No interrupt pending
   112                                          *  1  Interrupt pending */
   113            WDTIFG_t     WDTIFG;         /*! Watchdog timer+ interrupt flag.
   114                                          *  0  No interrupt pending
   115                                          *  1  Interrupt pending */
   116        }
   117    
   118       /*!
   119        *  ======== regIntVect_t ========
   120        *  Interrupt vector description
   121        *
   122        *  Type to describe a single interrupt vector pin and all its possible
   123        *  configurations.
   124        *
   125        *  @see #regIntVect_t
   126        */
   127        struct regIntVect_t {
   128            String                    registerName;
   129            String                    registerDescription;
   130            String                    isrToggleString;
   131            String                    priorityName;
   132            Bool                      interruptEnable;
   133            Bool                      interruptHandler;
   134            Int                       priority;
   135        }
   136    
   137        /*!
   138        *  ======== ForceSetDefaultRegister_t ========
   139        *  Force Set Default Register
   140        *
   141        *  Type to store if each register needs to be forced initialized
   142        *  even if the register is in default state.
   143        *
   144        *  @see #ForceSetDefaultRegister_t
   145        */
   146        struct ForceSetDefaultRegister_t {
   147            String     register;
   148            Bool       regForceSet;
   149        }
   150    
   151    instance:
   152        /*! IE1 interrupt enables
   153         */
   154        config regIntVect_t interruptSource[8];
   155    
   156        /*! IE1, Interrupt Enable Register 1 */
   157        config IE1_t IE1 = {
   158            ACCVIE      : ACCVIE_OFF,
   159            NMIIE       : NMIIE_OFF,
   160            OFIE        : OFIE_OFF,
   161            WDTIE       : WDTIE_OFF
   162        };
   163    
   164        /*! IFG1, Interrupt Flag Register 1 */
   165        config IFG1_t IFG1 = {
   166            ACCVIFG     : ACCVIFG_OFF,
   167            NMIIFG      : NMIIFG_OFF,
   168            OFIFG       : OFIFG_OFF,
   169            WDTIFG      : WDTIFG_OFF
   170        };
   171    
   172       /*!
   173        *  ======== getWDTIE ========
   174        *  Gets WDTIE bit
   175        *
   176        *  @see #getWDTIE
   177        */
   178        Bool    getWDTIE();
   179    
   180       /*!
   181        *  ======== setWDTIE ========
   182        *  Sets WDTIE bit
   183        *
   184        *  @see #setWDTIE
   185        */
   186        Bool    setWDTIE(Bool set);
   187    
   188       /*!
   189        *  ======== getWDTIFG ========
   190        *  Gets WDTIFG bit
   191        *
   192        *  @see #getWDTIFG
   193        */
   194        Bool    getWDTIFG();
   195    
   196       /*!
   197        *  ======== setWDTIFG ========
   198        *  Sets WDTIFG bit
   199        *
   200        *  @see #setWDTIFG
   201        */
   202        Bool    setWDTIFG(Bool set);
   203    
   204       /*!
   205        *  ======== getOFIE ========
   206        *  Gets OFIE bit
   207        *
   208        *  @see #getOFIE
   209        */
   210        Bool    getOFIE();
   211    
   212       /*!
   213        *  ======== setOFIE ========
   214        *  Sets OFIE bit
   215        *
   216        *  @see #setOFIE
   217        */
   218        Bool    setOFIE(Bool set);
   219    
   220       /*!
   221        *  ======== getOFIFG ========
   222        *  Gets OFIFG bit
   223        *
   224        *  @see #getOFIFG
   225        */
   226        Bool    getOFIFG();
   227    
   228       /*!
   229        *  ======== setOFIFG ========
   230        *  Sets OFIFG bit
   231        *
   232        *  @see #setOFIFG
   233        */
   234        Bool    setOFIFG(Bool set);
   235    
   236       /*!
   237        *  ======== getNMIIE ========
   238        *  Gets NMIIE bit
   239        *
   240        *  @see #getNMIIE
   241        */
   242        Bool    getNMIIE();
   243    
   244       /*!
   245        *  ======== setNMIIE ========
   246        *  Sets NMIIE bit
   247        *
   248        *  @see #setNMIIE
   249        */
   250        Bool    setNMIIE(Bool set);
   251    
   252       /*!
   253        *  ======== getNMIIFG ========
   254        *  Gets NMIIFG bit
   255        *
   256        *  @see #getNMIIFG
   257        */
   258        Bool    getNMIIFG();
   259    
   260       /*!
   261        *  ======== setNMIIFG ========
   262        *  Sets NMIIFG bit
   263        *
   264        *  @see #setNMIIFG
   265        */
   266        Bool    setNMIIFG(Bool set);
   267    
   268        /*!
   269        *  ======== getACCVIE ========
   270        *  Gets ACCVIE bit
   271        *
   272        *  @see #getACCVIE
   273        */
   274        Bool    getACCVIE();
   275    
   276       /*!
   277        *  ======== setACCVIE ========
   278        *  Sets ACCVIE bit
   279        *
   280        *  @see #setACCVIE
   281        */
   282        Bool    setACCVIE(Bool set);
   283    
   284        /*!
   285        *  ======== getACCVIFG ========
   286        *  Gets ACCVIFG bit
   287        *
   288        *  @see #getACCVIFG
   289        */
   290        Bool    getACCVIFG();
   291    
   292       /*!
   293        *  ======== setACCVIFG ========
   294        *  Sets ACCVIFG bit
   295        *
   296        *  @see #setACCVIFG
   297        */
   298        Bool    setACCVIFG(Bool set);
   299    
   300        /*! Determine if each Register needs to be forced set or not */
   301        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   302        [
   303            { register : "IE1" , regForceSet : false },
   304            { register : "IFG1" , regForceSet : false },
   305        ];
   306    }