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32
33 /*!
34 * Universal Serial Communication Interface
35 */
36 metaonly interface IUSCI_I2C inherits IUSCI {
37
38
39
40
41
42 /*! Own addressing mode select */
43 enum UCA10_t {
44 UCA10_OFF = 0x00, /*! Own address is a 7-bit address */
45 UCA10 = 0x80 /*! Own address is a 10-bit address */
46 };
47
48 /*! Slave addressing mode select */
49 enum UCSLA10_t {
50 UCSLA10_OFF = 0x00, /*! Address slave with 7-bit address */
51 UCSLA10 = 0x40 /*! Address slave with 10-bit address */
52 };
53
54 /*! Multi-master environment select */
55 enum UCMM_t {
56 UCMM_OFF = 0x00, /*! Single master environment. There is no other master in the system. The address compare unit is disabled. */
57 UCMM = 0x20 /*! Multi master environment */
58 };
59
60 /*! Master mode select */
61 enum UCMST_t {
62 UCMST_OFF = 0x00, /*! Slave mode */
63 UCMST = 0x40 /*! Master mode */
64 };
65
66 /*! USCI clock source select. These bits select the BRCLK source clock. */
67 enum UCSSEL_I2C_t {
68 UCSSEL_0 = 0x00, /*! UCLK */
69 UCSSEL_1 = 0x01, /*! ACLK */
70 UCSSEL_2 = 0x02 /*! SMCLK */
71
72 };
73
74 /*! Transmitter/Receiver */
75 enum UCTR_t {
76 UCTR_OFF = 0x00, /*! Receiver */
77 UCTR = 0x10 /*! Transmitter */
78 };
79
80 /*! Transmit a NACK */
81 enum UCTXNACK_t {
82 UCTXNACK_OFF = 0x00, /*! Acknowledge normally */
83 UCTXNACK = 0x08 /*! Generate NACK */
84 };
85
86 /*! Transmit STOP condition in master mode */
87 enum UCTXSTP_t {
88 UCTXSTP_OFF = 0x00, /*! No STOP generated */
89 UCTXSTP = 0x10 /*! Generate STOP */
90 };
91
92 /*! Transmit START condition in master mode */
93 enum UCTXSTT_t {
94 UCTXSTT_OFF = 0x00, /*! Do not generate START condition */
95 UCTXSTT = 0x10 /*! Generate START condition */
96 };
97
98 /*! SCL low */
99 enum UCSCLLOW_t {
100 UCSCLLOW_OFF = 0x00, /*! SCL is not held low */
101 UCSCLLOW = 0x10 /*! SCL is held low */
102 };
103
104 /*! General call address received */
105 enum UCGC_t {
106 UCGC_OFF = 0x00, /*! No general call address received */
107 UCGC = 0x10 /*! General call address received */
108 };
109
110 /*! Bus busy */
111 enum UCBBUSY_t {
112 UCBBUSY_OFF = 0x00, /*! Bus inactive */
113 UCBBUSY = 0x10 /*! Bus busy */
114 };
115
116 /*! Not-acknowledge received interrupt flag */
117 enum UCNACKIFG_t {
118 UCNACKIFG_OFF = 0x00, /*! No interrupt pending */
119 UCNACKIFG = 0x10 /*! Interrupt pending */
120 };
121
122 /*! Stop condition interrupt flag */
123 enum UCSTPIFG_t {
124 UCSTPIFG_OFF = 0x00, /*! No interrupt pending */
125 UCSTPIFG = 0x10 /*! Interrupt pending */
126 };
127
128 /*! Start condition interrupt flag */
129 enum UCSTTIFG_t {
130 UCSTTIFG_OFF = 0x00, /*! No interrupt pending */
131 UCSTTIFG = 0x10 /*! Interrupt pending */
132 };
133
134 /*! Arbitration lost interrupt flag */
135 enum UCALIFG_t {
136 UCALIFG_OFF = 0x00, /*! No interrupt pending */
137 UCALIFG = 0x10 /*! Interrupt pending */
138 };
139
140 /*! General call response enable */
141 enum UCGCEN_t {
142 UCGCEN_OFF = 0x00, /*! Do not respond to a general call */
143 UCGCEN = 0x80 /*! Respond to a general call */
144 };
145
146 struct UCxCTL0_t {
147 UCA10_t UCA10; /*! Own addressing mode select
148 * 0 Own address is a 7-bit address
149 * 1 Own address is a 10-bit address */
150 UCSLA10_t UCSLA10; /*! Slave addressing mode select
151 * 0 Address slave with 7-bit address
152 * 1 Address slave with 10-bit address */
153 UCMM_t UCMM; /*! Multi-master environment select
154 * 0 Single master environment. There is no other master in the system.
155 * The address compare unit is disabled.
156 * 1 Multi master environment */
157 UCMST_t UCMST; /*! Master mode select. When a master looses arbitration in a multi-master
158 *environment (UCMM = 1) the UCMST bit is automatically cleared and the
159 *module acts as slave.
160 * 0 Slave mode
161 * 1 Master mode */
162 UCMODE_SYNC_t UCMODE; /*! USCI Mode. The UCMODEx bits select the synchronous mode when
163 *UCSYNC = 1.
164 * 00 3-pin SPI
165 * 01 4-pin SPI (master/slave enabled if STE = 1)
166 * 10 4-pin SPI (master/slave enabled if STE = 0)
167 * 11 I2C mode */
168 UCSYNC_t UCSYNC; /*! Synchronous mode enable
169 * 0 Asynchronous mode
170 * 1 Synchronous mode */
171 }
172
173 struct UCxCTL1_t {
174 UCSSEL_I2C_t UCSSEL; /*! USCI clock source select. These bits select the BRCLK source clock.
175 * 00 UCLKI
176 * 01 ACLK
177 * 10 SMCLK
178 * 11 SMCLK */
179 UCTR_t UCTR; /*! Transmitter/Receiver
180 * 0 Receiver
181 * 1 Transmitter */
182 UCTXNACK_t UCTXNACK; /*! Transmit a NACK. UCTXNACK is automatically cleared after a NACK is
183 *transmitted.
184 * 0 Acknowledge normally
185 * 1 Generate NACK */
186 UCTXSTP_t UCTXSTP; /*! Transmit STOP condition in master mode. Ignored in slave mode. In
187 *master receiver mode the STOP condition is preceded by a NACK.
188 *UCTXSTP is automatically cleared after STOP is generated.
189 * 0 No STOP generated
190 * 1 Generate STOP */
191 UCTXSTT_t UCTXSTT; /*! Transmit START condition in master mode. Ignored in slave mode. In
192 *master receiver mode a repeated START condition is preceded by a
193 *NACK. UCTXSTT is automatically cleared after START condition and
194 *address information is transmitted.
195 *Ignored in slave mode.
196 * 0 Do not generate START condition
197 * 1 Generate START condition */
198 UCSWRST_t UCSWRST; /*! Software reset enable
199 * 0 Disabled. USCI reset released for operation.
200 * 1 Enabled. USCI logic held in reset state. */
201 }
202
203 struct UCxSTAT_t {
204 UCSCLLOW_t UCSCLLOW; /*! SCL low
205 * 0 SCL is not held low
206 * 1 SCL is held low */
207 UCGC_t UCGC; /*! General call address received. UCGC is automatically cleared when a
208 *START condition is received.
209 * 0 No general call address received
210 * 1 General call address received */
211 UCBBUSY_t UCBBUSY; /*! Bus busy
212 * 0 Bus inactive
213 * 1 Bus busy */
214 UCNACKIFG_t UCNACKIFG; /*! Not-acknowledge received interrupt flag. UCNACKIFG is automatically
215 *cleared when a START condition is received.
216 * 0 No interrupt pending
217 * 1 Interrupt pending */
218 UCSTPIFG_t UCSTPIFG; /*! Stop condition interrupt flag. UCSTPIFG is automatically cleared when a
219 *START condition is received.
220 * 0 No interrupt pending
221 * 1 Interrupt pending */
222 UCSTTIFG_t UCSTTIFG; /*! Start condition interrupt flag. UCSTTIFG is automatically cleared if a STOP
223 *condition is received.
224 * 0 No interrupt pending
225 * 1 Interrupt pending */
226 UCALIFG_t UCALIFG; /*! Arbitration lost interrupt flag
227 * 0 No interrupt pending
228 * 1 Interrupt pending */
229 }
230
231 struct UCBxI2COA_t {
232 UCGCEN_t UCGCEN; /*! General call response enable
233 * 0 Do not respond to a general call
234 * 1 Respond to a general call */
235 Bits16 I2COA; /*! I2C own address. The I2COAx bits contain the local address of the USCI_Bx
236 *I2C controller. The address is right-justified. In 7-bit addressing mode Bit 6 is
237 *the MSB, Bits 9-7 are ignored. In 10-bit addressing mode Bit 9 is the MSB. */
238 }
239
240 instance:
241 /*!
242 * ======== getUCBxI2CSA ========
243 * Returns UCBxI2CSA register value based on which module
244 *
245 * @see #getUCBxI2CSA
246 */
247 Bits8 getUCBxI2CSA();
248
249 /*!
250 * ======== setUCBxI2CSA ========
251 * Sets UCxxI2CSA register value based on which module
252 *
253 * @see #setUCBxI2CSA
254 */
255 void setUCBxI2CSA(Bits8 value);
256 }