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32
33 34 35 36
37
38 package ti.catalog.c6000;
39
40 metaonly interface ITMS320TCI6608 inherits ti.catalog.ICpuDataSheet
41 {
42
43 config long cacheSizeL1[string] = [
44 ["0k", 0x0000],
45 ["4k", 0x1000],
46 ["8k", 0x2000],
47 ["16k", 0x4000],
48 ["32k", 0x8000],
49 ];
50
51 config long cacheSizeL2[string] = [
52 ["0k", 0x000000],
53 ["32k", 0x008000],
54 ["64k", 0x010000],
55 ["128k", 0x020000],
56 ["256k", 0x040000],
57 ["512k", 0x080000]
58 ];
59
60 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
61 ['l1PMode',{desc:"L1P Cache",
62 base: 0x00E00000,
63 map : [["0k",0x0000],
64 ["4k",0x1000],
65 ["8k",0x2000],
66 ["16k",0x4000],
67 ["32k",0x8000]],
68 defaultValue: "32k",
69 memorySection: "L1PSRAM"}],
70
71 ['l1DMode',{desc:"L1D Cache",
72 base: 0x00F00000,
73 map : [["0k",0x0000],
74 ["4k",0x1000],
75 ["8k",0x2000],
76 ["16k",0x4000],
77 ["32k",0x8000]],
78 defaultValue: "32k",
79 memorySection: "L1DSRAM"}],
80
81 ['l2Mode',{desc:"L2 Cache",
82 base: 0x00800000,
83 map : [["0k",0x0000],
84 ["32k",0x8000],
85 ["64k",0x10000],
86 ["128k", 0x020000],
87 ["256k", 0x040000],
88 ["512k", 0x080000]],
89 defaultValue: "0k",
90 memorySection: "L2SRAM"}],
91
92 ];
93
94 instance:
95
96 override config string cpuCore = "6600";
97 override config string isa = "66";
98 override config string cpuCoreRevision = "1.0";
99
100 override config int minProgUnitSize = 1;
101 override config int minDataUnitSize = 1;
102 override config int dataWordSize = 4;
103
104 /*!
105 * ======== memMap ========
106 * The default memory map for this device
107 */
108 config xdc.platform.IPlatform.Memory memMap[string] = [
109 ["L2SRAM", {
110 comment: "512KB L2 SRAM/CACHE",
111 name: "L2SRAM",
112 base: 0x00800000,
113 len: 0x00080000,
114 space: "code/data",
115 access: "RWX"
116 }],
117
118 ["L1PSRAM", {
119 comment: "32KB RAM/CACHE L1 program memory",
120 name: "L1PSRAM",
121 base: 0x00E00000,
122 len: 0x00008000,
123 space: "code",
124 access: "RWX"
125 }],
126
127 ["L1DSRAM", {
128 comment: "32KB RAM/CACHE L1 data memory",
129 name: "L1DSRAM",
130 base: 0x00F00000,
131 len: 0x00008000,
132 space: "data",
133 access: "RW"
134 }],
135
136 ["MSMCSRAM", {
137 comment: "4MB MSMC SRAM",
138 name: "MSMCSRAM",
139 base: 0x0C000000,
140 len: 0x00400000,
141 space: "code/data",
142 access: "RWX"
143 }],
144 ];
145 };