1    /*
     2     * Copyright (c) 2016, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    
    33    import ti.catalog.msp430.peripherals.clock.IClock;
    34    
    35    /*!
    36     *  ======== WDT+ ========
    37     *  MSP430 Watchdog Timer+
    38     */
    39    metaonly module WDTplus inherits IWDT
    40    {
    41        enum WDTPW_t {
    42            WDTPW_OFF = 0x0000,         /*! no Watchdog password value */
    43            WDTPW     = 0x5A00          /*! Watchdog password */
    44        };
    45    
    46        enum WDTHOLD_t {
    47            WDTHOLD_OFF = 0x0000,       /*! Watchdog timer+ is not stopped */
    48            WDTHOLD     = 0x0080        /*! Watchdog timer+ is stopped */
    49        };
    50    
    51        enum WDTNMIES_t {
    52            WDTNMIES_OFF = 0x0000,      /*! NMI on rising edge */
    53            WDTNMIES     = 0x0040       /*! NMI on falling edge */
    54        };
    55    
    56        enum WDTNMI_t {
    57            WDTNMI_OFF = 0x0000,        /*! Reset function */
    58            WDTNMI     = 0x0020         /*! NMI function */
    59        };
    60    
    61        enum WDTTMSEL_t {
    62            WDTTMSEL_OFF = 0x0000,      /*! Watchdog mode */
    63            WDTTMSEL     = 0x0010       /*! Interval timer mode */
    64        };
    65    
    66        enum WDTCNTCL_t {
    67            WDTCNTCL_OFF = 0x0000,      /*! No action */
    68            WDTCNTCL     = 0x0008       /*! WDTCNT = 0000h */
    69        };
    70    
    71        enum WDTSSEL_t {
    72            WDTSSEL_OFF = 0x0000,       /*! SMCLK */
    73            WDTSSEL     = 0x0004        /*! ACLK */
    74        };
    75    
    76        enum WDTIS1_t {
    77            WDTIS1_OFF = 0x0000,        /*! Watchdog clock source bit1 disabled */
    78            WDTIS1     = 0x0002         /*! Watchdog clock source bit1 enabled */
    79        };
    80    
    81        enum WDTIS0_t {
    82            WDTIS0_OFF = 0x0000,        /*! Watchdog clock source bit0 disabled */
    83            WDTIS0     = 0x0001         /*! Watchdog clock source bit0 enabled */
    84        };
    85    
    86        /* WDTCTL Register */
    87        struct WDTCTL_t {
    88            WDTPW_t     WDTPW;          /*! WDT+ password */
    89            WDTHOLD_t   WDTHOLD;        /*! Watchdog timer+ hold. This bit stops the watchdog timer+. Setting
    90                                         *WDTHOLD = 1 when the WDT+ is not in use conserves power.
    91                                         *  0    Watchdog timer+ is not stopped
    92                                         *  1    Watchdog timer+ is stopped
    93                                         */
    94            WDTNMIES_t  WDTNMIES;       /*! Watchdog timer+ NMI edge select. This bit selects the interrupt edge for the
    95                                         *NMI interrupt when WDTNMI = 1. Modifying this bit can trigger an NMI. Modify
    96                                         *this bit when WDTIE = 0 to avoid triggering an accidental NMI.
    97                                         *  0    NMI on rising edge
    98                                         *  1    NMI on falling edge
    99                                         */
   100            WDTNMI_t    WDTNMI;         /*! Watchdog timer+ NMI select. This bit selects the function for the RST/NMI pin.
   101                                         *  0    Reset function
   102                                         *  1    NMI function
   103                                         */
   104            WDTTMSEL_t  WDTTMSEL;       /*! Watchdog timer+ mode select
   105                                         *  0    Watchdog mode
   106                                         *  1    Interval timer mode
   107                                         */
   108            WDTCNTCL_t  WDTCNTCL;       /*! Watchdog timer+ counter clear. Setting WDTCNTCL = 1 clears the count
   109                                         *value to 0000h. WDTCNTCL is automatically reset.
   110                                         *  0    No action
   111                                         *  1    WDTCNT = 0000h
   112                                         */
   113            WDTSSEL_t   WDTSSEL;        /*! Watchdog timer+ clock source select
   114                                         *  0    SMCLK
   115                                         *  1    ACLK
   116                                         */
   117            WDTIS0_t    WDTIS0;         /*! Watchdog timer+ interval select. These bits select the watchdog timer+
   118                                         *interval to set the WDTIFG flag and/or generate a PUC.
   119                                         *  00   Watchdog clock source /32768
   120                                         *  01   Watchdog clock source /8192
   121                                         *  10   Watchdog clock source /512
   122                                         *  11   Watchdog clock source /64
   123                                         */
   124            WDTIS1_t    WDTIS1;          /*! Watchdog timer+ interval select. These bits select the watchdog timer+
   125                                          *interval to set the WDTIFG flag and/or generate a PUC.
   126                                          *  00   Watchdog clock source /32768
   127                                          *  01   Watchdog clock source /8192
   128                                          *  10   Watchdog clock source /512
   129                                          *  11   Watchdog clock source /64
   130                                          */
   131        }
   132    
   133        create(IClock.Instance clock);
   134    
   135    instance:
   136        /*! WDTCTL, Watchdog Timer+ Register */
   137        config WDTCTL_t WDTCTL = {
   138            WDTPW       : WDTPW,
   139            WDTHOLD     : WDTHOLD_OFF,
   140            WDTNMIES    : WDTNMIES_OFF,
   141            WDTNMI      : WDTNMI_OFF,
   142            WDTTMSEL    : WDTTMSEL_OFF,
   143            WDTCNTCL    : WDTCNTCL_OFF,
   144            WDTSSEL     : WDTSSEL_OFF,
   145            WDTIS0      : WDTIS0_OFF,
   146            WDTIS1      : WDTIS1_OFF,
   147        };
   148    
   149        /*! Determine if each Register needs to be forced set or not */
   150        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   151        [
   152            { register : "WDTCTL" , regForceSet : true }
   153        ];
   154    
   155        /*!
   156         *  ======== baseAddr ========
   157         *  Address of the peripheral's control register.
   158         *
   159         *  A peripheral's registers are commonly accessed through a structure
   160         *  that defines the offsets of a particular register from the lowest
   161         *  address mapped to a peripheral. That lowest address is specified by
   162         *  this parameter.
   163         */
   164        config UInt baseAddr;
   165    
   166        /*! @_nodoc */
   167        config IClock.Instance clock;
   168    }