1    /*
     2     *  Copyright (c) 2014 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== DRA7XX.xdc ========
    15     *
    16     */
    17    
    18    package ti.catalog.c6000;
    19    
    20    /*!
    21     *  ======== DRA7XX ========
    22     *  The DRA7XX device data sheet module.
    23     *
    24     *  This module implements the ICpuDataSheet interface and is
    25     *  used by platforms to obtain "data sheet" information about this device.
    26     */ 
    27    metaonly module DRA7XX inherits ti.catalog.ICpuDataSheet
    28    {
    29    
    30        config long cacheSizeL1[string] = [
    31            ["0k",  0x0000],
    32            ["4k",  0x1000],
    33            ["8k",  0x2000],
    34            ["16k", 0x4000],
    35            ["32k", 0x8000]
    36        ];
    37    
    38        config long cacheSizeL2[string] = [
    39            ["0k",    0x000000],
    40            ["32k",   0x008000],
    41            ["64k",   0x010000],
    42            ["128k",  0x020000],
    43            ["256k",  0x040000]
    44        ];
    45    
    46        readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    47                 ['l1PMode',{desc:"L1P Cache",
    48                             base: 0x00E00000,
    49                             map : [["0k" ,0x0000],
    50                                    ["4k" ,0x1000],
    51                                    ["8k" ,0x2000],
    52                                    ["16k",0x4000],
    53                                    ["32k",0x8000]],
    54                             defaultValue: "32k",
    55                             memorySection: "L1PSRAM"}],
    56    
    57                 ['l1DMode',{desc:"L1D Cache",
    58                             base: 0x00F00000,
    59                             map : [["0k"  ,0x0000],
    60                                    ["4k"  ,0x1000],
    61                                    ["8k"  ,0x2000],
    62                                    ["16k" ,0x4000],
    63                                    ["32k" ,0x8000]],
    64                             defaultValue: "32k",
    65                             memorySection: "L1DSRAM"}],
    66    
    67                 ['l2Mode',{desc:"L2 Cache",
    68                             base: 0x00800000,
    69                             map : [["0k"   ,0x0000],
    70                                    ["32k"  ,0x8000],
    71                                    ["64k"  ,0x10000],
    72                                ["128k" ,0x020000],
    73                                    ["256k" ,0x040000]],
    74                             defaultValue: "0k",
    75                             memorySection: "L2SRAM"}],
    76    
    77        ];
    78    
    79    instance:
    80        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
    81        override config string   cpuCore        = "6600";
    82        override config string   isa = "66";
    83        override config string   cpuCoreRevision = "1.0";
    84    
    85        override config int     minProgUnitSize = 1;
    86        override config int     minDataUnitSize = 1;
    87        override config int     dataWordSize    = 4;
    88    
    89        /*!
    90         *  ======== memMap ========
    91         *  The default memory map for this device
    92         */
    93        config xdc.platform.IPlatform.Memory memMap[string]  = [
    94            ["L2SRAM", {
    95                comment:    "256KB L2 SRAM/CACHE",
    96                name:       "L2SRAM",
    97                base:       0x00800000,
    98                len:        0x00040000,
    99                space:      "code/data",
   100                access:     "RWX"
   101            }],
   102    
   103            ["L1PSRAM", {
   104                comment:    "32KB RAM/CACHE L1 program memory",
   105                name:       "L1PSRAM",
   106                base:       0x00E00000,
   107                len:        0x00008000,
   108                space:      "code",
   109                access:     "RWX"
   110            }],
   111    
   112            ["L1DSRAM", {
   113                comment:    "32KB RAM/CACHE L1 data memory",
   114                name:       "L1DSRAM",
   115                base:       0x00F00000,
   116                len:        0x00008000,
   117                space:      "data",
   118                access:     "RW"
   119            }],
   120    
   121            ["OCMC_RAM1", {
   122                comment:    "OCMC (On-chip RAM) Bank 1 (512KB)",
   123                name:       "OCMC_RAM1",
   124                base:       0x40300000,
   125                len:        0x00080000,
   126                space:      "code/data",
   127                access:     "RWX"
   128            }],
   129    
   130            ["OCMC_RAM2", {
   131                comment:    "OCMC (On-chip RAM) Bank 2 (1MB)",
   132                name:       "OCMC_RAM2",
   133                base:       0x40400000,
   134                len:        0x00100000,
   135                space:      "code/data",
   136                access:     "RWX"
   137            }],
   138    
   139            ["OCMC_RAM3", {
   140                comment:    "OCMC (On-chip RAM) Bank 3 (1MB)",
   141                name:       "OCMC_RAM3",
   142                base:       0x40500000,
   143                len:        0x00100000,
   144                space:      "code/data",
   145                access:     "RWX"
   146            }],
   147        ];
   148    };
   149    /*
   150     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,459; 5-29-2014 17:13:26; /db/ztree/library/trees/platform/platform-o51x/src/
   151     */
   152