1    /*
     2     * Copyright (c) 2012, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     * */
    32    /*
    33     *  ======== Boot.xdc ========
    34     */
    35    
    36    package ti.catalog.arm.cortexm3.lm3init;
    37    
    38    import xdc.rov.ViewInfo;
    39    
    40    /*!
    41     *  ======== Boot ========
    42     *  Stellaris M3 Boot Support.
    43     *
    44     *  The Boot module supports boot initialization for the Stellaris M3 devices.
    45     *  A special boot init function is created based on the configuration
    46     *  settings for this module.  This function is hooked into the
    47     *  xdc.runtime.Reset.fxns[] array and called very early at boot time (prior
    48     *  to cinit processing).
    49     *
    50     *  The code to support the boot module is placed in a separate section
    51     *  named `".text:.bootCodeSection"` to allow placement of this section in
    52     *  the linker .cmd file if necessary. This section is a subsection of the
    53     *  `".text"` section so this code will be placed into the .text section unless
    54     *  explicitly placed, either through
    55     *  `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
    56     *  command file.
    57     */
    58    @Template("./Boot.xdt")
    59    @NoRuntime
    60    module Boot
    61    {
    62        metaonly struct ModuleView {
    63            Bool    configureClock;
    64            Bool    sysClockDivEnable;
    65            String  sysClockDiv;
    66            Bool    pwmClockDivEnable;
    67            String  pwmClockDiv;
    68            String  xtal;
    69            String  oscSrc;
    70            Bool    pllBypass;
    71            Bool    pllOutEnable;
    72            Bool    ioscDisable;
    73            Bool    moscDisable;
    74            Bool    configureLdo;
    75            String  ldoOut;
    76        }
    77    
    78        @Facet
    79        metaonly config ViewInfo.Instance rovViewInfo =
    80            ViewInfo.create({
    81                viewMap: [
    82                [
    83                    'Module',
    84                    {
    85                        type: ViewInfo.MODULE,
    86                        viewInitFxn: 'viewInitModule',
    87                        structName: 'ModuleView'
    88                    }
    89                ],
    90                ]
    91            });
    92    
    93    
    94        enum SysDiv {
    95            SYSDIV_1     = 0x07800000,  /*! CPU clock is osc/pll / 1 */
    96            SYSDIV_2     = 0x00C00000,  /*! CPU clock is osc/pll / 2 */
    97            SYSDIV_3     = 0x01400000,  /*! CPU clock is osc/pll / 3 */
    98            SYSDIV_4     = 0x01C00000,  /*! CPU clock is osc/pll / 4 */
    99            SYSDIV_5     = 0x02400000,  /*! CPU clock is osc/pll / 5 */
   100            SYSDIV_6     = 0x02C00000,  /*! CPU clock is osc/pll / 6 */
   101            SYSDIV_7     = 0x03400000,  /*! CPU clock is osc/pll / 7 */
   102            SYSDIV_8     = 0x03C00000,  /*! CPU clock is osc/pll / 8 */
   103            SYSDIV_9     = 0x04400000,  /*! CPU clock is osc/pll / 9 */
   104            SYSDIV_10    = 0x04C00000,  /*! CPU clock is osc/pll / 10 */
   105            SYSDIV_11    = 0x05400000,  /*! CPU clock is osc/pll / 11 */
   106            SYSDIV_12    = 0x05C00000,  /*! CPU clock is osc/pll / 12 */
   107            SYSDIV_13    = 0x06400000,  /*! CPU clock is osc/pll / 13 */
   108            SYSDIV_14    = 0x06C00000,  /*! CPU clock is osc/pll / 14 */
   109            SYSDIV_15    = 0x07400000,  /*! CPU clock is osc/pll / 15 */
   110            SYSDIV_16    = 0x07C00000,  /*! CPU clock is osc/pll / 16 */
   111            SYSDIV_17    = 0x88400000,  /*! CPU clock is osc/pll / 17 */
   112            SYSDIV_18    = 0x88C00000,  /*! CPU clock is osc/pll / 18 */
   113            SYSDIV_19    = 0x89400000,  /*! CPU clock is osc/pll / 19 */
   114            SYSDIV_20    = 0x89C00000,  /*! CPU clock is osc/pll / 20 */
   115            SYSDIV_21    = 0x8A400000,  /*! CPU clock is osc/pll / 21 */
   116            SYSDIV_22    = 0x8AC00000,  /*! CPU clock is osc/pll / 22 */
   117            SYSDIV_23    = 0x8B400000,  /*! CPU clock is osc/pll / 23 */
   118            SYSDIV_24    = 0x8BC00000,  /*! CPU clock is osc/pll / 24 */
   119            SYSDIV_25    = 0x8C400000,  /*! CPU clock is osc/pll / 25 */
   120            SYSDIV_26    = 0x8CC00000,  /*! CPU clock is osc/pll / 26 */
   121            SYSDIV_27    = 0x8D400000,  /*! CPU clock is osc/pll / 27 */
   122            SYSDIV_28    = 0x8DC00000,  /*! CPU clock is osc/pll / 28 */
   123            SYSDIV_29    = 0x8E400000,  /*! CPU clock is osc/pll / 29 */
   124            SYSDIV_30    = 0x8EC00000,  /*! CPU clock is osc/pll / 30 */
   125            SYSDIV_31    = 0x8F400000,  /*! CPU clock is osc/pll / 31 */
   126            SYSDIV_32    = 0x8FC00000,  /*! CPU clock is osc/pll / 32 */
   127            SYSDIV_33    = 0x90400000,  /*! CPU clock is osc/pll / 33 */
   128            SYSDIV_34    = 0x90C00000,  /*! CPU clock is osc/pll / 34 */
   129            SYSDIV_35    = 0x91400000,  /*! CPU clock is osc/pll / 35 */
   130            SYSDIV_36    = 0x91C00000,  /*! CPU clock is osc/pll / 36 */
   131            SYSDIV_37    = 0x92400000,  /*! CPU clock is osc/pll / 37 */
   132            SYSDIV_38    = 0x92C00000,  /*! CPU clock is osc/pll / 38 */
   133            SYSDIV_39    = 0x93400000,  /*! CPU clock is osc/pll / 39 */
   134            SYSDIV_40    = 0x93C00000,  /*! CPU clock is osc/pll / 40 */
   135            SYSDIV_41    = 0x94400000,  /*! CPU clock is osc/pll / 41 */
   136            SYSDIV_42    = 0x94C00000,  /*! CPU clock is osc/pll / 42 */
   137            SYSDIV_43    = 0x95400000,  /*! CPU clock is osc/pll / 43 */
   138            SYSDIV_44    = 0x95C00000,  /*! CPU clock is osc/pll / 44 */
   139            SYSDIV_45    = 0x96400000,  /*! CPU clock is osc/pll / 45 */
   140            SYSDIV_46    = 0x96C00000,  /*! CPU clock is osc/pll / 46 */
   141            SYSDIV_47    = 0x97400000,  /*! CPU clock is osc/pll / 47 */
   142            SYSDIV_48    = 0x97C00000,  /*! CPU clock is osc/pll / 48 */
   143            SYSDIV_49    = 0x98400000,  /*! CPU clock is osc/pll / 49 */
   144            SYSDIV_50    = 0x98C00000,  /*! CPU clock is osc/pll / 50 */
   145            SYSDIV_51    = 0x99400000,  /*! CPU clock is osc/pll / 51 */
   146            SYSDIV_52    = 0x99C00000,  /*! CPU clock is osc/pll / 52 */
   147            SYSDIV_53    = 0x9A400000,  /*! CPU clock is osc/pll / 53 */
   148            SYSDIV_54    = 0x9AC00000,  /*! CPU clock is osc/pll / 54 */
   149            SYSDIV_55    = 0x9B400000,  /*! CPU clock is osc/pll / 55 */
   150            SYSDIV_56    = 0x9BC00000,  /*! CPU clock is osc/pll / 56 */
   151            SYSDIV_57    = 0x9C400000,  /*! CPU clock is osc/pll / 57 */
   152            SYSDIV_58    = 0x9CC00000,  /*! CPU clock is osc/pll / 58 */
   153            SYSDIV_59    = 0x9D400000,  /*! CPU clock is osc/pll / 59 */
   154            SYSDIV_60    = 0x9DC00000,  /*! CPU clock is osc/pll / 60 */
   155            SYSDIV_61    = 0x9E400000,  /*! CPU clock is osc/pll / 61 */
   156            SYSDIV_62    = 0x9EC00000,  /*! CPU clock is osc/pll / 62 */
   157            SYSDIV_63    = 0x9F400000,  /*! CPU clock is osc/pll / 63 */
   158            SYSDIV_64    = 0x9FC00000,  /*! CPU clock is osc/pll / 64 */
   159            SYSDIV_2_5   = 0xC1000000,  /*! CPU clock is osc/pll / 2.5 */
   160            SYSDIV_3_5   = 0xC1800000,  /*! CPU clock is osc/pll / 3.5 */
   161            SYSDIV_4_5   = 0xC2000000,  /*! CPU clock is osc/pll / 4.5 */
   162            SYSDIV_5_5   = 0xC2800000,  /*! CPU clock is osc/pll / 5.5 */
   163            SYSDIV_6_5   = 0xC3000000,  /*! CPU clock is osc/pll / 6.5 */
   164            SYSDIV_7_5   = 0xC3800000,  /*! CPU clock is osc/pll / 7.5 */
   165            SYSDIV_8_5   = 0xC4000000,  /*! CPU clock is osc/pll / 8.5 */
   166            SYSDIV_9_5   = 0xC4800000,  /*! CPU clock is osc/pll / 9.5 */
   167            SYSDIV_10_5  = 0xC5000000,  /*! CPU clock is osc/pll / 10.5 */
   168            SYSDIV_11_5  = 0xC5800000,  /*! CPU clock is osc/pll / 11.5 */
   169            SYSDIV_12_5  = 0xC6000000,  /*! CPU clock is osc/pll / 12.5 */
   170            SYSDIV_13_5  = 0xC6800000,  /*! CPU clock is osc/pll / 13.5 */
   171            SYSDIV_14_5  = 0xC7000000,  /*! CPU clock is osc/pll / 14.5 */
   172            SYSDIV_15_5  = 0xC7800000,  /*! CPU clock is osc/pll / 15.5 */
   173            SYSDIV_16_5  = 0xC8000000,  /*! CPU clock is osc/pll / 16.5 */
   174            SYSDIV_17_5  = 0xC8800000,  /*! CPU clock is osc/pll / 17.5 */
   175            SYSDIV_18_5  = 0xC9000000,  /*! CPU clock is osc/pll / 18.5 */
   176            SYSDIV_19_5  = 0xC9800000,  /*! CPU clock is osc/pll / 19.5 */
   177            SYSDIV_20_5  = 0xCA000000,  /*! CPU clock is osc/pll / 20.5 */
   178            SYSDIV_21_5  = 0xCA800000,  /*! CPU clock is osc/pll / 21.5 */
   179            SYSDIV_22_5  = 0xCB000000,  /*! CPU clock is osc/pll / 22.5 */
   180            SYSDIV_23_5  = 0xCB800000,  /*! CPU clock is osc/pll / 23.5 */
   181            SYSDIV_24_5  = 0xCC000000,  /*! CPU clock is osc/pll / 24.5 */
   182            SYSDIV_25_5  = 0xCC800000,  /*! CPU clock is osc/pll / 25.5 */
   183            SYSDIV_26_5  = 0xCD000000,  /*! CPU clock is osc/pll / 26.5 */
   184            SYSDIV_27_5  = 0xCD800000,  /*! CPU clock is osc/pll / 27.5 */
   185            SYSDIV_28_5  = 0xCE000000,  /*! CPU clock is osc/pll / 28.5 */
   186            SYSDIV_29_5  = 0xCE800000,  /*! CPU clock is osc/pll / 29.5 */
   187            SYSDIV_30_5  = 0xCF000000,  /*! CPU clock is osc/pll / 30.5 */
   188            SYSDIV_31_5  = 0xCF800000,  /*! CPU clock is osc/pll / 31.5 */
   189            SYSDIV_32_5  = 0xD0000000,  /*! CPU clock is osc/pll / 32.5 */
   190            SYSDIV_33_5  = 0xD0800000,  /*! CPU clock is osc/pll / 33.5 */
   191            SYSDIV_34_5  = 0xD1000000,  /*! CPU clock is osc/pll / 34.5 */
   192            SYSDIV_35_5  = 0xD1800000,  /*! CPU clock is osc/pll / 35.5 */
   193            SYSDIV_36_5  = 0xD2000000,  /*! CPU clock is osc/pll / 36.5 */
   194            SYSDIV_37_5  = 0xD2800000,  /*! CPU clock is osc/pll / 37.5 */
   195            SYSDIV_38_5  = 0xD3000000,  /*! CPU clock is osc/pll / 38.5 */
   196            SYSDIV_39_5  = 0xD3800000,  /*! CPU clock is osc/pll / 39.5 */
   197            SYSDIV_40_5  = 0xD4000000,  /*! CPU clock is osc/pll / 40.5 */
   198            SYSDIV_41_5  = 0xD4800000,  /*! CPU clock is osc/pll / 41.5 */
   199            SYSDIV_42_5  = 0xD5000000,  /*! CPU clock is osc/pll / 42.5 */
   200            SYSDIV_43_5  = 0xD5800000,  /*! CPU clock is osc/pll / 43.5 */
   201            SYSDIV_44_5  = 0xD6000000,  /*! CPU clock is osc/pll / 44.5 */
   202            SYSDIV_45_5  = 0xD6800000,  /*! CPU clock is osc/pll / 45.5 */
   203            SYSDIV_46_5  = 0xD7000000,  /*! CPU clock is osc/pll / 46.5 */
   204            SYSDIV_47_5  = 0xD7800000,  /*! CPU clock is osc/pll / 47.5 */
   205            SYSDIV_48_5  = 0xD8000000,  /*! CPU clock is osc/pll / 48.5 */
   206            SYSDIV_49_5  = 0xD8800000,  /*! CPU clock is osc/pll / 49.5 */
   207            SYSDIV_50_5  = 0xD9000000,  /*! CPU clock is osc/pll / 50.5 */
   208            SYSDIV_51_5  = 0xD9800000,  /*! CPU clock is osc/pll / 51.5 */
   209            SYSDIV_52_5  = 0xDA000000,  /*! CPU clock is osc/pll / 52.5 */
   210            SYSDIV_53_5  = 0xDA800000,  /*! CPU clock is osc/pll / 53.5 */
   211            SYSDIV_54_5  = 0xDB000000,  /*! CPU clock is osc/pll / 54.5 */
   212            SYSDIV_55_5  = 0xDB800000,  /*! CPU clock is osc/pll / 55.5 */
   213            SYSDIV_56_5  = 0xDC000000,  /*! CPU clock is osc/pll / 56.5 */
   214            SYSDIV_57_5  = 0xDC800000,  /*! CPU clock is osc/pll / 57.5 */
   215            SYSDIV_58_5  = 0xDD000000,  /*! CPU clock is osc/pll / 58.5 */
   216            SYSDIV_59_5  = 0xDD800000,  /*! CPU clock is osc/pll / 59.5 */
   217            SYSDIV_60_5  = 0xDE000000,  /*! CPU clock is osc/pll / 60.5 */
   218            SYSDIV_61_5  = 0xDE800000,  /*! CPU clock is osc/pll / 61.5 */
   219            SYSDIV_62_5  = 0xDF000000,  /*! CPU clock is osc/pll / 62.5 */
   220            SYSDIV_63_5  = 0xDF800000   /*! CPU clock is osc/pll / 63.5 */
   221        }
   222    
   223        enum PwmDiv {
   224            PWMDIV_1     = 0x00000000,  /*! PWM clock /1 */
   225            PWMDIV_2     = 0x00100000,  /*! PWM clock /2 */
   226            PWMDIV_4     = 0x00120000,  /*! PWM clock /4 */
   227            PWMDIV_8     = 0x00140000,  /*! PWM clock /8 */
   228            PWMDIV_16    = 0x00160000,  /*! PWM clock /16 */
   229            PWMDIV_32    = 0x00180000,  /*! PWM clock /32 */
   230            PWMDIV_64    = 0x001A0000   /*! PWM clock /64 */
   231        }
   232    
   233        enum XtalFreq {
   234            XTAL_1MHZ    = 0x00000000,  /*! Using a 1MHz crystal */
   235            XTAL_1_84MHZ = 0x00000040,  /*! Using a 1.8432MHz crystal */
   236            XTAL_2MHZ    = 0x00000080,  /*! Using a 2MHz crystal */
   237            XTAL_2_45MHZ = 0x000000C0,  /*! Using a 2.4576MHz crystal */
   238            XTAL_3_57MHZ = 0x00000100,  /*! Using a 3.579545MHz crystal */
   239            XTAL_3_68MHZ = 0x00000140,  /*! Using a 3.6864MHz crystal */
   240            XTAL_4MHZ    = 0x00000180,  /*! Using a 4MHz crystal */
   241            XTAL_4_09MHZ = 0x000001C0,  /*! Using a 4.096MHz crystal */
   242            XTAL_4_91MHZ = 0x00000200,  /*! Using a 4.9152MHz crystal */
   243            XTAL_5MHZ    = 0x00000240,  /*! Using a 5MHz crystal */
   244            XTAL_5_12MHZ = 0x00000280,  /*! Using a 5.12MHz crystal */
   245            XTAL_6MHZ    = 0x000002C0,  /*! Using a 6MHz crystal */
   246            XTAL_6_14MHZ = 0x00000300,  /*! Using a 6.144MHz crystal */
   247            XTAL_7_37MHZ = 0x00000340,  /*! Using a 7.3728MHz crystal */
   248            XTAL_8MHZ    = 0x00000380,  /*! Using a 8MHz crystal */
   249            XTAL_8_19MHZ = 0x000003C0,  /*! Using a 8.192MHz crystal */
   250            XTAL_10MHZ   = 0x00000400,  /*! 10.0 MHz (USB) */
   251            XTAL_12MHZ   = 0x00000440,  /*! 12.0 MHz (USB) */
   252            XTAL_12_2MHZ = 0x00000480,  /*! 12.288 MHz */
   253            XTAL_13_5MHZ = 0x000004C0,  /*! 13.56 MHz */
   254            XTAL_14_3MHZ = 0x00000500,  /*! 14.31818 MHz */
   255            XTAL_16MHZ   = 0x00000540,  /*! 16.0 MHz (USB) */
   256            XTAL_16_3MHZ = 0x00000580   /*! 16.384 MHz */
   257        }
   258    
   259        enum OscSrc {
   260            OSCSRC_MAIN  = 0x00000000,  /*! Use the main oscillator */
   261            OSCSRC_INT   = 0x00000010,  /*! Use the internal oscillator */
   262            OSCSRC_INT4  = 0x00000020,  /*! Use the internal oscillator / 4 */
   263            OSCSRC_30    = 0x00000030   /*! 30 KHz internal oscillator */
   264        }
   265    
   266        enum LdoOut {
   267            LDOPCTL_2_55V    = 0x0000001F,  /*! LDO output of 2.55V */
   268            LDOPCTL_2_60V    = 0x0000001E,  /*! LDO output of 2.60V */
   269            LDOPCTL_2_65V    = 0x0000001D,  /*! LDO output of 2.65V */
   270            LDOPCTL_2_70V    = 0x0000001C,  /*! LDO output of 2.70V */
   271            LDOPCTL_2_75V    = 0x0000001B,  /*! LDO output of 2.75V */
   272            LDOPCTL_2_25V    = 0x00000005,  /*! LDO output of 2.25V */
   273            LDOPCTL_2_30V    = 0x00000004,  /*! LDO output of 2.30V */
   274            LDOPCTL_2_35V    = 0x00000003,  /*! LDO output of 2.35V */
   275            LDOPCTL_2_40V    = 0x00000002,  /*! LDO output of 2.40V */
   276            LDOPCTL_2_45V    = 0x00000001,  /*! LDO output of 2.45V */
   277            LDOPCTL_2_50V    = 0x00000000   /*! LDO output of 2.50V */
   278        }
   279    
   280        /*!
   281         *  Clock configuration flag, default is false.
   282         *
   283         *  Set to true to automatically configure the Clock.
   284         */
   285        config Bool configureClock = false;
   286    
   287        /*! SYS Clock Divisor */
   288        config SysDiv sysClockDiv = SYSDIV_1;
   289    
   290        /*! PWM Clock Divisor */
   291        config PwmDiv pwmClockDiv = PWMDIV_1;
   292    
   293        /*! Crystal Value */
   294        config XtalFreq xtal = XTAL_1MHZ;
   295    
   296        /*! Oscillator Source */
   297        config OscSrc oscSrc = OSCSRC_MAIN;
   298    
   299        /*! PLL Bypass flag */
   300        config Bool pllBypass = false;
   301    
   302        /*! PLL Output Enable flag */
   303        config Bool pllOutEnable = false;
   304    
   305        /*! Internal Oscillator Disable flag */
   306        config Bool ioscDisable = false;
   307    
   308        /*! Main Oscillator Disable flag */
   309        config Bool moscDisable = false;
   310    
   311        /*!
   312         *  LDO configuration flag, default is false.
   313         *
   314         *  Set to true to automatically configure the LDO.
   315         */
   316        config Bool configureLdo = false;
   317    
   318        /*!
   319         *  LDO VADJ setting, default is 2.5V
   320         */
   321        config LdoOut ldoOut = LDOPCTL_2_50V;
   322    
   323        /*!
   324         *  @_nodoc
   325         *  computed RCC value based on settings
   326         */
   327        config UInt ulConfig;
   328    
   329        /*!
   330         *  @_nodoc
   331         *  ======== getFrequency ========
   332         *  Gets the resulting output frequency (in Hz) given the Clock
   333         *  configuration parameters.
   334         *
   335         *  Currently un-implemented.
   336         */
   337        UInt32 getFrequency();
   338    
   339        /*!
   340         *  @_nodoc
   341         *  ======== registerFreqListener ========
   342         *  Register a module to be notified whenever the frequency changes.
   343         *
   344         *  The registered module must have a function named 'fireFrequencyUpdate'
   345         *  which takes the new frequency as an argument.
   346         */
   347        function registerFreqListener();
   348    
   349    internal:
   350    
   351        /*!
   352         *  @_nodoc
   353         *  computed cpu frequency based on clock settings
   354         */
   355        config UInt cpuFreq;
   356    
   357    };