1    /* --COPYRIGHT--,EPL
     2     *  Copyright (c) 2008 Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * --/COPYRIGHT--*/
    12    /*!
    13     *  ======== ADC12 ========
    14     *  MSP430 12-bit Analog to Digital Converter
    15     */
    16    metaonly module ADC12 inherits IADC {
    17    
    18        /*! SHT1 Bits */
    19        enum ADC12SHT1_t {
    20            SHT1_0  = (0*0x1000u), /*! 4 ADC12CLK cycles */
    21            SHT1_1  = (1*0x1000u), /*! 8 ADC12CLK cycles */
    22            SHT1_2  = (2*0x1000u), /*! 16 ADC12CLK cycles */
    23            SHT1_3  = (3*0x1000u), /*! 32 ADC12CLK cycles */
    24            SHT1_4  = (4*0x1000u), /*! 64 ADC12CLK cycles */
    25            SHT1_5  = (5*0x1000u), /*! 96 ADC12CLK cycles */
    26            SHT1_6  = (6*0x1000u), /*! 128 ADC12CLK cycles */
    27            SHT1_7  = (7*0x1000u), /*! 192 ADC12CLK cycles */
    28            SHT1_8  = (8*0x1000u), /*! 256 ADC12CLK cycles */
    29            SHT1_9  = (9*0x1000u), /*! 384 ADC12CLK cycles */
    30            SHT1_10 = (10*0x1000u), /*! 512  ADC12CLK cycles */
    31            SHT1_11 = (11*0x1000u), /*! 768 ADC12CLK cycles */
    32            SHT1_12 = 12*0x1000u    /*! 1024 ADC12CLK cycles */
    33        };
    34    
    35        /*! SHT0 Bits */
    36        enum ADC12SHT0_t {
    37            SHT0_0  = (0*0x1000u), /*! 4 ADC12CLK cycles */
    38            SHT0_1  = (1*0x1000u), /*! 8 ADC12CLK cycles */
    39            SHT0_2  = (2*0x1000u), /*! 16 ADC12CLK cycles */
    40            SHT0_3  = (3*0x1000u), /*! 32 ADC12CLK cycles */
    41            SHT0_4  = (4*0x1000u), /*! 64 ADC12CLK cycles */
    42            SHT0_5  = (5*0x1000u), /*! 96 ADC12CLK cycles */
    43            SHT0_6  = (6*0x1000u), /*! 128 ADC12CLK cycles */
    44            SHT0_7  = (7*0x1000u), /*! 192 ADC12CLK cycles */
    45            SHT0_8  = (8*0x1000u), /*! 256 ADC12CLK cycles */
    46            SHT0_9  = (9*0x1000u), /*! 384 ADC12CLK cycles */
    47            SHT0_10 = (10*0x1000u), /*! 512  ADC12CLK cycles */
    48            SHT0_11 = (11*0x1000u), /*! 768 ADC12CLK cycles */
    49            SHT0_12 = 12*0x1000u    /*! 1024 ADC12CLK cycles */
    50        };
    51    
    52        /*! MSC Bit */
    53        enum MSC_t {
    54            MSC_OFF = 0x000,       /*! The sampling timer requires a rising edge of the SHI
    55                                    *  signal to trigger each sample-and-conversion */
    56            MSC     = 0x080        /*! The first rising edge of the SHI signal triggers
    57                                    *  the sampling timer, but further sample-and-conversions
    58                                    *  are performed automatically as soon as the prior conversion
    59                                    *  is completed */
    60        };
    61    
    62        /*! REF2_5V Bit */
    63        enum REF2_5V_t {
    64            REF2_5V_OFF = 0x000,   /*! 1.5V */
    65            REF2_5V     = 0x040    /*! 2.5V */
    66        };
    67    
    68        /*! REFON Bit */
    69        enum REFON_t {
    70            REFON_OFF   = 0x000,   /*! Reference off */
    71            REFON       = 0x020    /*! Reference on */
    72        };
    73    
    74        /*! ADC12ON Bit */
    75        enum ADC12ON_t {
    76            ADC12ON_OFF = 0x000,   /*! ADC12 off */
    77            ADC12ON     = 0x010    /*! ADC12 on */
    78        };
    79    
    80        /*! ADC12OVIE Bit */
    81        enum ADC12OVIE_t {
    82            ADC12OVIE_OFF = 0x000,   /*! Overflow interrupt disabled */
    83            ADC12OVIE     = 0x008    /*! Overflow interrupt enabled */
    84        };
    85    
    86        /*! ADC12TOVIE Bit */
    87        enum ADC12TOVIE_t {
    88            ADC12TOVIE_OFF = 0x000,   /*! Conversion time overflow interrupt disabled */
    89            ADC12TOVIE     = 0x004    /*! Conversion time overflow interrupt disabled */
    90        };
    91    
    92        /*! ENC Bit */
    93        enum ENC_t {
    94            ENC_OFF = 0x000,  /*! ADC12 disabled */
    95            ENC     = 0x002   /*! ADC12 enabled */
    96        };
    97    
    98        /*! ADC12SC Bit */
    99        enum ADC12SC_t {
   100            ADC12SC_OFF = 0x000,  /*! No sample-and-conversion-start */
   101            ADC12SC     = 0x001   /*! Start sample-and-conversion */
   102        };
   103    
   104        /*! CSTARTADD Bits */
   105        enum CSTARTADD_t {
   106            CSTARTADD_0  = (0*0x1000u), /*! ADC12MEM0 */
   107            CSTARTADD_1  = (1*0x1000u), /*! ADC12MEM1 */
   108            CSTARTADD_2  = (2*0x1000u), /*! ADC12MEM2 */
   109            CSTARTADD_3  = (3*0x1000u), /*! ADC12MEM3 */
   110            CSTARTADD_4  = (4*0x1000u), /*! ADC12MEM4 */
   111            CSTARTADD_5  = (5*0x1000u), /*! ADC12MEM5 */
   112            CSTARTADD_6  = (6*0x1000u), /*! ADC12MEM6 */
   113            CSTARTADD_7  = (7*0x1000u), /*! ADC12MEM7 */
   114            CSTARTADD_8  = (8*0x1000u), /*! ADC12MEM8 */
   115            CSTARTADD_9  = (9*0x1000u), /*! ADC12MEM9 */
   116            CSTARTADD_10 = (10*0x1000u), /*! ADC12MEM10 */
   117            CSTARTADD_11 = (11*0x1000u), /*! ADC12MEM11 */
   118            CSTARTADD_12 = (12*0x1000u), /*! ADC12MEM12 */
   119            CSTARTADD_13 = (13*0x1000u), /*! ADC12MEM13 */
   120            CSTARTADD_14 = (14*0x1000u), /*! ADC12MEM14 */
   121            CSTARTADD_15 = 15*0x1000u    /*! ADC12MEM15 */
   122        };
   123    
   124        /*! SHS Bits */
   125        enum SHS_t {
   126            SHS_0 = (0*0x400u),    /*! ADC12SC bit */
   127            SHS_1 = (1*0x400u),    /*! Timer_A.OUT1 */
   128            SHS_2 = (2*0x400u),    /*! Timer_B.OUT0 */
   129            SHS_3 = 3*0x400u       /*! Timer_B.OUT1 */
   130        };
   131    
   132        /*! SHP Bits */
   133        enum SHP_t {
   134            SHP_OFF = 0x0000,  /*! SAMPCON signal is sourced from the sample-input signal */
   135            SHP     = 0x0200   /*! SAMPCON signal is sourced from the sampling timer. */
   136        };
   137    
   138        /*! ISSH Bits */
   139        enum ISSH_t {
   140            ISSH_OFF = 0x0000,  /*! The sample-input signal is not inverted */
   141            ISSH     = 0x0100   /*! The sample-input signal is inverted */
   142        };
   143    
   144    
   145        /*! ADC12DIV Bits */
   146        enum ADC12DIV_t {
   147            ADC12DIV_0 = (0*0x20u),    /*! Divide by 1 */
   148            ADC12DIV_1 = (1*0x20u),    /*! Divide by 2 */
   149            ADC12DIV_2 = (2*0x20u),    /*! Divide by 3 */
   150            ADC12DIV_3 = (3*0x20u),    /*! Divide by 4 */
   151            ADC12DIV_4 = (4*0x20u),    /*! Divide by 5 */
   152            ADC12DIV_5 = (5*0x20u),    /*! Divide by 6 */
   153            ADC12DIV_6 = (6*0x20u),    /*! Divide by 7 */
   154            ADC12DIV_7 = 7*0x20u       /*! Divide by 8 */
   155        };
   156    
   157        /*! ADC12SSEL Bits */
   158        enum ADC12SSEL_t {
   159            ADC12SSEL_0 = (0*8u),   /*! ADC12OSC */
   160            ADC12SSEL_1 = (1*8u),   /*! ACLK */
   161            ADC12SSEL_2 = (2*8u),   /*! MCLK */
   162            ADC12SSEL_3 = 3*8u      /*! SMCLK */
   163        };
   164    
   165        /*! CONSEQ Bits */
   166        enum CONSEQ_t {
   167            CONSEQ_0 = (0*2u),       /*! Single channel single conversion */
   168            CONSEQ_1 = (1*2u),       /*! Sequence of channels */
   169            CONSEQ_2 = (2*2u),       /*! Repeat single channel */
   170            CONSEQ_3 = 3*2u          /*! Repeat sequence of channels */
   171        };
   172    
   173        /*! ADC12 Busy Bit */
   174        enum ADC12BUSY_t {
   175            ADC12BUSY_OFF = 0x0000,
   176            ADC12BUSY     = 0x0001
   177        };
   178    
   179        /*! EOS Bit */
   180        enum EOS_t {
   181            EOS_OFF = 0x0000,  /*! Not end of sequence */
   182            EOS     = 0x0080   /*! End of sequence */
   183        };
   184    
   185        /*! SREF Bits */
   186        enum SREF_t {
   187            SREF_0 = (0*0x10u),    /*! VR+ = AVcc and VR-- = AVss */
   188            SREF_1 = (1*0x10u),    /*! VR+ = VREF+ and VR-- = AVss */
   189            SREF_2 = (2*0x10u),    /*! VR+ = VeREF+ and VR-- = AVss */
   190            SREF_3 = (3*0x10u),    /*! VR+ = VeREF+ and VR-- = AVss */
   191            SREF_4 = (4*0x10u),    /*! VR+ = AVcc and VR-- = VREF--/ VeREF-- */
   192            SREF_5 = (5*0x10u),    /*! VR+ = VREF+ and VR-- = VREF--/ VeREF-- */
   193            SREF_6 = (6*0x10u),    /*! VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
   194            SREF_7 = 7*0x10u       /*! VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
   195        };
   196    
   197        /*! ADC12 Interrupt Enable Bit 15 */
   198        enum ADC12IE15_t {
   199            ADC12IE15_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG15 bit */
   200            ADC12IE15     = 0x8000   /*! Enable the interrupt request for the ADC12IFG15 bit */
   201        };
   202    
   203        /*! ADC12 Interrupt Enable Bit 14 */
   204        enum ADC12IE14_t {
   205            ADC12IE14_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG14 bit */
   206            ADC12IE14     = 0x4000   /*! Enable the interrupt request for the ADC12IFG14 bit */
   207        };
   208    
   209        /*! ADC12 Interrupt Enable Bit 13 */
   210        enum ADC12IE13_t {
   211            ADC12IE13_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG13 bit */
   212            ADC12IE13     = 0x2000   /*! Enable the interrupt request for the ADC12IFG13 bit */
   213        };
   214    
   215        /*! ADC12 Interrupt Enable Bit 12 */
   216        enum ADC12IE12_t {
   217            ADC12IE12_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG12 bit */
   218            ADC12IE12     = 0x1000   /*! Enable the interrupt request for the ADC12IFG12 bit */
   219        };
   220    
   221        /*! ADC12 Interrupt Enable Bit 11 */
   222        enum ADC12IE11_t {
   223            ADC12IE11_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG11 bit */
   224            ADC12IE11     = 0x0800   /*! Enable the interrupt request for the ADC12IFG11 bit */
   225        };
   226    
   227        /*! ADC12 Interrupt Enable Bit 10 */
   228        enum ADC12IE10_t {
   229            ADC12IE10_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG10 bit */
   230            ADC12IE10     = 0x0400   /*! Enable the interrupt request for the ADC12IFG10 bit */
   231        };
   232    
   233        /*! ADC12 Interrupt Enable Bit 9 */
   234        enum ADC12IE9_t {
   235            ADC12IE9_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG9 bit */
   236            ADC12IE9     = 0x0200   /*! Enable the interrupt request for the ADC12IFG9 bit */
   237        };
   238    
   239        /*! ADC12 Interrupt Enable Bit 8 */
   240        enum ADC12IE8_t {
   241            ADC12IE8_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG8 bit */
   242            ADC12IE8     = 0x0100   /*! Enable the interrupt request for the ADC12IFG8 bit */
   243        };
   244    
   245        /*! ADC12 Interrupt Enable Bit 7 */
   246        enum ADC12IE7_t {
   247            ADC12IE7_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG7 bit */
   248            ADC12IE7     = 0x0080   /*! Enable the interrupt request for the ADC12IFG7 bit */
   249        };
   250    
   251        /*! ADC12 Interrupt Enable Bit 6 */
   252        enum ADC12IE6_t {
   253            ADC12IE6_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG6 bit */
   254            ADC12IE6     = 0x0040   /*! Enable the interrupt request for the ADC12IFG6 bit */
   255        };
   256    
   257        /*! ADC12 Interrupt Enable Bit 5 */
   258        enum ADC12IE5_t {
   259            ADC12IE5_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG5 bit */
   260            ADC12IE5     = 0x0020   /*! Enable the interrupt request for the ADC12IFG5 bit */
   261        };
   262    
   263        /*! ADC12 Interrupt Enable Bit 4 */
   264        enum ADC12IE4_t {
   265            ADC12IE4_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG4 bit */
   266            ADC12IE4     = 0x0010   /*! Enable the interrupt request for the ADC12IFG4 bit */
   267        };
   268    
   269        /*! ADC12 Interrupt Enable Bit 3 */
   270        enum ADC12IE3_t {
   271            ADC12IE3_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG3 bit */
   272            ADC12IE3     = 0x0008   /*! Enable the interrupt request for the ADC12IFG3 bit */
   273        };
   274    
   275        /*! ADC12 Interrupt Enable Bit 2 */
   276        enum ADC12IE2_t {
   277            ADC12IE2_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG2 bit */
   278            ADC12IE2     = 0x0004   /*! Enable the interrupt request for the ADC12IFG2 bit */
   279        };
   280    
   281        /*! ADC12 Interrupt Enable Bit 1 */
   282        enum ADC12IE1_t {
   283            ADC12IE1_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG1 bit */
   284            ADC12IE1     = 0x0002   /*! Enable the interrupt request for the ADC12IFG1 bit */
   285        };
   286    
   287        /*! ADC12 Interrupt Enable Bit 0 */
   288        enum ADC12IE0_t {
   289            ADC12IE0_OFF = 0x0000,  /*! Disable the interrupt request for the ADC12IFG0 bit */
   290            ADC12IE0     = 0x0001   /*! Enable the interrupt request for the ADC12IFG0 bit */
   291        };
   292    
   293        /*! INCH Bits */
   294        enum INCH_t {
   295            INCH_0 = (0),       /*! A0 */
   296            INCH_1 = (1),       /*! A1 */
   297            INCH_2 = (2),       /*! A2 */
   298            INCH_3 = (3),       /*! A3 */
   299            INCH_4 = (4),       /*! A4 */
   300            INCH_5 = (5),       /*! A5 */
   301            INCH_6 = (6),       /*! A6 */
   302            INCH_7 = (7),       /*! A7 */
   303            INCH_8 = (8),       /*! VeREF+ */
   304            INCH_9 = (9),       /*! VREF--/VeREF- */
   305            INCH_10 = (10),     /*! Temperature diode */
   306            INCH_11 = (11),     /*! (AVcc - AVss) / 2 */
   307            INCH_12 = (12),     /*! GND */
   308            INCH_13 = (13),     /*! GND */
   309            INCH_14 = (14),     /*! GND */
   310            INCH_15 = 15        /*! GND */
   311        };
   312    
   313    
   314        /*! ADC12IV Definitions */
   315        enum ADC12IV_t {
   316            ADC12IV_NONE        =  (0x0000),  /*! No Interrupt pending */
   317            ADC12IV_ADC12OVIFG  =  (0x0002),  /*! ADC12OVIFG */
   318            ADC12IV_ADC12TOVIFG =  (0x0004),  /*! ADC12TOVIFG */
   319            ADC12IV_ADC12IFG0   =  (0x0006),  /*! ADC12IFG0 */
   320            ADC12IV_ADC12IFG1   =  (0x0008),  /*! ADC12IFG1 */
   321            ADC12IV_ADC12IFG2   =  (0x000A),  /*! ADC12IFG2 */
   322            ADC12IV_ADC12IFG3   =  (0x000C),  /*! ADC12IFG3 */
   323            ADC12IV_ADC12IFG4   =  (0x000E),  /*! ADC12IFG4 */
   324            ADC12IV_ADC12IFG5   =  (0x0010),  /*! ADC12IFG5 */
   325            ADC12IV_ADC12IFG6   =  (0x0012),  /*! ADC12IFG6 */
   326            ADC12IV_ADC12IFG7   =  (0x0014),  /*! ADC12IFG7 */
   327            ADC12IV_ADC12IFG8   =  (0x0016),  /*! ADC12IFG8 */
   328            ADC12IV_ADC12IFG9   =  (0x0018),  /*! ADC12IFG9 */
   329            ADC12IV_ADC12IFG10  =  (0x001A),  /*! ADC12IFG10 */
   330            ADC12IV_ADC12IFG11  =  (0x001C),  /*! ADC12IFG11 */
   331            ADC12IV_ADC12IFG12  =  (0x001E),  /*! ADC12IFG12 */
   332            ADC12IV_ADC12IFG13  =  (0x0020),  /*! ADC12IFG13 */
   333            ADC12IV_ADC12IFG14  =  (0x0022),  /*! ADC12IFG14 */
   334            ADC12IV_ADC12IFG15  =  0x0024     /*! ADC12IFG15 */
   335        };
   336    
   337        /*! ADC12 Control Register 0 */
   338        struct ADC12CTL0_t {
   339            ADC12SHT1_t ADC12SHT1;  /*! Sample-and-hold time. These bits define the number
   340                                     * of ADC12CLK cycles in the sampling period for registers
   341                                     * ADC12MEM8 to ADC12MEM15. */
   342            ADC12SHT0_t ADC12SHT0;  /*! Sample-and-hold time. These bits define the number
   343                                     * of ADC12CLK cycles in the sampling period for registers
   344                                     * ADC12MEM0 to ADC12MEM7. */
   345            MSC_t MSC;              /*! Multiple sample and conversion. Valid only for sequence
   346                                     * or repeated modes.
   347                                     * 0 The sampling timer requires a rising edge of the SHI signal
   348                                     *   to trigger each sample-and-conversion.
   349                                     * 1 The first rising edge of the SHI signal triggers the sampling
   350                                     *   timer, but further sample-and-conversions are performed
   351                                     *   automatically as soon as the prior conversion is completed. */
   352            REF2_5V_t REF2_5V;      /*! Reference generator voltage. REFON must also be set.
   353                                     * 0 1.5V
   354                                     * 1 2.5V */
   355            REFON_t REFON;          /*! Reference generator on
   356                                     * 0 Reference off
   357                                     * 1 Reference on */
   358            ADC12ON_t ADC12ON;      /*! ADC12 on
   359                                     * 0 ADC12 off
   360                                     * 1 ADC12 on */
   361            ADC12OVIE_t ADC12OVIE;  /*! ADC12MEMx overflow-interrupt enable. The GIE bit must also be
   362                                     * set to enable the interrupt.
   363                                     * 0 Overflow interrupt disabled
   364                                     * 1 Overflow interrupt enabled */
   365            ADC12TOVIE_t ADC12TOVIE;  /*! ADC12 conversion-time-overflow interrupt enable.
   366                                       * The GIE bit must also be set to enable the interrupt.
   367                                       * 0 Conversion time overflow interrupt disabled
   368                                       * 1 Conversion time overflow interrupt enabled */
   369            ENC_t ENC;               /*! Enable conversion
   370                                      * 0 ADC12 disabled
   371                                      * 1 ADC12 enabled */
   372            ADC12SC_t ADC12SC;       /*! Start conversion. Software-controlled sample-and-conversion start.
   373                                      * ADC12SC and ENC may be set together with one instruction. ADC12SC is
   374                                      * reset automatically.
   375                                      * 0 No sample-and-conversion-start
   376                                      * 1 Start sample-and-conversion */
   377        };
   378    
   379        /*! ADC12 Control Register 1 */
   380        struct ADC12CTL1_t {
   381            CSTARTADD_t CSTARTADD;  /*! Conversion start address. These bits select which ADC12
   382                                     * conversion-memory register is used for a single conversion or for the first
   383                                     * conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh,
   384                                     * corresponding to ADC12MEM0 to ADC12MEM15. */
   385            SHS_t SHS;              /*! Sample-and-hold source select
   386                                     * 00 ADC12SC bit
   387                                     * 01 Timer_A.OUT1
   388                                     * 10 Timer_B.OUT0
   389                                     * 11 Timer_B.OUT1 */
   390            SHP_t SHP;              /*! Sample-and-hold pulse-mode select. This bit selects the source of the
   391                                     * sampling signal (SAMPCON) to be either the output of the sampling timer or
   392                                     * the sample-input signal directly.
   393                                     * 0 SAMPCON signal is sourced from the sample-input signal.
   394                                     * 1 SAMPCON signal is sourced from the sampling timer. */
   395            ISSH_t ISSH;            /*! Invert signal sample-and-hold
   396                                     * 0 The sample-input signal is not inverted.
   397                                     * 1 The sample-input signal is inverted. */
   398            ADC12DIV_t ADC12DIV;    /*! ADC12 clock divider
   399                                     * 000 /1
   400                                     * 001 /2
   401                                     * 010 /3
   402                                     * 011 /4
   403                                     * 100 /5
   404                                     * 101 /6
   405                                     * 110 /7
   406                                     * 111 /8 */
   407            ADC12SSEL_t ADC12SSEL;  /*! ADC12 clock source select
   408                                     * 00 ADC12OSC
   409                                     * 01 ACLK
   410                                     * 10 MCLK
   411                                     * 11 SMCLK */
   412            CONSEQ_t CONSEQ;        /*! Conversion sequence mode select
   413                                     * 00 Single-channel, single-conversion
   414                                     * 01 Sequence-of-channels
   415                                     * 10 Repeat-single-channel
   416                                     * 11 Repeat-sequence-of-channels */
   417            ADC12BUSY_t ADC12BUSY;  /*! ADC12 busy. This bit indicates an active sample or conversion operation.
   418                                     * 0 No operation is active.
   419                                     * 1 A sequence, sample, or conversion is active. */
   420        };
   421    
   422        /*! ADC12 Conversion Memory Control Registers */
   423        struct ADC12MCTL_t {
   424            EOS_t EOS;              /*! End of sequence. Indicates the last conversion in a sequence.
   425                                     * 0 Not end of sequence
   426                                     * 1 End of sequence */
   427            SREF_t SREF;            /*! Select reference
   428                                     * 000 VR+ = AVCC and VR-- = AVSS
   429                                     * 001 VR+ = VREF+ and VR-- = AVSS
   430                                     * 010 VR+ = VeREF+ and VR-- = AVSS
   431                                     * 011 VR+ = VeREF+ and VR-- = AVSS
   432                                     * 100 VR+ = AVCC and VR-- = VREF--/ VeREF--
   433                                     * 101 VR+ = VREF+ and VR-- = VREF--/ VeREF--
   434                                     * 110 VR+ = VeREF+ and VR-- = VREF--/ VeREF--
   435                                     * 111 VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
   436            INCH_t INCH;            /*! Input channel select
   437                                     * 0000 A0
   438                                     * 0001 A1
   439                                     * 0010 A2
   440                                     * 0011 A3
   441                                     * 0100 A4
   442                                     * 0101 A5
   443                                     * 0110 A6
   444                                     * 0111 A7
   445                                     * 1000 VeREF+
   446                                     * 1001 VREF--/VeREF--
   447                                     * 1010 Temperature diode
   448                                     * 1011 (AVCC � AVSS) / 2
   449                                     * 1100 GND
   450                                     * 1101 GND
   451                                     * 1110 GND
   452                                     * 1111 GND */
   453        };
   454    
   455        /*! ADC12 Interrupt Enable Register */
   456        struct ADC12IE_t {
   457            ADC12IE15_t ADC12IE15;  /*! Enable or disable the interrupt request for the ADC12IFG15 bit.
   458                                     * 0 Interrupt disabled
   459                                     * 1 Interrupt enabled */
   460            ADC12IE14_t ADC12IE14;  /*! Enable or disable the interrupt request for the ADC12IFG14 bit.
   461                                     * 0 Interrupt disabled
   462                                     * 1 Interrupt enabled */
   463            ADC12IE13_t ADC12IE13;  /*! Enable or disable the interrupt request for the ADC12IFG13 bit.
   464                                     * 0 Interrupt disabled
   465                                     * 1 Interrupt enabled */
   466            ADC12IE12_t ADC12IE12;  /*! Enable or disable the interrupt request for the ADC12IFG12 bit.
   467                                     * 0 Interrupt disabled
   468                                     * 1 Interrupt enabled */
   469            ADC12IE11_t ADC12IE11;  /*! Enable or disable the interrupt request for the ADC12IFG11 bit.
   470                                     * 0 Interrupt disabled
   471                                     * 1 Interrupt enabled */
   472            ADC12IE10_t ADC12IE10;  /*! Enable or disable the interrupt request for the ADC12IFG10 bit.
   473                                     * 0 Interrupt disabled
   474                                     * 1 Interrupt enabled */
   475            ADC12IE9_t ADC12IE9;  /*! Enable or disable the interrupt request for the ADC12IFG9 bit.
   476                                   * 0 Interrupt disabled
   477                                   * 1 Interrupt enabled */
   478            ADC12IE8_t ADC12IE8;  /*! Enable or disable the interrupt request for the ADC12IFG8 bit.
   479                                   * 0 Interrupt disabled
   480                                   * 1 Interrupt enabled */
   481            ADC12IE7_t ADC12IE7;  /*! Enable or disable the interrupt request for the ADC12IFG7 bit.
   482                                   * 0 Interrupt disabled
   483                                   * 1 Interrupt enabled */
   484            ADC12IE6_t ADC12IE6;  /*! Enable or disable the interrupt request for the ADC12IFG6 bit.
   485                                   * 0 Interrupt disabled
   486                                   * 1 Interrupt enabled */
   487            ADC12IE5_t ADC12IE5;  /*! Enable or disable the interrupt request for the ADC12IFG5 bit.
   488                                   * 0 Interrupt disabled
   489                                   * 1 Interrupt enabled */
   490            ADC12IE4_t ADC12IE4;  /*! Enable or disable the interrupt request for the ADC12IFG4 bit.
   491                                   * 0 Interrupt disabled
   492                                   * 1 Interrupt enabled */
   493            ADC12IE3_t ADC12IE3;  /*! Enable or disable the interrupt request for the ADC12IFG3 bit.
   494                                   * 0 Interrupt disabled
   495                                   * 1 Interrupt enabled */
   496            ADC12IE2_t ADC12IE2;  /*! Enable or disable the interrupt request for the ADC12IFG2 bit.
   497                                   * 0 Interrupt disabled
   498                                   * 1 Interrupt enabled */
   499            ADC12IE1_t ADC12IE1;  /*! Enable or disable the interrupt request for the ADC12IFG1 bit.
   500                                   * 0 Interrupt disabled
   501                                   * 1 Interrupt enabled */
   502            ADC12IE0_t ADC12IE0;  /*! Enable or disable the interrupt request for the ADC12IFG0 bit.
   503                                   * 0 Interrupt disabled
   504                                   * 1 Interrupt enabled */
   505        };
   506    
   507    instance:
   508        /*! ADC12CTL0 Register  */
   509        config ADC12CTL0_t  ADC12CTL0 = {
   510            ADC12SHT1 : SHT1_0,
   511            ADC12SHT0 : SHT0_0,
   512            MSC       : MSC_OFF,
   513            REF2_5V   : REF2_5V_OFF,
   514            REFON     : REFON_OFF,
   515            ADC12ON   : ADC12ON_OFF,
   516            ADC12OVIE : ADC12OVIE_OFF,
   517            ADC12TOVIE : ADC12TOVIE_OFF,
   518            ENC        : ENC_OFF,
   519            ADC12SC    : ADC12SC_OFF
   520        };
   521    
   522        /*! ADC12CTL1 Register */
   523        config ADC12CTL1_t  ADC12CTL1 = {
   524            CSTARTADD   : CSTARTADD_0,
   525            SHS         : SHS_0,
   526            SHP         : SHP_OFF,
   527            ISSH        : ISSH_OFF,
   528            ADC12DIV    : ADC12DIV_0,
   529            ADC12SSEL   : ADC12SSEL_0,
   530            CONSEQ      : CONSEQ_0,
   531            ADC12BUSY   : ADC12BUSY_OFF
   532        };
   533    
   534        /*! ADC12MCTL0 Register */
   535        config ADC12MCTL_t ADC12MCTL0 = {
   536            EOS    : EOS_OFF,
   537            SREF   : SREF_0,
   538            INCH   : INCH_0
   539        };
   540    
   541        /*! ADC12MCTL1 Register */
   542        config ADC12MCTL_t ADC12MCTL1 = {
   543            EOS    : EOS_OFF,
   544            SREF   : SREF_0,
   545            INCH   : INCH_0
   546        };
   547    
   548        /*! ADC12MCTL2 Register */
   549        config ADC12MCTL_t ADC12MCTL2 = {
   550            EOS    : EOS_OFF,
   551            SREF   : SREF_0,
   552            INCH   : INCH_0
   553        };
   554    
   555        /*! ADC12MCTL3 Register */
   556        config ADC12MCTL_t ADC12MCTL3 = {
   557            EOS    : EOS_OFF,
   558            SREF   : SREF_0,
   559            INCH   : INCH_0
   560        };
   561    
   562        /*! ADC12MCTL4 Register */
   563        config ADC12MCTL_t ADC12MCTL4 = {
   564            EOS    : EOS_OFF,
   565            SREF   : SREF_0,
   566            INCH   : INCH_0
   567        };
   568    
   569        /*! ADC12MCTL5 Register */
   570        config ADC12MCTL_t ADC12MCTL5 = {
   571            EOS    : EOS_OFF,
   572            SREF   : SREF_0,
   573            INCH   : INCH_0
   574        };
   575    
   576        /*! ADC12MCTL6 Register */
   577        config ADC12MCTL_t ADC12MCTL6 = {
   578            EOS    : EOS_OFF,
   579            SREF   : SREF_0,
   580            INCH   : INCH_0
   581        };
   582    
   583        /*! ADC12MCTL7 Register */
   584        config ADC12MCTL_t ADC12MCTL7 = {
   585            EOS    : EOS_OFF,
   586            SREF   : SREF_0,
   587            INCH   : INCH_0
   588        };
   589    
   590        /*! ADC12MCTL8 Register */
   591        config ADC12MCTL_t ADC12MCTL8 = {
   592            EOS    : EOS_OFF,
   593            SREF   : SREF_0,
   594            INCH   : INCH_0
   595        };
   596    
   597        /*! ADC12MCTL9 Register */
   598        config ADC12MCTL_t ADC12MCTL9 = {
   599            EOS    : EOS_OFF,
   600            SREF   : SREF_0,
   601            INCH   : INCH_0
   602        };
   603    
   604        /*! ADC12MCTL10 Register */
   605        config ADC12MCTL_t ADC12MCTL10 = {
   606            EOS    : EOS_OFF,
   607            SREF   : SREF_0,
   608            INCH   : INCH_0
   609        };
   610    
   611        /*! ADC12MCTL11 Register */
   612        config ADC12MCTL_t ADC12MCTL11 = {
   613            EOS    : EOS_OFF,
   614            SREF   : SREF_0,
   615            INCH   : INCH_0
   616        };
   617    
   618        /*! ADC12MCTL12 Register */
   619        config ADC12MCTL_t ADC12MCTL12 = {
   620            EOS    : EOS_OFF,
   621            SREF   : SREF_0,
   622            INCH   : INCH_0
   623        };
   624    
   625        /*! ADC12MCTL13 Register */
   626        config ADC12MCTL_t ADC12MCTL13 = {
   627            EOS    : EOS_OFF,
   628            SREF   : SREF_0,
   629            INCH   : INCH_0
   630        };
   631    
   632        /*! ADC12MCTL14 Register */
   633        config ADC12MCTL_t ADC12MCTL14 = {
   634            EOS    : EOS_OFF,
   635            SREF   : SREF_0,
   636            INCH   : INCH_0
   637        };
   638    
   639        /*! ADC12MCTL15 Register */
   640        config ADC12MCTL_t ADC12MCTL15 = {
   641            EOS    : EOS_OFF,
   642            SREF   : SREF_0,
   643            INCH   : INCH_0
   644        };
   645    
   646        /*! ADC12 Interrupt Enable Register */
   647        config ADC12IE_t ADC12IE = {
   648            ADC12IE15  : ADC12IE15_OFF,
   649            ADC12IE14  : ADC12IE14_OFF,
   650            ADC12IE13  : ADC12IE13_OFF,
   651            ADC12IE12  : ADC12IE12_OFF,
   652            ADC12IE11  : ADC12IE11_OFF,
   653            ADC12IE10  : ADC12IE10_OFF,
   654            ADC12IE9  : ADC12IE9_OFF,
   655            ADC12IE8  : ADC12IE8_OFF,
   656            ADC12IE7  : ADC12IE7_OFF,
   657            ADC12IE6  : ADC12IE6_OFF,
   658            ADC12IE5  : ADC12IE5_OFF,
   659            ADC12IE4  : ADC12IE4_OFF,
   660            ADC12IE3  : ADC12IE3_OFF,
   661            ADC12IE2  : ADC12IE2_OFF,
   662            ADC12IE1  : ADC12IE1_OFF,
   663            ADC12IE0  : ADC12IE0_OFF
   664        };
   665    
   666    
   667        /*! ADC12MEM0 Register */
   668        config Bits16 ADC12MEM0 = 0;
   669    
   670        /*! ADC12MEM1 Register */
   671        config Bits16 ADC12MEM1 = 0;
   672    
   673        /*! ADC12MEM2 Register */
   674        config Bits16 ADC12MEM2 = 0;
   675    
   676        /*! ADC12MEM3 Register */
   677        config Bits16 ADC12MEM3 = 0;
   678    
   679        /*! ADC12MEM4 Register */
   680        config Bits16 ADC12MEM4 = 0;
   681    
   682        /*! ADC12MEM5 Register */
   683        config Bits16 ADC12MEM5 = 0;
   684    
   685        /*! ADC12MEM6 Register */
   686        config Bits16 ADC12MEM6 = 0;
   687    
   688        /*! ADC12MEM7 Register */
   689        config Bits16 ADC12MEM7 = 0;
   690    
   691        /*! ADC12MEM8 Register */
   692        config Bits16 ADC12MEM8 = 0;
   693    
   694        /*! ADC12MEM9 Register */
   695        config Bits16 ADC12MEM9 = 0;
   696    
   697        /*! ADC12MEM10 Register */
   698        config Bits16 ADC12MEM10 = 0;
   699    
   700        /*! ADC12MEM11 Register */
   701        config Bits16 ADC12MEM11 = 0;
   702    
   703        /*! ADC12MEM12 Register */
   704        config Bits16 ADC12MEM12 = 0;
   705    
   706        /*! ADC12MEM13 Register */
   707        config Bits16 ADC12MEM13 = 0;
   708    
   709        /*! ADC12MEM14 Register */
   710        config Bits16 ADC12MEM14 = 0;
   711    
   712        /*! ADC12MEM15 Register */
   713        config Bits16 ADC12MEM15 = 0;
   714    
   715        /*! ADC12IV Register */
   716        config Bits16 ADC12IV = ADC12IV_NONE;
   717    
   718        /*! ADC12IFG Register */
   719        config Bits16 ADC12IFG = 0;
   720    
   721        /*! ADC12 has 16 interrupt enable */
   722        config regIntVect_t interruptSource[16];
   723    
   724        /*! Determine if each Register needs to be forced set or not */
   725        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   726        [
   727            { register : "ADC12CTL0" , regForceSet : false },
   728            { register : "ADC12CTL1" , regForceSet : false },
   729            { register : "ADC12IFG" , regForceSet : false },
   730            { register : "ADC12IV" , regForceSet : false },
   731            { register : "ADC12IE" , regForceSet : false },
   732            { register : "ADC12MCTL0" , regForceSet : false },
   733            { register : "ADC12MCTL1" , regForceSet : false },
   734            { register : "ADC12MCTL2" , regForceSet : false },
   735            { register : "ADC12MCTL3" , regForceSet : false },
   736            { register : "ADC12MCTL4" , regForceSet : false },
   737            { register : "ADC12MCTL5" , regForceSet : false },
   738            { register : "ADC12MCTL6" , regForceSet : false },
   739            { register : "ADC12MCTL7" , regForceSet : false },
   740            { register : "ADC12MCTL8" , regForceSet : false },
   741            { register : "ADC12MCTL9" , regForceSet : false },
   742            { register : "ADC12MCTL10" , regForceSet : false },
   743            { register : "ADC12MCTL11" , regForceSet : false },
   744            { register : "ADC12MCTL12" , regForceSet : false },
   745            { register : "ADC12MCTL13" , regForceSet : false },
   746            { register : "ADC12MCTL14" , regForceSet : false },
   747            { register : "ADC12MCTL15" , regForceSet : false },
   748            { register : "ADC12MEM0" , regForceSet : false },
   749            { register : "ADC12MEM1" , regForceSet : false },
   750            { register : "ADC12MEM2" , regForceSet : false },
   751            { register : "ADC12MEM3" , regForceSet : false },
   752            { register : "ADC12MEM4" , regForceSet : false },
   753            { register : "ADC12MEM5" , regForceSet : false },
   754            { register : "ADC12MEM6" , regForceSet : false },
   755            { register : "ADC12MEM7" , regForceSet : false },
   756            { register : "ADC12MEM8" , regForceSet : false },
   757            { register : "ADC12MEM9" , regForceSet : false },
   758            { register : "ADC12MEM10" , regForceSet : false },
   759            { register : "ADC12MEM11" , regForceSet : false },
   760            { register : "ADC12MEM12" , regForceSet : false },
   761            { register : "ADC12MEM13" , regForceSet : false },
   762            { register : "ADC12MEM14" , regForceSet : false },
   763            { register : "ADC12MEM15" , regForceSet : false },
   764        ];
   765    }