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13 14 15 16
17
18 package ti.catalog.c6000;
19
20 metaonly module TMS320C66AK2E05 inherits ti.catalog.ICpuDataSheet
21 {
22
23 config long cacheSizeL1[string] = [
24 ["0k", 0x0000],
25 ["4k", 0x1000],
26 ["8k", 0x2000],
27 ["16k", 0x4000],
28 ["32k", 0x8000],
29 ];
30
31
32 config long cacheSizeL2[string] = [
33 ["0k", 0x000000],
34 ["32k", 0x008000],
35 ["64k", 0x010000],
36 ["128k", 0x020000],
37 ["256k", 0x040000],
38 ["512k", 0x080000],
39 ];
40
41
42 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
43 ['l1PMode', {
44 desc:"L1P Cache",
45 base: 0x00E00000,
46 map : [
47 ["0k",0x0000],
48 ["4k",0x1000],
49 ["8k",0x2000],
50 ["16k",0x4000],
51 ["32k",0x8000]
52 ],
53 defaultValue: "32k",
54 memorySection: "L1PSRAM"
55 }],
56 ['l1DMode', {
57 desc:"L1D Cache",
58 base: 0x00F00000,
59 map : [
60 ["0k",0x0000],
61 ["4k",0x1000],
62 ["8k",0x2000],
63 ["16k",0x4000],
64 ["32k",0x8000]
65 ],
66 defaultValue: "32k",
67 memorySection: "L1DSRAM"
68 }],
69 ['l2Mode', {
70 desc:"L2 Cache",
71 base: 0x00800000,
72 map : [
73 ["0k",0x0000],
74 ["32k",0x8000],
75 ["64k",0x10000],
76 ["128k", 0x020000],
77 ["256k", 0x040000],
78 ["512k", 0x080000],
79 ],
80 defaultValue: "0k",
81 memorySection: "L2SRAM"}
82 ],
83 ];
84
85 instance:
86
87 override config string cpuCore = "6600";
88 override config string isa = "66";
89 override config string cpuCoreRevision = "1.0";
90
91 override config int minProgUnitSize = 1;
92 override config int minDataUnitSize = 1;
93 override config int dataWordSize = 4;
94
95 /*!
96 * ======== memMap ========
97 * The default memory map for this device
98 */
99 config xdc.platform.IPlatform.Memory memMap[string] = [
100 ["L2SRAM", {
101 comment: "1MB L2 SRAM/CACHE",
102 name: "L2SRAM",
103 base: 0x00800000,
104 len: 0x00100000,
105 space: "code/data",
106 access: "RWX"
107 }],
108
109 ["L1PSRAM", {
110 comment: "32KB RAM/CACHE L1 program memory",
111 name: "L1PSRAM",
112 base: 0x00E00000,
113 len: 0x00008000,
114 space: "code",
115 access: "RWX"
116 }],
117
118 ["L1DSRAM", {
119 comment: "32KB RAM/CACHE L1 data memory",
120 name: "L1DSRAM",
121 base: 0x00F00000,
122 len: 0x00008000,
123 space: "data",
124 access: "RW"
125 }],
126
127 ["MSMCSRAM", {
128 comment: "2MB MSMC SRAM",
129 name: "MSMCSRAM",
130 base: 0x0C000000,
131 len: 0x00200000,
132 space: "code/data",
133 access: "RWX"
134 }],
135 ];
136 };
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140