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18 package ti.catalog.arm.cortexm3.concertoInit;
19
20 import xdc.rov.ViewInfo;
21
22 /*!
23 * ======== Boot ========
24 * Concerto M3 Boot Support.
25 *
26 * The Boot module supports boot initialization for the Concerto M3 core.
27 * A special boot init function is created based on the configuration
28 * settings for this module. This function is hooked into the
29 * xdc.runtime.Reset.fxns[] array and called very early at boot time (prior
30 * to cinit processing).
31 *
32 * The code to support the boot module is placed in a separate section
33 * named `".text:.bootCodeSection"` to allow placement of this section in
34 * the linker .cmd file if necessary. This section is a subsection of the
35 * `".text"` section so this code will be placed into the .text section unless
36 * explicitly placed, either through
37 * `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
38 * command file.
39 */
40 @Template("./Boot.xdt")
41 @NoRuntime
42 module Boot
43 {
44 /*! System PLL Fractional Multiplier (SPLLFMULT) value */
45 metaonly enum FractMult {
46 Fract_0 = 0x000, /*! Fractional multiplier is 0 */
47 Fract_25 = 0x100, /*! Fractional multiplier is 0.25 */
48 Fract_50 = 0x200, /*! Fractional multiplier is 0.5 */
49 Fract_75 = 0x300 /*! Fractional multiplier is 0.75 */
50 }
51
52 /*! System Clock Divider (SYSDIVSEL) value */
53 metaonly enum SysDiv {
54 Div_1 = 0x0, /*! Divide by 1 */
55 Div_2 = 0x1, /*! Divide by 2 */
56 Div_4 = 0x2, /*! Divide by 4 */
57 Div_8 = 0x3 /*! Divide by 8 */
58 };
59
60 /*! M3 Subsystem Clock Divider (M3SSDIVSEL) value */
61 metaonly enum M3Div {
62 M3Div_1 = 0x0, /*! Divide by 1 */
63 M3Div_2 = 0x1, /*! Divide by 2 */
64 M3Div_4 = 0x2 /*! Divide by 4 */
65 };
66
67 metaonly struct ModuleView {
68 Bool configureClocks;
69 UInt OSCCLK;
70 UInt SPLLIMULT;
71 String SPLLFMULT;
72 String SYSDIVSEL;
73 String M3SSDIVSEL;
74 Bool bootC28;
75 }
76
77 @Facet
78 metaonly config ViewInfo.Instance rovViewInfo =
79 ViewInfo.create({
80 viewMap: [
81 [
82 'Module',
83 {
84 type: ViewInfo.MODULE,
85 viewInitFxn: 'viewInitModule',
86 structName: 'ModuleView'
87 }
88 ],
89 ]
90 });
91
92 /*!
93 * Clock configuration flag, default is false.
94 *
95 * Set to true to configure the PLL and system and M3 subsystem clock
96 * dividers.
97 */
98 config Bool configureClocks = false;
99
100 /*!
101 * ======== sharedMemoryEnable ========
102 * Shared RAM memory enable mask.
103 *
104 * This parameter is used for writing the MEMCNF register.
105 * By default, all shared RAM segments will be enabled at runtime.
106 * To disable a shared RAM segment, set the corresponding bit to 0.
107 * If any data is loaded to a shared RAM segment, the segment must
108 * be enabled prior to loading the program through other means.
109 */
110 config Bits32 sharedMemoryEnable = 0xffffffff;
111
112 /*!
113 * ======== sharedMemoryOwnerMask ========
114 * Shared RAM owner select mask.
115 *
116 * This parameter is used for writing the MSxMSEL register.
117 * By default, each value of each shared RAM select bit is '0'.
118 * This means the M3 is the owner and has write access based upon
119 * the sharedMemoryAccess bits. Setting a '1' in any bit position
120 * makes the C28 the owner of that shared RAM segment.
121 */
122 config Bits32 sharedMemoryOwnerMask = 0;
123
124 /*!
125 * ======== sharedMemoryAccess ========
126 * Shared RAM M3 write access.
127 *
128 * This parameter is used for writing the MSxSRCR registers.
129 * It determines the M3 write access for each shared RAM segment only
130 * when the M3 is the owner of the shared RAM segment.
131 * By default, the M3 is allowed to CPU fetch, DMA write, and CPU write.
132 *
133 * Bit 0 is for CPU fetch. 0 - fetch allowed, 1 - fetch not allowed
134 * Bit 1 is for DMA write. 0 - write allowed, 1 - write not allowed
135 * Bit 2 is for CPU write. 0 - write allowed, 1 - write not allowed
136 */
137 config Bits32 sharedMemoryAccess[8];
138
139 /*!
140 * OSCCLK input frequency to PLL, in MHz. Default is 20 MHz.
141 *
142 * This is the frequency of the oscillator clock (OSCCLK) input to the
143 * PLL.
144 */
145 metaonly config UInt OSCCLK = 20;
146
147 /*! System PLL Integer Multiplier (SPLLIMULT) value */
148 metaonly config UInt SPLLIMULT = 1;
149
150 /*! System PLL Fractional Multiplier (SPLLFMULT) value */
151 metaonly config FractMult SPLLFMULT = Fract_0;
152
153 /*! System Clock Divider (SYSDIVSEL) value */
154 metaonly config SysDiv SYSDIVSEL = Div_8;
155
156 /*! M3 Subsystem Clock Divider (M3SSDIVSEL) value */
157 metaonly config M3Div M3SSDIVSEL = M3Div_4;
158
159 /*!
160 * Flash controller wait states configuration flag, default is true.
161 *
162 * Set to true to configure the Flash controller wait states. The number
163 * of wait states is computed based upon the CPU frequency.
164 */
165 metaonly config Bool configureFlashWaitStates = true;
166
167 /*!
168 * Flash controller program cache enable flag, default is true.
169 *
170 * Set to true to enable the Flash controller's program cache.
171 */
172 metaonly config Bool enableFlashProgramCache = true;
173
174 /*!
175 * Flash controller data cache enable flag, default is true.
176 *
177 * Set to true to enable the Flash controller's data cache.
178 */
179 metaonly config Bool enableFlashDataCache = true;
180
181 /*!
182 * Function to be called when Limp mode is detected.
183 *
184 * This function is called when the Boot module is about to configure
185 * the PLL, but finds the device operating in Limp mode (i.e., the mode
186 * when a missing OSCCLK input has been detected).
187 *
188 * If this function is not specified by the application, a default
189 * function will be used, which spins in an infinite loop.
190 */
191 metaonly config Fxn limpAbortFunction;
192
193 /*!
194 * Boot from Flash flag. Default is true.
195 *
196 * Set to true to enable booting the M3 from Flash.
197 */
198 metaonly config Bool bootFromFlash = true;
199
200 /*!
201 * Initiate booting of the C28 processor. Default is false.
202 *
203 * Set to true to enable the M3 to initiate boot of the C28.
204 *
205 * If enabled, this will occur after the optional clock configuration
206 * step, enabled by `{@link #configureClocks}`.
207 */
208 metaonly config Bool bootC28 = false;
209
210 /*!
211 * Initialize C28 RAM regions before booting the C28 processor.
212 * Default is true.
213 *
214 * Set to true to enable initialization of these C28 RAM regions: M1,
215 * CtoM, LO, L1, L2, and L3. RAM locations will be zeroed, and the ECC or
216 * parity bits will be initialized.
217 */
218 metaonly config Bool initC28RAMs = true;
219
220 /*!
221 * Configure Shared RAM regions before booting the C28 processor.
222 * Default is true.
223 *
224 * Set to true to enable Shared RAM regions S0-S7, to set the
225 * owner of each region and the write access permissions for the onwer.
226 */
227 metaonly config Bool configSharedRAMs = true;
228
229 /*!
230 * @_nodoc
231 * ======== getFrequency ========
232 * Gets the resulting M3 CPU frequency (in Hz) given the Clock
233 * configuration parameters.
234 *
235 */
236 UInt32 getFrequency();
237
238 /*!
239 * @_nodoc
240 * ======== registerFreqListener ========
241 * Register a module to be notified whenever the frequency changes.
242 *
243 * The registered module must have a function named 'fireFrequencyUpdate'
244 * which takes the new frequency as an argument.
245 */
246 function registerFreqListener();
247
248 internal:
249
250
251 metaonly config UInt timestampFreq;
252
253
254 metaonly config String displayFrequency;
255
256
257 metaonly config String displayFrequency28;
258
259
260 metaonly config UInt flashWaitStates = 3;
261
262
263 metaonly config Bits32 MSxSRCR[2];
264
265 };
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