1    /*
     2     *  Copyright (c) 2014 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== ITMS320CDRx40x.xdc ========
    15     *
    16     */
    17    
    18    /*!
    19     *  ======== ITMS320CDRx40x ========
    20     *  An interface implemented by all DRx40x and DRx41x devices
    21     *
    22     *  This interface is defined to factor common data about all DRA40x and
    23     *  DRA41x devices into a single file; they are all configured in the same way.
    24     */
    25    metaonly interface ITMS320CDRx40x inherits ti.catalog.ICpuDataSheet
    26    {
    27        config long cacheSizeL1[string] = [
    28            ["0k",  0x0000],
    29            ["4k",  0x1000],
    30            ["8k",  0x2000],
    31            ["16k", 0x4000],
    32            ["32k", 0x8000],
    33        ];
    34    
    35        config long cacheSizeL2[string] = [
    36            ["0k",  0x00000],
    37            ["32k", 0x08000],
    38            ["64k", 0x10000],
    39            ["128k",0x20000],
    40        ];
    41    
    42        readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    43             ['l1PMode',{desc:"L1P Cache",
    44                         base:0x11E00000,
    45                         map : [["0k",0x0000],
    46                                ["4k",0x1000],
    47                                ["8k",0x2000],
    48                                ["16k",0x4000]],
    49                         defaultValue: "16k",
    50                         memorySection: "L1PSRAM"}],
    51         
    52             ['l1DMode',{desc:"L1D Cache",
    53                         base:0x11F00000,
    54                         map : [["0k",0x0000],
    55                                ["4k",0x1000],
    56                                ["8k",0x2000],
    57                                ["16k",0x4000],
    58                                ["32k",0x8000]],
    59                         defaultValue: "32k",
    60                         memorySection: "L1DSRAM"}],
    61                     
    62             ['l2Mode',{desc:"L2 Cache",
    63                         base: 0x11810000,
    64                         map : [["0k",0x0000],
    65                                ["32k",0x8000],
    66                                ["64k",0x10000],
    67                                ["128k",0x20000]],
    68                         defaultValue: "0k",
    69                         memorySection: "IRAM"}]
    70    
    71        ];
    72    
    73    instance:
    74        
    75        override config string   cpuCore        = "64x+";
    76        override config string   isa            = "64P";
    77        override config string   cpuCoreRevision = "1.0";
    78    
    79        override config int     minProgUnitSize = 1;
    80        override config int     minDataUnitSize = 1;    
    81        override config int     dataWordSize    = 4;
    82    
    83        /*!
    84         *  ======== memMap ========
    85         *  The default memory map for this device
    86         */
    87        config xdc.platform.IPlatform.Memory memMap[string]  = [
    88            ["IRAM", {
    89                comment:    "Internal 192KB UMAP0 memory",
    90                name:       "IRAM",
    91                base:       0x11810000,
    92                len:        0x00030000,
    93                space:      "code/data",
    94                access:     "RWX"
    95            }],
    96    
    97            ["L1PSRAM", {
    98                comment:    "Internal 16KB RAM/CACHE L1 program memory",
    99                name:       "L1PSRAM",
   100                base:       0x11E00000,
   101                len:        0x00004000,
   102                space:      "code",
   103                access:     "RWX"
   104            }],
   105    
   106            ["L1DSRAM", {
   107                comment:    "Internal 32KB RAM/CACHE L1 data memory",
   108                name:       "L1DSRAM",
   109                base:       0x11F00000,
   110                len:        0x00008000,
   111                space:      "data",
   112                access:     "RW"
   113            }],
   114    
   115            ["ARM_RAM", {
   116                comment:    "Internal ARM RAM memory",
   117                name:       "ARM_RAM",
   118                base:       0x10008000,
   119                len:        0x00004000,
   120                space:      "data",
   121                access:     "RW"
   122            }],
   123        ];
   124    };
   125    /*
   126     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,456; 3-22-2014 18:56:52; /db/ztree/library/trees/platform/platform-o48x/src/
   127     */
   128