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18 metaonly module DRA7XX inherits ti.catalog.ICpuDataSheet
19 {
20 instance:
21 config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
22
23 override config string cpuCore = "v7A15";
24 override config string isa = "v7A15";
25 override config string cpuCoreRevision = "1.0";
26 override config int minProgUnitSize = 1;
27 override config int minDataUnitSize = 1;
28 override config int dataWordSize = 4;
29
30 /*!
31 * ======== memMap ========
32 * The memory map returned be getMemoryMap().
33 */
34 config xdc.platform.IPlatform.Memory memMap[string] = [
35 ["SRAM", {
36 comment: "On-Chip SRAM",
37 name: "SRAM",
38 base: 0x402F0000,
39 len: 0x00010000,
40 space: "code/data",
41 access: "RWX"
42 }],
43
44 45 46
47 ["OCMC_RAM1", {
48 name: "OCMC_RAM1",
49 base: 0x40300000,
50 len: 0x00080000
51 }],
52
53 54 55
56 ["OCMC_RAM2", {
57 name: "OCMC_RAM2",
58 base: 0x40400000,
59 len: 0x00100000
60 }],
61
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65 ["OCMC_RAM3", {
66 name: "OCMC_RAM3",
67 base: 0x40500000,
68 len: 0x00100000
69 }]
70 ];
71 }
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