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17
18 package ti.catalog.c2800.initF2837x;
19
20 import xdc.rov.ViewInfo;
21
22 /*!
23 * ======== Boot ========
24 * Soprano Boot Support.
25 *
26 * The Boot module supports boot initialization for the C28 Soprano cores.
27 * A special boot init function is created based on the configuration
28 * settings for this module. This function is hooked into the
29 * xdc.runtime.Reset.fxns[] array and called very early at boot time (prior
30 * to cinit processing).
31 *
32 * The code to support the boot module is placed in a separate section
33 * named `".text:.bootCodeSection"` to allow placement of this section in
34 * the linker .cmd file if necessary. This section is a subsection of the
35 * `".text"` section so this code will be placed into the .text section unless
36 * explicitly placed, either through
37 * `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
38 * command file.
39 */
40 @Template("./Boot.xdt")
41 @NoRuntime
42 module Boot
43 {
44 /*! System PLL Fractional Multiplier (SPLLFMULT) value */
45 metaonly enum FractMult {
46 Fract_0 = 0x000, /*! Fractional multiplier is 0 */
47 Fract_25 = 0x100, /*! Fractional multiplier is 0.25 */
48 Fract_50 = 0x200, /*! Fractional multiplier is 0.5 */
49 Fract_75 = 0x300 /*! Fractional multiplier is 0.75 */
50 }
51
52 metaonly struct ModuleView {
53 Bool configureClocks;
54 UInt OSCCLK;
55 UInt SPLLIMULT;
56 String SPLLFMULT;
57 String SYSCLKDIVSEL;
58 Bool bootCPU2;
59 }
60
61 @Facet
62 metaonly config ViewInfo.Instance rovViewInfo =
63 ViewInfo.create({
64 viewMap: [
65 [
66 'Module',
67 {
68 type: ViewInfo.MODULE,
69 viewInitFxn: 'viewInitModule',
70 structName: 'ModuleView'
71 }
72 ],
73 ]
74 });
75
76 /*!
77 * Clock configuration flag, default is false.
78 *
79 * Set to true to configure the PLL and system and M3 subsystem clock
80 * dividers.
81 */
82 config Bool configureClocks = false;
83
84 /*!
85 * Watchdog disable flag, default is false.
86 *
87 * Set to true to disable the watchdog timer.
88 */
89 metaonly config Bool disableWatchdog = false;
90
91 /*!
92 * OSCCLK input frequency to PLL, in MHz. Default is 10 MHz.
93 *
94 * This is the frequency of the oscillator clock (OSCCLK) input to the
95 * PLL.
96 */
97 metaonly config UInt OSCCLK = 20;
98
99 /*! System PLL Integer Multiplier (SPLLIMULT) value */
100 metaonly config UInt SPLLIMULT = 1;
101
102 /*! System PLL Fractional Multiplier (SPLLFMULT) value */
103 metaonly config FractMult SPLLFMULT = Fract_0;
104
105 /*! System Clock Divider Select (SYSCLKDIVSEL) value */
106 metaonly config UInt SYSCLKDIVSEL = 2;
107
108 /*!
109 * Flash controller wait states configuration flag, default is true.
110 *
111 * Set to true to configure the Flash controller wait states. The number
112 * of wait states is computed based upon the CPU frequency.
113 */
114 metaonly config Bool configureFlashWaitStates = true;
115
116 /*!
117 * Flash controller program cache enable flag, default is true.
118 *
119 * Set to true to enable the Flash controller's program cache.
120 */
121 metaonly config Bool enableFlashProgramCache = true;
122
123 /*!
124 * Flash controller data cache enable flag, default is true.
125 *
126 * Set to true to enable the Flash controller's data cache.
127 */
128 metaonly config Bool enableFlashDataCache = true;
129
130 /*!
131 * Function to be called when Limp mode is detected.
132 *
133 * This function is called when the Boot module is about to configure
134 * the PLL, but finds the device operating in Limp mode (i.e., the mode
135 * when a missing OSCCLK input has been detected).
136 *
137 * If this function is not specified by the application, a default
138 * function will be used, which spins in an infinite loop.
139 */
140 metaonly config Fxn limpAbortFunction;
141
142 /*!
143 * Boot from Flash flag. Default is true.
144 *
145 * Set to true to enable booting CPU1 from Flash.
146 */
147 metaonly config Bool bootFromFlash = true;
148
149 /*!
150 * Initiate booting of the CPU2 processor. Default is false.
151 *
152 * Set to true to enable CPU1 to initiate boot of CPU2.
153 *
154 * If enabled, this will occur after the optional clock configuration
155 * step, enabled by `{@link #configureClocks}`.
156 */
157 metaonly config Bool bootCPU2 = false;
158
159 /*!
160 * Configure Shared RAM regions before booting the C28 processor.
161 * Default is true.
162 *
163 * Set to true to enable Shared RAM regions S0-S7, to set the
164 * owner of each region and the write access permissions for the onwer.
165 */
166 metaonly config Bool configSharedRAMs = true;
167
168 /*!
169 * ======== sharedMemoryOwnerMask ========
170 * Shared RAM owner select mask.
171 *
172 * This parameter is used for writing the GSxMSEL register.
173 * By default, each value of each shared RAM select bit is '0'.
174 * This means the CPU1 is the owner and has write access.
175 * Setting a '1' in any bit position makes CPU2 the owner of that
176 * shared RAM segment.
177 */
178 metaonly config Bits32 sharedMemoryOwnerMask = 0;
179
180 /*!
181 * @_nodoc
182 * ======== getFrequency ========
183 * Gets the resulting M3 CPU frequency (in Hz) given the Clock
184 * configuration parameters.
185 *
186 */
187 UInt32 getFrequency();
188
189 /*!
190 * @_nodoc
191 * ======== registerFreqListener ========
192 * Register a module to be notified whenever the frequency changes.
193 *
194 * The registered module must have a function named 'fireFrequencyUpdate'
195 * which takes the new frequency as an argument.
196 */
197 function registerFreqListener();
198
199 internal:
200
201
202 metaonly config UInt timestampFreq;
203
204
205 metaonly config String displayFrequency;
206
207
208 metaonly config UInt flashWaitStates = 3;
209
210 };
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