1    /* --COPYRIGHT--,EPL
     2     *  Copyright (c) 2008 Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     * 
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     * 
    11     * --/COPYRIGHT--*/
    12    
    13    import ti.catalog.msp430.peripherals.timer.Timer_A3;
    14    import ti.catalog.msp430.peripherals.timer.Timer_B3;
    15    import ti.catalog.msp430.peripherals.clock.BCSplus;
    16    import ti.catalog.msp430.peripherals.communication.USCI_A0_UART_2xx;
    17    import ti.catalog.msp430.peripherals.communication.USCI_A0_SPI_2xx;
    18    import ti.catalog.msp430.peripherals.communication.USCI_B0_SPI_2xx;
    19    import ti.catalog.msp430.peripherals.communication.USCI_B0_I2C_2xx;
    20    import ti.catalog.msp430.peripherals.adc.ADC10;
    21    import ti.catalog.msp430.peripherals.watchdog.WDTplus;
    22    import ti.catalog.msp430.peripherals.oa.OA_2;
    23    import ti.catalog.msp430.peripherals.gpio.GPIO_MSP430F22x4;
    24    import ti.catalog.msp430.peripherals.memory.Flash_2xx;
    25    import ti.catalog.msp430.peripherals.special_function.IE1;
    26    import ti.catalog.msp430.peripherals.special_function.IE2;
    27    import ti.catalog.msp430.peripherals.interrupt.Interrupt_Controller;
    28    
    29    /*!
    30     *  ======== IMSP430x22xx.xdc ========
    31     *  Common definition for MSP430x22xx devices
    32     */
    33    metaonly interface IMSP430x22xx inherits ti.catalog.msp430.IMSP430
    34    {
    35    
    36    instance:
    37    
    38        config Timer_A3.Instance timer_A3;
    39        config Timer_B3.Instance timer_B3;
    40        config BCSplus.Instance clock;
    41        config USCI_A0_UART_2xx.Instance usci_A0_UART;
    42        config USCI_A0_SPI_2xx.Instance usci_A0_SPI;
    43        config USCI_B0_SPI_2xx.Instance usci_B0_SPI;
    44        config USCI_B0_I2C_2xx.Instance usci_B0_I2C;
    45        config ADC10.Instance adc10;
    46        config WDTplus.Instance wdtPlus;
    47        config OA_2.Instance oa;
    48        config GPIO_MSP430F22x4.Instance gpio;
    49        config Flash_2xx.Instance flash;
    50        config IE1.Instance interruptEnableRegister1;
    51        config IE2.Instance interruptEnableRegister2;
    52        config Interrupt_Controller.Instance interruptController;
    53    
    54        /*!
    55         *  ======== commonMap ========
    56         *  Memory map elements shared by all MSP430x22xx devices
    57         */
    58        config xdc.platform.IPlatform.Memory commonMap[string]  = [
    59            ["PERIPHERALS_8BIT", {
    60                comment:    "Memory mapped I/O registers",
    61                name:       "PERIPHERALS_8BIT",
    62                base:       0x0010,
    63                len:        0x00F0,
    64                space:      "io",
    65                access:     "RW"
    66            }],
    67    
    68            ["PERIPHERALS_16BIT", {
    69                comment:    "Memory mapped I/O registers",
    70                name:       "PERIPHERALS_16BIT",
    71                base:       0x0100,
    72                len:        0x0100,
    73                space:      "io",
    74                access:     "RW"
    75            }],
    76    
    77            ["BSLSKEY", {
    78                comment:    "Boot loader security key",
    79                name:       "BSLSKEY",
    80                base:       0xFFDE,
    81                len:        0x0002,
    82                space:      "data",
    83                access:     "RI"
    84            }],
    85    
    86            ["INT00", {
    87                comment:    "Reserved Vector (int00)",
    88                name:       "INT00",
    89                base:       0xFFE0,
    90                len:        0x0002,
    91                space:      "data",
    92                access:     "RW"
    93            }],
    94    
    95            ["INT01", {
    96                comment:    "Reserved Vector (int01)",
    97                name:       "INT01",
    98                base:       0xFFE2,
    99                len:        0x0002,
   100                space:      "data",
   101                access:     "RW"
   102            }],
   103    
   104            ["INT02", {
   105                comment:    "I/O Port P1 Vector (int02)",
   106                name:       "INT02",
   107                base:       0xFFE4,
   108                len:        0x0002,
   109                space:      "data",
   110                access:     "RW"
   111            }],
   112    
   113            ["INT03", {
   114                comment:    "I/O Port P2 Vector (int03)",
   115                name:       "INT03",
   116                base:       0xFFE6,
   117                len:        0x0002,
   118                space:      "data",
   119                access:     "RW"
   120            }],
   121    
   122            ["INT04", {
   123                comment:    "Reserved Vector (int04)",
   124                name:       "INT04",
   125                base:       0xFFE8,
   126                len:        0x0002,
   127                space:      "data",
   128                access:     "RW"
   129            }],
   130    
   131            ["INT05", {
   132                comment:    "ADC10 Vector (int05)",
   133                name:       "INT05",
   134                base:       0xFFEA,
   135                len:        0x0002,
   136                space:      "data",
   137                access:     "RW"
   138            }],
   139    
   140            ["INT06", {
   141                comment:    "USCI_A0/B0 Transmit Vector (int06)",
   142                name:       "INT06",
   143                base:       0xFFEC,
   144                len:        0x0002,
   145                space:      "data",
   146                access:     "RW"
   147            }],
   148    
   149            ["INT07", {
   150                comment:    "USCI_A0/B0 Receive Vector (int07)",
   151                name:       "INT07",
   152                base:       0xFFEE,
   153                len:        0x0002,
   154                space:      "data",
   155                access:     "RW"
   156            }],
   157    
   158            ["INT08", {
   159                comment:    "Timer_A3 TBCCR1 Vector (int08)",
   160                name:       "INT08",
   161                base:       0xFFF0,
   162                len:        0x0002,
   163                space:      "data",
   164                access:     "RW"
   165            }],
   166    
   167            ["INT09", {
   168                comment:    "Timer_A3 TBCCR0 Vector (int09)",
   169                name:       "INT09",
   170                base:       0xFFF2,
   171                len:        0x0002,
   172                space:      "data",
   173                access:     "RW"
   174            }],
   175    
   176            ["INT10", {
   177                comment:    "Watchdog Vector (int10)",
   178                name:       "INT10",
   179                base:       0xFFF4,
   180                len:        0x0002,
   181                space:      "data",
   182                access:     "RW"
   183            }],
   184    
   185            ["INT11", {
   186                comment:    "Reserved Vector (int11)",
   187                name:       "INT11",
   188                base:       0xFFF6,
   189                len:        0x0002,
   190                space:      "data",
   191                access:     "RW"
   192            }],
   193    
   194            ["INT12", {
   195                comment:    "Timer_B3 TBCCR1 Vector (int12)",
   196                name:       "INT12",
   197                base:       0xFFF8,
   198                len:        0x0002,
   199                space:      "data",
   200                access:     "RW"
   201            }],
   202    
   203            ["INT13", {
   204                comment:    "Timer_B3 TBCCR0 Vector (int13)",
   205                name:       "INT13",
   206                base:       0xFFFA,
   207                len:        0x0002,
   208                space:      "data",
   209                access:     "RW"
   210            }],
   211    
   212            ["INT14", {
   213                comment:    "NMI Vector (int14)",
   214                name:       "INT14",
   215                base:       0xFFFC,
   216                len:        0x0002,
   217                space:      "data",
   218                access:     "RW"
   219            }],
   220    
   221            ["RESET", {
   222                comment:    "Reset Vector (int15)",
   223                name:       "RESET", 
   224                base:       0xFFFE,
   225                len:        0x0002,
   226                space:      "data",
   227                access:     "RW"
   228            }],
   229    
   230            ["INFOA", {
   231                comment:    "INFO Flash Memory Segment A",
   232                name:       "INFOA",
   233                base:       0x10C0,
   234                len:        0x0040,
   235                space:      "data",
   236                access:     "RW"
   237            }],
   238    
   239            ["INFOB", {
   240                comment:    "INFO Flash Memory Segment B",
   241                name:       "INFOB",
   242                base:       0x1080,
   243                len:        0x0040,
   244                space:      "data",
   245                access:     "RW"
   246            }],
   247    
   248            ["INFOC", {
   249                comment:    "INFO Flash Memory Segment C",
   250                name:       "INFOC",
   251                base:       0x1040,
   252                len:        0x0040,
   253                space:      "data",
   254                access:     "RW"
   255            }],
   256    
   257            ["INFOD", {
   258                comment:    "INFO Flash Memory Segment D",
   259                name:       "INFOD",
   260                base:       0x1000,
   261                len:        0x0040,
   262                space:      "data",
   263                access:     "RW"
   264            }],
   265        ];
   266    }