1    /*
     2     *  Copyright (c) 2014 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== DRA7XX.xdc ========
    15     *
    16     */
    17    
    18    /*!
    19     *  ======== DRA7XX ========
    20     *  The DRA7XX device data sheet module.
    21     *
    22     *  This module implements the xdc.platform.ICpuDataSheet interface and is 
    23     *  used by platforms to obtain "data sheet" information about this device.
    24     *
    25     */
    26    metaonly module DRA7XX inherits ti.catalog.ICpuDataSheet
    27    {
    28    instance:
    29        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
    30    
    31        override config string cpuCore           = "CM4";
    32        override config string isa               = "v7M4";
    33        override config string cpuCoreRevision   = "1.0";
    34        override config int    minProgUnitSize   = 1;
    35        override config int    minDataUnitSize   = 1;
    36        override config int    dataWordSize      = 4;
    37    
    38        /*!
    39         *  ======== memMap ========
    40         *  The memory map returned be getMemoryMap().
    41         */
    42        config xdc.platform.IPlatform.Memory memMap[string] = [
    43    
    44                /* 
    45                 * AMMU mapped L2 ROM virtual address
    46                 * Physical address is 0x55000000
    47                 */
    48                ["L2_ROM", {
    49                    name: "L2_ROM",
    50                    base: 0x00000000,
    51                    len:  0x00004000
    52                }],
    53    
    54                /* 
    55                 * AMMU mapped L2 RAM virtual address
    56                 * Physical address is 0x55020000
    57                 */
    58                ["L2_RAM", {
    59                    name: "L2_RAM",
    60                    base: 0x20000000, 
    61                len:  0x00010000
    62            }],
    63    
    64            /* 
    65                 * On-chip RAM memory 
    66                 */
    67                ["OCMC_RAM1", {
    68                    name: "OCMC_RAM1",
    69                    base: 0x40300000, 
    70                len:  0x00080000
    71            }],
    72    
    73            /* 
    74                 * On-chip RAM memory 
    75                 */
    76                ["OCMC_RAM2", {
    77                    name: "OCMC_RAM2",
    78                    base: 0x40400000, 
    79                len:  0x00100000
    80            }],
    81    
    82            /* 
    83                 * On-chip RAM memory 
    84                 */
    85                ["OCMC_RAM3", {
    86                    name: "OCMC_RAM3",
    87                    base: 0x40500000, 
    88                len:  0x00100000
    89            }]
    90        ];
    91    };
    92    /*
    93     *  @(#) ti.catalog.arm.cortexm4; 1, 0, 0,81; 3-22-2014 18:56:44; /db/ztree/library/trees/platform/platform-o48x/src/
    94     */
    95