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12 /*!
13 * ======== Timer0_B3 ========
14 * MSP430 Timer0_B3 timer
15 */
16 metaonly module Timer0_B3 inherits ITimer_B {
17
18 instance:
19 /*! TB0CTL, Timer_B3 Control Register */
20 config TBCTL_t TB0CTL = {
21 TBCLGRP : TBCLGRP_0,
22 CNTL : CNTL_0,
23 TBSSEL : TBSSEL_0,
24 ID : ID_0,
25 MC : MC_0,
26 TBCLR : TBCLR_OFF,
27 TBIE : TBIE_OFF,
28 TBIFG : TBIFG_OFF
29 };
30
31
32 /*! TB0CCTL0, Capture/Compare Control Register 0 */
33 config TBCCTLx_t TB0CCTL0 = {
34 CM : CM_0,
35 CCIS : CCIS_0,
36 SCS : SCS_OFF,
37 CLLD : CLLD_0,
38 CAP : CAP_OFF,
39 OUTMOD : OUTMOD_0,
40 CCIE : CCIE_OFF,
41 CCI : CCI_OFF,
42 OUT : OUT_OFF,
43 COV : COV_OFF,
44 CCIFG : CCIFG_OFF
45 };
46
47 /*! TB0CCTL1, Capture/Compare Control Register 1 */
48 config TBCCTLx_t TB0CCTL1 = {
49 CM : CM_0,
50 CCIS : CCIS_0,
51 SCS : SCS_OFF,
52 CLLD : CLLD_0,
53 CAP : CAP_OFF,
54 OUTMOD : OUTMOD_0,
55 CCIE : CCIE_OFF,
56 CCI : CCI_OFF,
57 OUT : OUT_OFF,
58 COV : COV_OFF,
59 CCIFG : CCIFG_OFF
60 };
61
62 /*! TB0CCTL2, Capture/Compare Control Register 2 */
63 config TBCCTLx_t TB0CCTL2 = {
64 CM : CM_0,
65 CCIS : CCIS_0,
66 SCS : SCS_OFF,
67 CLLD : CLLD_0,
68 CAP : CAP_OFF,
69 OUTMOD : OUTMOD_0,
70 CCIE : CCIE_OFF,
71 CCI : CCI_OFF,
72 OUT : OUT_OFF,
73 COV : COV_OFF,
74 CCIFG : CCIFG_OFF
75 };
76
77 /*! TB0CCR0, Timer_B Capture/Compare Register 0 */
78 config Bits16 TB0CCR0 = 0;
79 /*! TB0CCR1, Timer_B Capture/Compare Register 1 */
80 config Bits16 TB0CCR1 = 0;
81 /*! TB0CCR2, Timer_B Capture/Compare Register 2 */
82 config Bits16 TB0CCR2 = 0;
83
84 /*! Timer interrupt enables */
85 config regIntVect_t interruptSource[4];
86
87 /*! Determine if each Register needs to be forced set or not */
88 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
89 [
90 { register : "TB0CTL" , regForceSet : false },
91 { register : "TB0CCTL0" , regForceSet : false },
92 { register : "TB0CCTL1" , regForceSet : false },
93 { register : "TB0CCTL2" , regForceSet : false },
94 { register : "TB0CCR0" , regForceSet : false },
95 { register : "TB0CCR1" , regForceSet : false },
96 { register : "TB0CCR2" , regForceSet : false }
97 ];
98 }