1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
32
33 34 35
36
37 package ti.catalog.arm.cortexm4.tiva.ce;
38
39 import xdc.rov.ViewInfo;
40 import xdc.runtime.Assert;
41
42 /*!
43 * ======== Boot ========
44 * Stellaris M3 Boot Support.
45 *
46 * The Boot module supports boot initialization for the Stellaris M3 devices.
47 * A special boot init function is created based on the configuration
48 * settings for this module. This function is hooked into the
49 * xdc.runtime.Reset.fxns[] array and called very early at boot time (prior
50 * to cinit processing).
51 *
52 * The code to support the boot module is placed in a separate section
53 * named `".text:.bootCodeSection"` to allow placement of this section in
54 * the linker .cmd file if necessary. This section is a subsection of the
55 * `".text"` section so this code will be placed into the .text section unless
56 * explicitly placed, either through
57 * `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
58 * command file.
59 */
60 @Template("./Boot.xdt")
61 module Boot
62 {
63 metaonly struct ModuleView {
64 Bool configureClock;
65 Bool sysClockDivEnable;
66 String sysClockDiv;
67 Bool pwmClockDivEnable;
68 String pwmClockDiv;
69 String xtal;
70 String oscSrc;
71 Bool pllBypass;
72 Bool pllOutEnable;
73 Bool ioscDisable;
74 Bool moscDisable;
75 Bool configureLdo;
76 String ldoOut;
77 }
78
79 @Facet
80 metaonly config ViewInfo.Instance rovViewInfo =
81 ViewInfo.create({
82 viewMap: [
83 [
84 'Module',
85 {
86 type: ViewInfo.MODULE,
87 viewInitFxn: 'viewInitModule',
88 structName: 'ModuleView'
89 }
90 ],
91 ]
92 });
93
94
95 metaonly enum SysDiv {
96 SYSDIV_1 = 0x07800000, /*! CPU clock is osc/pll / 1 */
97 SYSDIV_2 = 0x00C00000, /*! CPU clock is osc/pll / 2 */
98 SYSDIV_3 = 0x01400000, /*! CPU clock is osc/pll / 3 */
99 SYSDIV_4 = 0x01C00000, /*! CPU clock is osc/pll / 4 */
100 SYSDIV_5 = 0x02400000, /*! CPU clock is osc/pll / 5 */
101 SYSDIV_6 = 0x02C00000, /*! CPU clock is osc/pll / 6 */
102 SYSDIV_7 = 0x03400000, /*! CPU clock is osc/pll / 7 */
103 SYSDIV_8 = 0x03C00000, /*! CPU clock is osc/pll / 8 */
104 SYSDIV_9 = 0x04400000, /*! CPU clock is osc/pll / 9 */
105 SYSDIV_10 = 0x04C00000, /*! CPU clock is osc/pll / 10 */
106 SYSDIV_11 = 0x05400000, /*! CPU clock is osc/pll / 11 */
107 SYSDIV_12 = 0x05C00000, /*! CPU clock is osc/pll / 12 */
108 SYSDIV_13 = 0x06400000, /*! CPU clock is osc/pll / 13 */
109 SYSDIV_14 = 0x06C00000, /*! CPU clock is osc/pll / 14 */
110 SYSDIV_15 = 0x07400000, /*! CPU clock is osc/pll / 15 */
111 SYSDIV_16 = 0x07C00000, /*! CPU clock is osc/pll / 16 */
112 SYSDIV_17 = 0x88400000, /*! CPU clock is osc/pll / 17 */
113 SYSDIV_18 = 0x88C00000, /*! CPU clock is osc/pll / 18 */
114 SYSDIV_19 = 0x89400000, /*! CPU clock is osc/pll / 19 */
115 SYSDIV_20 = 0x89C00000, /*! CPU clock is osc/pll / 20 */
116 SYSDIV_21 = 0x8A400000, /*! CPU clock is osc/pll / 21 */
117 SYSDIV_22 = 0x8AC00000, /*! CPU clock is osc/pll / 22 */
118 SYSDIV_23 = 0x8B400000, /*! CPU clock is osc/pll / 23 */
119 SYSDIV_24 = 0x8BC00000, /*! CPU clock is osc/pll / 24 */
120 SYSDIV_25 = 0x8C400000, /*! CPU clock is osc/pll / 25 */
121 SYSDIV_26 = 0x8CC00000, /*! CPU clock is osc/pll / 26 */
122 SYSDIV_27 = 0x8D400000, /*! CPU clock is osc/pll / 27 */
123 SYSDIV_28 = 0x8DC00000, /*! CPU clock is osc/pll / 28 */
124 SYSDIV_29 = 0x8E400000, /*! CPU clock is osc/pll / 29 */
125 SYSDIV_30 = 0x8EC00000, /*! CPU clock is osc/pll / 30 */
126 SYSDIV_31 = 0x8F400000, /*! CPU clock is osc/pll / 31 */
127 SYSDIV_32 = 0x8FC00000, /*! CPU clock is osc/pll / 32 */
128 SYSDIV_33 = 0x90400000, /*! CPU clock is osc/pll / 33 */
129 SYSDIV_34 = 0x90C00000, /*! CPU clock is osc/pll / 34 */
130 SYSDIV_35 = 0x91400000, /*! CPU clock is osc/pll / 35 */
131 SYSDIV_36 = 0x91C00000, /*! CPU clock is osc/pll / 36 */
132 SYSDIV_37 = 0x92400000, /*! CPU clock is osc/pll / 37 */
133 SYSDIV_38 = 0x92C00000, /*! CPU clock is osc/pll / 38 */
134 SYSDIV_39 = 0x93400000, /*! CPU clock is osc/pll / 39 */
135 SYSDIV_40 = 0x93C00000, /*! CPU clock is osc/pll / 40 */
136 SYSDIV_41 = 0x94400000, /*! CPU clock is osc/pll / 41 */
137 SYSDIV_42 = 0x94C00000, /*! CPU clock is osc/pll / 42 */
138 SYSDIV_43 = 0x95400000, /*! CPU clock is osc/pll / 43 */
139 SYSDIV_44 = 0x95C00000, /*! CPU clock is osc/pll / 44 */
140 SYSDIV_45 = 0x96400000, /*! CPU clock is osc/pll / 45 */
141 SYSDIV_46 = 0x96C00000, /*! CPU clock is osc/pll / 46 */
142 SYSDIV_47 = 0x97400000, /*! CPU clock is osc/pll / 47 */
143 SYSDIV_48 = 0x97C00000, /*! CPU clock is osc/pll / 48 */
144 SYSDIV_49 = 0x98400000, /*! CPU clock is osc/pll / 49 */
145 SYSDIV_50 = 0x98C00000, /*! CPU clock is osc/pll / 50 */
146 SYSDIV_51 = 0x99400000, /*! CPU clock is osc/pll / 51 */
147 SYSDIV_52 = 0x99C00000, /*! CPU clock is osc/pll / 52 */
148 SYSDIV_53 = 0x9A400000, /*! CPU clock is osc/pll / 53 */
149 SYSDIV_54 = 0x9AC00000, /*! CPU clock is osc/pll / 54 */
150 SYSDIV_55 = 0x9B400000, /*! CPU clock is osc/pll / 55 */
151 SYSDIV_56 = 0x9BC00000, /*! CPU clock is osc/pll / 56 */
152 SYSDIV_57 = 0x9C400000, /*! CPU clock is osc/pll / 57 */
153 SYSDIV_58 = 0x9CC00000, /*! CPU clock is osc/pll / 58 */
154 SYSDIV_59 = 0x9D400000, /*! CPU clock is osc/pll / 59 */
155 SYSDIV_60 = 0x9DC00000, /*! CPU clock is osc/pll / 60 */
156 SYSDIV_61 = 0x9E400000, /*! CPU clock is osc/pll / 61 */
157 SYSDIV_62 = 0x9EC00000, /*! CPU clock is osc/pll / 62 */
158 SYSDIV_63 = 0x9F400000, /*! CPU clock is osc/pll / 63 */
159 SYSDIV_64 = 0x9FC00000, /*! CPU clock is osc/pll / 64 */
160 SYSDIV_2_5 = 0xC1000000, /*! CPU clock is osc/pll / 2.5 */
161 SYSDIV_3_5 = 0xC1800000, /*! CPU clock is osc/pll / 3.5 */
162 SYSDIV_4_5 = 0xC2000000, /*! CPU clock is osc/pll / 4.5 */
163 SYSDIV_5_5 = 0xC2800000, /*! CPU clock is osc/pll / 5.5 */
164 SYSDIV_6_5 = 0xC3000000, /*! CPU clock is osc/pll / 6.5 */
165 SYSDIV_7_5 = 0xC3800000, /*! CPU clock is osc/pll / 7.5 */
166 SYSDIV_8_5 = 0xC4000000, /*! CPU clock is osc/pll / 8.5 */
167 SYSDIV_9_5 = 0xC4800000, /*! CPU clock is osc/pll / 9.5 */
168 SYSDIV_10_5 = 0xC5000000, /*! CPU clock is osc/pll / 10.5 */
169 SYSDIV_11_5 = 0xC5800000, /*! CPU clock is osc/pll / 11.5 */
170 SYSDIV_12_5 = 0xC6000000, /*! CPU clock is osc/pll / 12.5 */
171 SYSDIV_13_5 = 0xC6800000, /*! CPU clock is osc/pll / 13.5 */
172 SYSDIV_14_5 = 0xC7000000, /*! CPU clock is osc/pll / 14.5 */
173 SYSDIV_15_5 = 0xC7800000, /*! CPU clock is osc/pll / 15.5 */
174 SYSDIV_16_5 = 0xC8000000, /*! CPU clock is osc/pll / 16.5 */
175 SYSDIV_17_5 = 0xC8800000, /*! CPU clock is osc/pll / 17.5 */
176 SYSDIV_18_5 = 0xC9000000, /*! CPU clock is osc/pll / 18.5 */
177 SYSDIV_19_5 = 0xC9800000, /*! CPU clock is osc/pll / 19.5 */
178 SYSDIV_20_5 = 0xCA000000, /*! CPU clock is osc/pll / 20.5 */
179 SYSDIV_21_5 = 0xCA800000, /*! CPU clock is osc/pll / 21.5 */
180 SYSDIV_22_5 = 0xCB000000, /*! CPU clock is osc/pll / 22.5 */
181 SYSDIV_23_5 = 0xCB800000, /*! CPU clock is osc/pll / 23.5 */
182 SYSDIV_24_5 = 0xCC000000, /*! CPU clock is osc/pll / 24.5 */
183 SYSDIV_25_5 = 0xCC800000, /*! CPU clock is osc/pll / 25.5 */
184 SYSDIV_26_5 = 0xCD000000, /*! CPU clock is osc/pll / 26.5 */
185 SYSDIV_27_5 = 0xCD800000, /*! CPU clock is osc/pll / 27.5 */
186 SYSDIV_28_5 = 0xCE000000, /*! CPU clock is osc/pll / 28.5 */
187 SYSDIV_29_5 = 0xCE800000, /*! CPU clock is osc/pll / 29.5 */
188 SYSDIV_30_5 = 0xCF000000, /*! CPU clock is osc/pll / 30.5 */
189 SYSDIV_31_5 = 0xCF800000, /*! CPU clock is osc/pll / 31.5 */
190 SYSDIV_32_5 = 0xD0000000, /*! CPU clock is osc/pll / 32.5 */
191 SYSDIV_33_5 = 0xD0800000, /*! CPU clock is osc/pll / 33.5 */
192 SYSDIV_34_5 = 0xD1000000, /*! CPU clock is osc/pll / 34.5 */
193 SYSDIV_35_5 = 0xD1800000, /*! CPU clock is osc/pll / 35.5 */
194 SYSDIV_36_5 = 0xD2000000, /*! CPU clock is osc/pll / 36.5 */
195 SYSDIV_37_5 = 0xD2800000, /*! CPU clock is osc/pll / 37.5 */
196 SYSDIV_38_5 = 0xD3000000, /*! CPU clock is osc/pll / 38.5 */
197 SYSDIV_39_5 = 0xD3800000, /*! CPU clock is osc/pll / 39.5 */
198 SYSDIV_40_5 = 0xD4000000, /*! CPU clock is osc/pll / 40.5 */
199 SYSDIV_41_5 = 0xD4800000, /*! CPU clock is osc/pll / 41.5 */
200 SYSDIV_42_5 = 0xD5000000, /*! CPU clock is osc/pll / 42.5 */
201 SYSDIV_43_5 = 0xD5800000, /*! CPU clock is osc/pll / 43.5 */
202 SYSDIV_44_5 = 0xD6000000, /*! CPU clock is osc/pll / 44.5 */
203 SYSDIV_45_5 = 0xD6800000, /*! CPU clock is osc/pll / 45.5 */
204 SYSDIV_46_5 = 0xD7000000, /*! CPU clock is osc/pll / 46.5 */
205 SYSDIV_47_5 = 0xD7800000, /*! CPU clock is osc/pll / 47.5 */
206 SYSDIV_48_5 = 0xD8000000, /*! CPU clock is osc/pll / 48.5 */
207 SYSDIV_49_5 = 0xD8800000, /*! CPU clock is osc/pll / 49.5 */
208 SYSDIV_50_5 = 0xD9000000, /*! CPU clock is osc/pll / 50.5 */
209 SYSDIV_51_5 = 0xD9800000, /*! CPU clock is osc/pll / 51.5 */
210 SYSDIV_52_5 = 0xDA000000, /*! CPU clock is osc/pll / 52.5 */
211 SYSDIV_53_5 = 0xDA800000, /*! CPU clock is osc/pll / 53.5 */
212 SYSDIV_54_5 = 0xDB000000, /*! CPU clock is osc/pll / 54.5 */
213 SYSDIV_55_5 = 0xDB800000, /*! CPU clock is osc/pll / 55.5 */
214 SYSDIV_56_5 = 0xDC000000, /*! CPU clock is osc/pll / 56.5 */
215 SYSDIV_57_5 = 0xDC800000, /*! CPU clock is osc/pll / 57.5 */
216 SYSDIV_58_5 = 0xDD000000, /*! CPU clock is osc/pll / 58.5 */
217 SYSDIV_59_5 = 0xDD800000, /*! CPU clock is osc/pll / 59.5 */
218 SYSDIV_60_5 = 0xDE000000, /*! CPU clock is osc/pll / 60.5 */
219 SYSDIV_61_5 = 0xDE800000, /*! CPU clock is osc/pll / 61.5 */
220 SYSDIV_62_5 = 0xDF000000, /*! CPU clock is osc/pll / 62.5 */
221 SYSDIV_63_5 = 0xDF800000 /*! CPU clock is osc/pll / 63.5 */
222 }
223
224 metaonly enum PwmDiv {
225 PWMDIV_1 = 0x00000000, /*! PWM clock /1 */
226 PWMDIV_2 = 0x00100000, /*! PWM clock /2 */
227 PWMDIV_4 = 0x00120000, /*! PWM clock /4 */
228 PWMDIV_8 = 0x00140000, /*! PWM clock /8 */
229 PWMDIV_16 = 0x00160000, /*! PWM clock /16 */
230 PWMDIV_32 = 0x00180000, /*! PWM clock /32 */
231 PWMDIV_64 = 0x001A0000 /*! PWM clock /64 */
232 }
233
234 metaonly enum XtalFreq {
235 XTAL_1MHZ = 0x00000000, /*! 1.0 MHz */
236 XTAL_1_84MHZ = 0x00000040, /*! 1.8432 MHz */
237 XTAL_2MHZ = 0x00000080, /*! 2.0 MHz */
238 XTAL_2_45MHZ = 0x000000C0, /*! 2.4576 MHz */
239 XTAL_3_57MHZ = 0x00000100, /*! 3.579545 MHz */
240 XTAL_3_68MHZ = 0x00000140, /*! 3.6864 MHz */
241 XTAL_4MHZ = 0x00000180, /*! 4.0 MHz */
242 XTAL_4_09MHZ = 0x000001C0, /*! 4.096 MHz */
243 XTAL_4_91MHZ = 0x00000200, /*! 4.9152 MHz */
244 XTAL_5MHZ = 0x00000240, /*! 5.0 MHz */
245 XTAL_5_12MHZ = 0x00000280, /*! 5.12 MHz */
246 XTAL_6MHZ = 0x000002C0, /*! 6.0 MHz */
247 XTAL_6_14MHZ = 0x00000300, /*! 6.144 MHz */
248 XTAL_7_37MHZ = 0x00000340, /*! 7.3728 MHz */
249 XTAL_8MHZ = 0x00000380, /*! 8.0 MHz */
250 XTAL_8_19MHZ = 0x000003C0, /*! 8.192 MHz */
251 XTAL_10MHZ = 0x00000400, /*! 10.0 MHz (USB) */
252 XTAL_12MHZ = 0x00000440, /*! 12.0 MHz (USB) */
253 XTAL_12_2MHZ = 0x00000480, /*! 12.288 MHz */
254 XTAL_13_5MHZ = 0x000004C0, /*! 13.56 MHz */
255 XTAL_14_3MHZ = 0x00000500, /*! 14.31818 MHz */
256 XTAL_16MHZ = 0x00000540, /*! 16.0 MHz (USB) */
257 XTAL_16_3MHZ = 0x00000580, /*! 16.384 MHz */
258 XTAL_18MHZ = 0x000005C0, /*! 18.0 MHz */
259 XTAL_20MHZ = 0x00000600, /*! 20.0 MHz */
260 XTAL_24MHZ = 0x00000640, /*! 24.0 MHz */
261 XTAL_25MHZ = 0x00000680 /*! 25.0 MHz */
262 }
263
264 metaonly enum OscSrc {
265 OSCSRC_MAIN = 0x00000000, /*! Main oscillator */
266 OSCSRC_INT = 0x00000010, /*! Internal oscillator */
267 OSCSRC_INT4 = 0x00000020, /*! Internal oscillator / 4 */
268 OSCSRC_INT30 = 0x00000030, /*! Internal 30 KHz oscillator */
269 OSCSRC_EXT4_19 = 0x80000028, /*! External 4.19 MHz */
270 OSCSRC_EXT32 = 0x80000038 /*! External 32 KHz */
271 }
272
273 metaonly enum LdoOut {
274 LDOPCTL_2_55V = 0x0000001F, /*! LDO output of 2.55V */
275 LDOPCTL_2_60V = 0x0000001E, /*! LDO output of 2.60V */
276 LDOPCTL_2_65V = 0x0000001D, /*! LDO output of 2.65V */
277 LDOPCTL_2_70V = 0x0000001C, /*! LDO output of 2.70V */
278 LDOPCTL_2_75V = 0x0000001B, /*! LDO output of 2.75V */
279 LDOPCTL_2_25V = 0x00000005, /*! LDO output of 2.25V */
280 LDOPCTL_2_30V = 0x00000004, /*! LDO output of 2.30V */
281 LDOPCTL_2_35V = 0x00000003, /*! LDO output of 2.35V */
282 LDOPCTL_2_40V = 0x00000002, /*! LDO output of 2.40V */
283 LDOPCTL_2_45V = 0x00000001, /*! LDO output of 2.45V */
284 LDOPCTL_2_50V = 0x00000000 /*! LDO output of 2.50V */
285 }
286
287 metaonly enum VcoFreq {
288 VCO_600 = 0xF2000000, /*! VCO is 600 MHz */
289 VCO_480 = 0xF1000000, /*! VCO is 480 MHz */
290 VCO_320 = 0xF0000000 /*! VCO is 320 MHz */
291 }
292
293 /*! Asserted in Boot_sysCtlClockSet */
294 config Assert.Id A_mustUseEnhancedClockMode = {
295 msg: "A_mustUseEnhancedClockMode: This device requires the Enhanced Clock Mode."
296 };
297
298 /*! Asserted in Boot_sysCtlClockFreqSet */
299 config Assert.Id A_mustNotUseEnhancedClockMode = {
300 msg: "A_mustNotUseEnhancedClockMode: This device does not support the Enhanced Clock Mode."
301 };
302
303
304 /*!
305 * Clock configuration flag, default is false.
306 *
307 * Set to true to automatically configure the Clock.
308 */
309 metaonly config Bool configureClock = false;
310
311 /*! SYS Clock Divisor */
312 metaonly config SysDiv sysClockDiv = SYSDIV_1;
313
314 /*! PWM Clock Divisor */
315 metaonly config PwmDiv pwmClockDiv = PWMDIV_1;
316
317 /*! Crystal Value */
318 metaonly config XtalFreq xtal = XTAL_1MHZ;
319
320 /*! Oscillator Source */
321 metaonly config OscSrc oscSrc = OSCSRC_MAIN;
322
323 /*! VCO frequency */
324 metaonly config VcoFreq vcoFreq = VCO_320;
325
326 /*! PLL Bypass flag */
327 metaonly config Bool pllBypass = false;
328
329 /*! PLL Output Enable flag */
330 metaonly config Bool pllOutEnable = false;
331
332 /*! Internal Oscillator Disable flag */
333 metaonly config Bool ioscDisable = false;
334
335 /*! Main Oscillator Disable flag */
336 metaonly config Bool moscDisable = false;
337
338 /*!
339 * LDO configuration flag, default is false.
340 *
341 * Set to true to automatically configure the LDO.
342 */
343 metaonly config Bool configureLdo = false;
344
345 /*!
346 * LDO VADJ setting, default is 2.5V
347 */
348 metaonly config LdoOut ldoOut = LDOPCTL_2_50V;
349
350 /*!
351 * Enahnced Clocking Mode.
352 *
353 * Must be set to true for OneMCU devices that support this feature.
354 */
355 metaonly config Bool enhancedClockMode = false;
356
357 /*!
358 * Desired CPU Clock Frequency in Hz.
359 *
360 * Configurable only on devices with "Enhanced Clocking Mode" support.
361 */
362 metaonly config UInt cpuFrequency = 40000000;
363
364 365 366 367 368 369 370 371 372
373 @DirectCall
374 Void sysCtlClockSet(ULong ulConfig);
375
376 377 378 379 380 381 382 383 384 385 386 387 388 389 390
391 @DirectCall
392 ULong sysCtlClockFreqSet(ULong ulConfig, ULong ulSysClock);
393
394 395 396 397 398 399 400
401 @DirectCall
402 Void sysCtlLDOSet(ULong ulVoltage);
403
404 /*!
405 * @_nodoc
406 * ======== registerFreqListener ========
407 * Register a module to be notified whenever the frequency changes.
408 *
409 * The registered module must have a function named 'fireFrequencyUpdate'
410 * which takes the new frequency as an argument.
411 */
412 function registerFreqListener();
413
414 internal:
415
416 417 418 419 420 421
422 Void sysCtlClockSetI(ULong ulConfig);
423
424 425 426 427 428 429 430 431 432 433
434 ULong sysCtlClockFreqSetI(ULong ulConfig, ULong ulSysClock);
435
436 437 438 439 440 441
442 Void sysCtlDelayI(ULong ulCount);
443
444 445 446 447 448 449 450 451
452 Void init();
453
454 /*!
455 * computed RCC value based on settings
456 */
457 metaonly config UInt ulConfig;
458
459 /*!
460 * computed cpu frequency based on clock settings
461 */
462 metaonly config UInt computedCpuFrequency;
463
464 };