1 2 3 4 5 6 7 8 9 10 11
12 import ti.catalog.msp430.peripherals.clock.IClock;
13
14 /*!
15 * Enhanced Univerisal Serial Communication Interface A1
16 */
17 metaonly module EUSCI_A1 inherits IEUSCI {
18
19 20 21
22 create(IClock.Instance clock);
23
24 instance:
25 /*! @_nodoc */
26 config IClock.Instance clock;
27
28 /*!
29 * ======== baseAddr ========
30 * Address of the peripheral's control register.
31 *
32 * A peripheral's registers are commonly accessed through a structure
33 * that defines the offsets of a particular register from the lowest
34 * address mapped to a peripheral. That lowest address is specified by
35 * this parameter.
36 */
37 config UInt baseAddr;
38
39 /*! USI interrupt enables */
40 config regIntVect_t interruptSource[2];
41
42 /*! Determine if each Register needs to be forced set or not */
43 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
44 [
45 ];
46 }