1 2 3 4 5 6 7 8 9 10 11
12 /*!
13 * ======== IE1 ========
14 * MSP430 Interrupt Enable Register 1
15 */
16 metaonly module IE1 inherits xdc.platform.IPeripheral {
17
18 enum NMIIE_t {
19 NMIIE_OFF = 0x00, /*! Interrupt not enabled */
20 NMIIE = 0x10 /*! Interrupt enabled */
21 };
22
23 enum WDTIE_t {
24 WDTIE_OFF = 0x00, /*! Interrupt not enabled */
25 WDTIE = 0x01 /*! Interrupt enabled */
26 };
27
28 enum OFIE_t {
29 OFIE_OFF = 0x00, /*! Interrupt not enabled */
30 OFIE = 0x02 /*! Interrupt enabled */
31 };
32
33 enum ACCVIE_t {
34 ACCVIE_OFF = 0x00, /*! Interrupt not enabled */
35 ACCVIE = 0x20 /*! Interrupt enabled */
36 };
37
38 enum NMIIFG_t {
39 NMIIFG_OFF = 0x00, /*! No interrupt pending */
40 NMIIFG = 0x10 /*! Interrupt pending */
41 };
42
43 enum WDTIFG_t {
44 WDTIFG_OFF = 0x00, /*! No interrupt pending */
45 WDTIFG = 0x01 /*! Interrupt pending */
46 };
47
48 enum OFIFG_t {
49 OFIFG_OFF = 0x00, /*! No interrupt pending */
50 OFIFG = 0x02 /*! Interrupt pending */
51 };
52
53 enum ACCVIFG_t {
54 ACCVIFG_OFF = 0x00, /*! No interrupt pending */
55 ACCVIFG = 0x20 /*! Interrupt pending */
56 };
57
58
59 struct IE1_t {
60 ACCVIE_t ACCVIE; /*! Flash memory access violation interrupt
61 * enable. This bit enables the ACCVIFG interrupt.
62 * 0 Interrupt disabled
63 * 1 Interrupt enabled */
64 NMIIE_t NMIIE; /*! NMI interrupt enable. This bit enables
65 *the NMI interrupt.
66 * 0 Interrupt disabled
67 * 1 Interrupt enabled */
68 OFIE_t OFIE; /*! Oscillator fault flag interrupt enable
69 *This bit enables the OFIFG interrupt.
70 * 0 Interrupt disabled
71 * 1 Interrupt enabled */
72 WDTIE_t WDTIE; /*! Watchdog timer+ interrupt enable. This
73 *bit enables the WDTIFG interrupt for
74 *interval timer mode. It is not necessary
75 *to set this bit for watchdog mode.
76 * 0 Interrupt disabled
77 * 1 Interrupt enabled */
78 }
79
80
81 struct IFG1_t {
82 ACCVIFG_t ACCVIFG; /*! Flash memory access violation interrupt
83 * flag.
84 * 0 No interrupt pending
85 * 1 Interrupt pending */
86 NMIIFG_t NMIIFG; /*! NMI interrupt flag.
87 * 0 No interrupt pending
88 * 1 Interrupt pending */
89 OFIFG_t OFIFG; /*! Oscillator fault interrupt flag
90 * 0 No interrupt pending
91 * 1 Interrupt pending */
92 WDTIFG_t WDTIFG; /*! Watchdog timer+ interrupt flag.
93 * 0 No interrupt pending
94 * 1 Interrupt pending */
95 }
96
97 /*!
98 * ======== regIntVect_t ========
99 * Interrupt vector description
100 *
101 * Type to describe a single interrupt vector pin and all its possible
102 * configurations.
103 *
104 * @see #regIntVect_t
105 */
106 struct regIntVect_t {
107 String registerName;
108 String registerDescription;
109 String isrToggleString;
110 String priorityName;
111 Bool interruptEnable;
112 Bool interruptHandler;
113 Int priority;
114 }
115
116 /*!
117 * ======== ForceSetDefaultRegister_t ========
118 * Force Set Default Register
119 *
120 * Type to store if each register needs to be forced initialized
121 * even if the register is in default state.
122 *
123 * @see #ForceSetDefaultRegister_t
124 */
125 struct ForceSetDefaultRegister_t {
126 String register;
127 Bool regForceSet;
128 }
129
130 instance:
131 /*! IE1 interrupt enables
132 */
133 config regIntVect_t interruptSource[8];
134
135 /*! IE1, Interrupt Enable Register 1 */
136 config IE1_t IE1 = {
137 ACCVIE : ACCVIE_OFF,
138 NMIIE : NMIIE_OFF,
139 OFIE : OFIE_OFF,
140 WDTIE : WDTIE_OFF
141 };
142
143 /*! IFG1, Interrupt Flag Register 1 */
144 config IFG1_t IFG1 = {
145 ACCVIFG : ACCVIFG_OFF,
146 NMIIFG : NMIIFG_OFF,
147 OFIFG : OFIFG_OFF,
148 WDTIFG : WDTIFG_OFF
149 };
150
151 /*!
152 * ======== getWDTIE ========
153 * Gets WDTIE bit
154 *
155 * @see #getWDTIE
156 */
157 Bool getWDTIE();
158
159 /*!
160 * ======== setWDTIE ========
161 * Sets WDTIE bit
162 *
163 * @see #setWDTIE
164 */
165 Bool setWDTIE(Bool set);
166
167 /*!
168 * ======== getWDTIFG ========
169 * Gets WDTIFG bit
170 *
171 * @see #getWDTIFG
172 */
173 Bool getWDTIFG();
174
175 /*!
176 * ======== setWDTIFG ========
177 * Sets WDTIFG bit
178 *
179 * @see #setWDTIFG
180 */
181 Bool setWDTIFG(Bool set);
182
183 /*!
184 * ======== getOFIE ========
185 * Gets OFIE bit
186 *
187 * @see #getOFIE
188 */
189 Bool getOFIE();
190
191 /*!
192 * ======== setOFIE ========
193 * Sets OFIE bit
194 *
195 * @see #setOFIE
196 */
197 Bool setOFIE(Bool set);
198
199 /*!
200 * ======== getOFIFG ========
201 * Gets OFIFG bit
202 *
203 * @see #getOFIFG
204 */
205 Bool getOFIFG();
206
207 /*!
208 * ======== setOFIFG ========
209 * Sets OFIFG bit
210 *
211 * @see #setOFIFG
212 */
213 Bool setOFIFG(Bool set);
214
215 /*!
216 * ======== getNMIIE ========
217 * Gets NMIIE bit
218 *
219 * @see #getNMIIE
220 */
221 Bool getNMIIE();
222
223 /*!
224 * ======== setNMIIE ========
225 * Sets NMIIE bit
226 *
227 * @see #setNMIIE
228 */
229 Bool setNMIIE(Bool set);
230
231 /*!
232 * ======== getNMIIFG ========
233 * Gets NMIIFG bit
234 *
235 * @see #getNMIIFG
236 */
237 Bool getNMIIFG();
238
239 /*!
240 * ======== setNMIIFG ========
241 * Sets NMIIFG bit
242 *
243 * @see #setNMIIFG
244 */
245 Bool setNMIIFG(Bool set);
246
247 /*!
248 * ======== getACCVIE ========
249 * Gets ACCVIE bit
250 *
251 * @see #getACCVIE
252 */
253 Bool getACCVIE();
254
255 /*!
256 * ======== setACCVIE ========
257 * Sets ACCVIE bit
258 *
259 * @see #setACCVIE
260 */
261 Bool setACCVIE(Bool set);
262
263 /*!
264 * ======== getACCVIFG ========
265 * Gets ACCVIFG bit
266 *
267 * @see #getACCVIFG
268 */
269 Bool getACCVIFG();
270
271 /*!
272 * ======== setACCVIFG ========
273 * Sets ACCVIFG bit
274 *
275 * @see #setACCVIFG
276 */
277 Bool setACCVIFG(Bool set);
278
279 /*! Determine if each Register needs to be forced set or not */
280 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
281 [
282 { register : "IE1" , regForceSet : false },
283 { register : "IFG1" , regForceSet : false },
284 ];
285 }