1 2 3 4 5 6 7 8 9 10 11
12 import ti.catalog.msp430.peripherals.adc.ADC10 as ADC10;
13
14 /*!
15 * ======== GPIO for MSP430G2x33 ========
16 * MSP430 General Purpose Input Output Ports
17 */
18 metaonly module GPIO_MSP430G2x33 inherits IGPIO {
19 /*!
20 * ======== create ========
21 * Create an instance of this peripheral. Use a customized
22 * init function so that we can get access to the ADC10
23 * instance.
24 */
25 create(ADC10.Instance adc10);
26
27 instance:
28 /*! @_nodoc */
29 config ADC10.Instance adc10;
30
31 /*! Define an array to describe all device pins. The 1st dimension
32 * denotes the port, the second the pin on that port. On an
33 * MSP430G2x33 device, there are 3 x 8 = 24 pins total.
34 */
35
36 37
38 39
40 config DevicePin_t devicePins[3][8];
41
42 /*! Implementation of Device Pin Functional Configuration */
43 override config DevicePinFunctionSetting_t devicePinSetting[3][8];
44
45 /*! Determine if each Register needs to be forced set or not */
46 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
47 [
48 { register : "P1OUT" , regForceSet : true },
49 { register : "P1SEL" , regForceSet : false },
50 { register : "P1SEL2", regForceSet : false },
51 { register : "P1DIR" , regForceSet : false },
52 { register : "P1REN" , regForceSet : false },
53 { register : "P1IES" , regForceSet : true },
54 { register : "P1IFG" , regForceSet : true },
55 { register : "P1IE" , regForceSet : false },
56 { register : "P2OUT" , regForceSet : true },
57 { register : "P2SEL" , regForceSet : false },
58 { register : "P2SEL2", regForceSet : false },
59 { register : "P2DIR" , regForceSet : false },
60 { register : "P2REN" , regForceSet : false },
61 { register : "P2IES" , regForceSet : true },
62 { register : "P2IFG" , regForceSet : true },
63 { register : "P2IE" , regForceSet : false },
64 { register : "P3OUT" , regForceSet : true },
65 { register : "P3SEL" , regForceSet : false },
66 { register : "P3SEL2", regForceSet : false },
67 { register : "P3DIR" , regForceSet : false },
68 { register : "P3REN" , regForceSet : false },
69 ];
70
71 72 73 74 75 76
77
78 /*! Port 1 Output Register */
79 config GpioBits8PxOut_t P1OUT = {
80 Bit0 : BIT0_OFF,
81 Bit1 : BIT1_OFF,
82 Bit2 : BIT2_OFF,
83 Bit3 : BIT3_OFF,
84 Bit4 : BIT4_OFF,
85 Bit5 : BIT5_OFF,
86 Bit6 : BIT6_OFF,
87 Bit7 : BIT7_OFF
88 };
89
90 /*! Port 1 Port Select Register */
91 config GpioBits8PxSel_t P1SEL = {
92 Bit0 : BIT0_OFF,
93 Bit1 : BIT1_OFF,
94 Bit2 : BIT2_OFF,
95 Bit3 : BIT3_OFF,
96 Bit4 : BIT4_OFF,
97 Bit5 : BIT5_OFF,
98 Bit6 : BIT6_OFF,
99 Bit7 : BIT7_OFF
100 };
101
102 /*! Port 1 Port Select 2 Register */
103 config GpioBits8PxSel_t P1SEL2 = {
104 Bit0 : BIT0_OFF,
105 Bit1 : BIT1_OFF,
106 Bit2 : BIT2_OFF,
107 Bit3 : BIT3_OFF,
108 Bit4 : BIT4_OFF,
109 Bit5 : BIT5_OFF,
110 Bit6 : BIT6_OFF,
111 Bit7 : BIT7_OFF
112 };
113
114 /*! Port 1 Direction Register */
115 config GpioBits8PxDir_t P1DIR = {
116 Bit0 : BIT0_OFF,
117 Bit1 : BIT1_OFF,
118 Bit2 : BIT2_OFF,
119 Bit3 : BIT3_OFF,
120 Bit4 : BIT4_OFF,
121 Bit5 : BIT5_OFF,
122 Bit6 : BIT6_OFF,
123 Bit7 : BIT7_OFF
124 };
125
126 /*! Port 1 Resistor Enable Register */
127 config GpioBits8PxRen_t P1REN = {
128 Bit0 : BIT0_OFF,
129 Bit1 : BIT1_OFF,
130 Bit2 : BIT2_OFF,
131 Bit3 : BIT3_OFF,
132 Bit4 : BIT4_OFF,
133 Bit5 : BIT5_OFF,
134 Bit6 : BIT6_OFF,
135 Bit7 : BIT7_OFF
136 };
137
138 /*! Port 2 Output Register */
139 config GpioBits8PxOut_t P2OUT = {
140 Bit0 : BIT0_OFF,
141 Bit1 : BIT1_OFF,
142 Bit2 : BIT2_OFF,
143 Bit3 : BIT3_OFF,
144 Bit4 : BIT4_OFF,
145 Bit5 : BIT5_OFF,
146 Bit6 : BIT6_OFF,
147 Bit7 : BIT7_OFF
148 };
149
150 /*! Port 2 Port Select Register */
151 config GpioBits8PxSel_t P2SEL = {
152 Bit0 : BIT0_OFF,
153 Bit1 : BIT1_OFF,
154 Bit2 : BIT2_OFF,
155 Bit3 : BIT3_OFF,
156 Bit4 : BIT4_OFF,
157 Bit5 : BIT5_OFF,
158 Bit6 : BIT6,
159 Bit7 : BIT7
160 };
161
162 /*! Port 2 Port Select 2 Register */
163 config GpioBits8PxSel2_t P2SEL2 = {
164 Bit0 : BIT0_OFF,
165 Bit1 : BIT1_OFF,
166 Bit2 : BIT2_OFF,
167 Bit3 : BIT3_OFF,
168 Bit4 : BIT4_OFF,
169 Bit5 : BIT5_OFF,
170 Bit6 : BIT6_OFF,
171 Bit7 : BIT7_OFF
172 };
173
174 /*! Port 2 Direction Register */
175 config GpioBits8PxDir_t P2DIR = {
176 Bit0 : BIT0_OFF,
177 Bit1 : BIT1_OFF,
178 Bit2 : BIT2_OFF,
179 Bit3 : BIT3_OFF,
180 Bit4 : BIT4_OFF,
181 Bit5 : BIT5_OFF,
182 Bit6 : BIT6_OFF,
183 Bit7 : BIT7_OFF
184 };
185
186 /*! Port 2 Resistor Enable Register */
187 config GpioBits8PxRen_t P2REN = {
188 Bit0 : BIT0_OFF,
189 Bit1 : BIT1_OFF,
190 Bit2 : BIT2_OFF,
191 Bit3 : BIT3_OFF,
192 Bit4 : BIT4_OFF,
193 Bit5 : BIT5_OFF,
194 Bit6 : BIT6_OFF,
195 Bit7 : BIT7_OFF
196 };
197
198 /*! Port 3 Output Register */
199 config GpioBits8PxOut_t P3OUT = {
200 Bit0 : BIT0_OFF,
201 Bit1 : BIT1_OFF,
202 Bit2 : BIT2_OFF,
203 Bit3 : BIT3_OFF,
204 Bit4 : BIT4_OFF,
205 Bit5 : BIT5_OFF,
206 Bit6 : BIT6_OFF,
207 Bit7 : BIT7_OFF
208 };
209
210 /*! Port 3 Port Select Register */
211 config GpioBits8PxSel_t P3SEL = {
212 Bit0 : BIT0_OFF,
213 Bit1 : BIT1_OFF,
214 Bit2 : BIT2_OFF,
215 Bit3 : BIT3_OFF,
216 Bit4 : BIT4_OFF,
217 Bit5 : BIT5_OFF,
218 Bit6 : BIT6_OFF,
219 Bit7 : BIT7_OFF
220 };
221
222 /*! Port 3 Port Select 2 Register */
223 config GpioBits8PxSel2_t P3SEL2 = {
224 Bit0 : BIT0_OFF,
225 Bit1 : BIT1_OFF,
226 Bit2 : BIT2_OFF,
227 Bit3 : BIT3_OFF,
228 Bit4 : BIT4_OFF,
229 Bit5 : BIT5_OFF,
230 Bit6 : BIT6_OFF,
231 Bit7 : BIT7_OFF
232 };
233
234 /*! Port 3 Direction Register */
235 config GpioBits8PxDir_t P3DIR = {
236 Bit0 : BIT0_OFF,
237 Bit1 : BIT1_OFF,
238 Bit2 : BIT2_OFF,
239 Bit3 : BIT3_OFF,
240 Bit4 : BIT4_OFF,
241 Bit5 : BIT5_OFF,
242 Bit6 : BIT6_OFF,
243 Bit7 : BIT7_OFF
244 };
245
246 /*! Port 3 Resistor Enable Register */
247 config GpioBits8PxRen_t P3REN = {
248 Bit0 : BIT0_OFF,
249 Bit1 : BIT1_OFF,
250 Bit2 : BIT2_OFF,
251 Bit3 : BIT3_OFF,
252 Bit4 : BIT4_OFF,
253 Bit5 : BIT5_OFF,
254 Bit6 : BIT6_OFF,
255 Bit7 : BIT7_OFF
256 };
257 }