1 2 3 4 5 6 7 8 9 10 11
12 import ti.catalog.msp430.peripherals.clock.CS as CS;
13
14 /*!
15 * ======== GPIO for MSP430FR5738_34_30_28_24_20 ========
16 * MSP430 General Purpose Input Output Ports
17 */
18 metaonly module GPIO_MSP430FR5738_34_30_28_24_20 inherits IGPIO {
19 /*!
20 * ======== create ========
21 * Create an instance of this peripheral. Use a customized
22 * init function so that we can get access to the CS
23 * instances.
24 */
25 create(CS.Instance clock);
26
27 instance:
28 /*! @_nodoc */
29 config CS.Instance clock;
30
31 /*! Define an array to describe all device pins. The 1st dimension
32 * denotes the port, the second the pin on that port. On an
33 * MSP430FR57xx device, there are 3 + 2 = 10 pins total.
34 */
35
36 37
38 config DevicePin_t devicePins[3][8];
39
40 /*! Implementation of Device Pin Functional Configuration */
41 override config DevicePinFunctionSetting_t devicePinSetting[3][8];
42
43 /*! Determine if each Register needs to be forced set or not */
44 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
45 [
46 { register : "P1OUT" , regForceSet : true },
47 { register : "P1SEL0" , regForceSet : false },
48 { register : "P1SEL1" , regForceSet : false },
49 { register : "P1DIR" , regForceSet : false },
50 { register : "P1REN" , regForceSet : false },
51 { register : "P1IES" , regForceSet : true },
52 { register : "P1IFG" , regForceSet : true },
53 { register : "P1IE" , regForceSet : false },
54 { register : "P2OUT" , regForceSet : true },
55 { register : "P2SEL0" , regForceSet : false },
56 { register : "P2SEL1" , regForceSet : false },
57 { register : "P2DIR" , regForceSet : false },
58 { register : "P2REN" , regForceSet : false },
59 { register : "P2IES" , regForceSet : true },
60 { register : "P2IFG" , regForceSet : true },
61 { register : "P2IE" , regForceSet : false },
62 { register : "PJOUT" , regForceSet : true },
63 { register : "PJSEL0" , regForceSet : false },
64 { register : "PJSEL1" , regForceSet : false },
65 { register : "PJDIR" , regForceSet : false },
66 { register : "PJREN" , regForceSet : false }
67 ];
68
69 70 71 72 73 74
75
76 /*! Port 1 Output Register */
77 config GpioBits8PxOut_t P1OUT = {
78 Bit0 : BIT0_OFF,
79 Bit1 : BIT1_OFF,
80 Bit2 : BIT2_OFF,
81 Bit3 : BIT3_OFF,
82 Bit4 : BIT4_OFF,
83 Bit5 : BIT5_OFF,
84 Bit6 : BIT6_OFF,
85 Bit7 : BIT7_OFF
86 };
87
88 /*! Port 1 Port Select Register 0 */
89 config GpioBits8PxSel_t P1SEL0 = {
90 Bit0 : BIT0_OFF,
91 Bit1 : BIT1_OFF,
92 Bit2 : BIT2_OFF,
93 Bit3 : BIT3_OFF,
94 Bit4 : BIT4_OFF,
95 Bit5 : BIT5_OFF,
96 Bit6 : BIT6_OFF,
97 Bit7 : BIT7_OFF
98 };
99
100 /*! Port 1 Port Select Register 1 */
101 config GpioBits8PxSel_t P1SEL1 = {
102 Bit0 : BIT0_OFF,
103 Bit1 : BIT1_OFF,
104 Bit2 : BIT2_OFF,
105 Bit3 : BIT3_OFF,
106 Bit4 : BIT4_OFF,
107 Bit5 : BIT5_OFF,
108 Bit6 : BIT6_OFF,
109 Bit7 : BIT7_OFF
110 };
111
112 /*! Port 1 Direction Register */
113 config GpioBits8PxDir_t P1DIR = {
114 Bit0 : BIT0_OFF,
115 Bit1 : BIT1_OFF,
116 Bit2 : BIT2_OFF,
117 Bit3 : BIT3_OFF,
118 Bit4 : BIT4_OFF,
119 Bit5 : BIT5_OFF,
120 Bit6 : BIT6_OFF,
121 Bit7 : BIT7_OFF
122 };
123
124 /*! Port 1 Resistor Enable Register */
125 config GpioBits8PxRen_t P1REN = {
126 Bit0 : BIT0_OFF,
127 Bit1 : BIT1_OFF,
128 Bit2 : BIT2_OFF,
129 Bit3 : BIT3_OFF,
130 Bit4 : BIT4_OFF,
131 Bit5 : BIT5_OFF,
132 Bit6 : BIT6_OFF,
133 Bit7 : BIT7_OFF
134 };
135
136 /*! Port 2 Output Register */
137 config GpioBits8PxOut_t P2OUT = {
138 Bit0 : BIT0_OFF,
139 Bit1 : BIT1_OFF,
140 Bit2 : BIT2_OFF,
141 Bit3 : BIT3_OFF,
142 Bit4 : BIT4_OFF,
143 Bit5 : BIT5_OFF,
144 Bit6 : BIT6_OFF,
145 Bit7 : BIT7_OFF
146 };
147
148 /*! Port 2 Port Select Register 0 */
149 config GpioBits8PxSel_t P2SEL0 = {
150 Bit0 : BIT0_OFF,
151 Bit1 : BIT1_OFF,
152 Bit2 : BIT2_OFF,
153 Bit3 : BIT3_OFF,
154 Bit4 : BIT4_OFF,
155 Bit5 : BIT5_OFF,
156 Bit6 : BIT6_OFF,
157 Bit7 : BIT7_OFF
158 };
159
160 /*! Port 2 Port Select Register 1 */
161 config GpioBits8PxSel_t P2SEL1 = {
162 Bit0 : BIT0_OFF,
163 Bit1 : BIT1_OFF,
164 Bit2 : BIT2_OFF,
165 Bit3 : BIT3_OFF,
166 Bit4 : BIT4_OFF,
167 Bit5 : BIT5_OFF,
168 Bit6 : BIT6_OFF,
169 Bit7 : BIT7_OFF
170 };
171
172 /*! Port 2 Direction Register */
173 config GpioBits8PxDir_t P2DIR = {
174 Bit0 : BIT0_OFF,
175 Bit1 : BIT1_OFF,
176 Bit2 : BIT2_OFF,
177 Bit3 : BIT3_OFF,
178 Bit4 : BIT4_OFF,
179 Bit5 : BIT5_OFF,
180 Bit6 : BIT6_OFF,
181 Bit7 : BIT7_OFF
182 };
183
184 /*! Port 2 Resistor Enable Register */
185 config GpioBits8PxRen_t P2REN = {
186 Bit0 : BIT0_OFF,
187 Bit1 : BIT1_OFF,
188 Bit2 : BIT2_OFF,
189 Bit3 : BIT3_OFF,
190 Bit4 : BIT4_OFF,
191 Bit5 : BIT5_OFF,
192 Bit6 : BIT6_OFF,
193 Bit7 : BIT7_OFF
194 };
195
196 /*! Port J Output Register */
197 config GpioBits8PxOut_t PJOUT = {
198 Bit0 : BIT0_OFF,
199 Bit1 : BIT1_OFF,
200 Bit2 : BIT2_OFF,
201 Bit3 : BIT3_OFF,
202 Bit4 : BIT4_OFF,
203 Bit5 : BIT5_OFF,
204 Bit6 : BIT6_OFF,
205 Bit7 : BIT7_OFF
206 };
207
208 /*! Port J Port Select Register 0 */
209 config GpioBits8PxSel_t PJSEL0 = {
210 Bit0 : BIT0_OFF,
211 Bit1 : BIT1_OFF,
212 Bit2 : BIT2_OFF,
213 Bit3 : BIT3_OFF,
214 Bit4 : BIT4_OFF,
215 Bit5 : BIT5_OFF,
216 Bit6 : BIT6_OFF,
217 Bit7 : BIT7_OFF
218 };
219
220 /*! Port J Port Select Register 1 */
221 config GpioBits8PxSel_t PJSEL1 = {
222 Bit0 : BIT0_OFF,
223 Bit1 : BIT1_OFF,
224 Bit2 : BIT2_OFF,
225 Bit3 : BIT3_OFF,
226 Bit4 : BIT4_OFF,
227 Bit5 : BIT5_OFF,
228 Bit6 : BIT6_OFF,
229 Bit7 : BIT7_OFF
230 };
231
232 /*! Port J Direction Register */
233 config GpioBits8PxDir_t PJDIR = {
234 Bit0 : BIT0_OFF,
235 Bit1 : BIT1_OFF,
236 Bit2 : BIT2_OFF,
237 Bit3 : BIT3_OFF,
238 Bit4 : BIT4_OFF,
239 Bit5 : BIT5_OFF,
240 Bit6 : BIT6_OFF,
241 Bit7 : BIT7_OFF
242 };
243
244 /*! Port J Resistor Enable Register */
245 config GpioBits8PxRen_t PJREN = {
246 Bit0 : BIT0_OFF,
247 Bit1 : BIT1_OFF,
248 Bit2 : BIT2_OFF,
249 Bit3 : BIT3_OFF,
250 Bit4 : BIT4_OFF,
251 Bit5 : BIT5_OFF,
252 Bit6 : BIT6_OFF,
253 Bit7 : BIT7_OFF
254 };
255 }