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12
13 /*!
14 * ======== BSCplus ========
15 * MSP430 Basic Clock System
16 */
17 metaonly module BCSplus inherits IClock
18 {
19 /*! MOD0 Bit */
20 enum MOD0_t {
21 MOD0_OFF = 0x00, /*! Disable MOD0 bit */
22 MOD0 = 0x01 /*! Enable MOD0 bit */
23 };
24
25 /*! MOD1 Bit */
26 enum MOD1_t {
27 MOD1_OFF = 0x00, /*! Disable MOD1 bit */
28 MOD1 = 0x02 /*! Enable MOD1 bit */
29 };
30
31 /*! MOD2 Bit */
32 enum MOD2_t {
33 MOD2_OFF = 0x00, /*! Disable MOD2 bit */
34 MOD2 = 0x04 /*! Enable MOD2 bit */
35 };
36
37 /*! MOD3 Bit */
38 enum MOD3_t {
39 MOD3_OFF = 0x00, /*! Disable MOD3 bit */
40 MOD3 = 0x08 /*! Enable MOD3 bit */
41 };
42
43 /*! MOD4 Bit */
44 enum MOD4_t {
45 MOD4_OFF = 0x00, /*! Disable MOD4 bit */
46 MOD4 = 0x10 /*! Enable MOD4 bit */
47 };
48
49 /*! DCO0 Bit */
50 enum DCO0_t {
51 DCO0_OFF = 0x00, /*! Disable DCO0 bit */
52 DCO0 = 0x20 /*! Enable DCO0 bit */
53 };
54
55 /*! DCO1 Bit */
56 enum DCO1_t {
57 DCO1_OFF = 0x00, /*! Disable DCO1 bit */
58 DCO1 = 0x40 /*! Enable DCO1 bit */
59 };
60
61 /*! DCO2 Bit */
62 enum DCO2_t {
63 DCO2_OFF = 0x00, /*! Disable DCO2 bit */
64 DCO2 = 0x80 /*! Enable DCO2 bit */
65 };
66
67 enum XT2OFF_t {
68 XT2OFF_OFF = 0x00, /*! Enable XT2CLK */
69 XT2OFF = 0x80 /*! Disable XT2CLK */
70 };
71
72 enum XTS_t {
73 XTS_OFF = 0x00, /*! Low Frequency */
74 XTS = 0x40 /*! High Frequency */
75 };
76
77 enum RSEL0_t {
78 RSEL0_OFF = 0x00, /*! Disable RSEL0 bit */
79 RSEL0 = 0x01 /*! Enable RSEL0 bit */
80 };
81
82 enum RSEL1_t {
83 RSEL1_OFF = 0x00, /*! Disable RSEL1 bit */
84 RSEL1 = 0x02 /*! Enable RSEL1 bit */
85 };
86
87 enum RSEL2_t {
88 RSEL2_OFF = 0x00, /*! Disable RSEL2 bit */
89 RSEL2 = 0x04 /*! Enable RSEL2 bit */
90 };
91
92 enum RSEL3_t {
93 RSEL3_OFF = 0x00, /*! Disable RSEL3 bit */
94 RSEL3 = 0x08 /*! Enable RSEL3 bit */
95 };
96
97 /*! MCLK Source Select */
98 enum SELM_t {
99 SELM_0 = 0x00, /*! DCOCLK */
100
101 SELM_2 = 0x80, /*! XT2CLK/LFXTCLK */
102 SELM_3 = 0xC0 /*! LFXTCLK */
103 };
104
105 /*! ACLK Divider values */
106 enum DIVA_t {
107 DIVA_0 = 0x00, /*! Divide by 1 */
108 DIVA_1 = 0x10, /*! Divide by 2 */
109 DIVA_2 = 0x20, /*! Divide by 4 */
110 DIVA_3 = 0x30 /*! Divide by 8 */
111 };
112
113 /*! MCLK Divider values */
114 enum DIVM_t {
115 DIVM_0 = 0x00, /*! Divide by 1 */
116 DIVM_1 = 0x10, /*! Divide by 2 */
117 DIVM_2 = 0x20, /*! Divide by 4 */
118 DIVM_3 = 0x30 /*! Divide by 8 */
119 };
120
121 /*! SMCLK Divider values */
122 enum DIVS_t {
123 DIVS_0 = 0x00, /*! Divide by 1 */
124 DIVS_1 = 0x02, /*! Divide by 2 */
125 DIVS_2 = 0x04, /*! Divide by 4 */
126 DIVS_3 = 0x06 /*! Divide by 8 */
127 };
128
129 enum SELS_t {
130 SELS_OFF = 0x00, /*! DCOCLK */
131 SELS = 0x08 /*! XT2CLK when XT2 oscillator present. LFXT1CLK or VLOCLK when XT2 oscillator not present */
132 };
133
134 enum DCOR_t {
135 DCOR_OFF = 0x00, /*! DCO uses internal resistor */
136 DCOR = 0x01 /*! DCO uses external resistor */
137 };
138
139 /*! XT2 frequency range select */
140 enum XT2S_t {
141 XT2S_0 = 0x00, /*! 0.4 - 1 MHz */
142 XT2S_1 = 0x40, /*! 1 - 3 MHz */
143 XT2S_2 = 0x80, /*! 3 - 16 MHz */
144 XT2S_3 = 0xC0 /*! Digital input signal */
145 };
146
147 enum LFXT1S_t {
148 LFXT1S_0 = 0x00, /*! If XTS = 0, XT1 = 32768kHz Crystal ; If XTS = 1, XT1 = 0.4 - 1-MHz crystal or resonator */
149 LFXT1S_1 = 0x10, /*! If XTS = 0, XT1 = Reserved ; If XTS = 1, XT1 = 1 - 3-MHz crystal or resonator */
150 LFXT1S_2 = 0x20, /*! If XTS = 0, XT1 = VLOCLK ; If XTS = 1, XT1 = 3 - 16-MHz crystal or resonator */
151 LFXT1S_3 = 0x30 /*! If XTS = 0, XT1 = Digital External ; If XTS = 1, XT1 = 0.4 - 16-MHz Digital External */
152 };
153
154 enum XCAP_t {
155 XCAP_0 = 0x00, /*! ~1 pF */
156 XCAP_1 = 0x04, /*! ~6 pF */
157 XCAP_2 = 0x08, /*! ~10 pF */
158 XCAP_3 = 0x0C /*! ~12.5 pF */
159 };
160
161 enum XT2OF_t {
162 XT2OF_OFF = 0x00, /*! No fault condition present */
163 XT2OF = 0x02 /*! XT2 fault condition present */
164 };
165
166 enum LFXT1OF_t {
167 LFXT1OF_OFF = 0x00, /*! No fault condition present */
168 LFXT1OF = 0x01 /*! LFXT1 fault condition present */
169 };
170
171 struct DCOCTL_t {
172 MOD0_t MOD0; /*! Modulation Bit 0 */
173 MOD1_t MOD1; /*! Modulation Bit 1 */
174 MOD2_t MOD2; /*! Modulation Bit 2 */
175 MOD3_t MOD3; /*! Modulation Bit 3 */
176 MOD4_t MOD4; /*! Modulation Bit 4 */
177 DCO0_t DCO0; /*! DCO Select Bit 0 */
178 DCO1_t DCO1; /*! DCO Select Bit 1 */
179 DCO2_t DCO2; /*! DCO Select Bit 2 */
180 }
181
182 /*!
183 * ======== BCSCTL1_t ========
184 * BCS Control Register 1
185 *
186 * @field(XT2OFF) This bit turns off the XT2 oscillator: 0 - XT2 is on,
187 * 1 - XT2 is off if it is not used for MCLK or SMCLK
188 *
189 * @field(XTS) 0 - Low frequency mode; 1 - High frequency mode
190 */
191 struct BCSCTL1_t {
192 XT2OFF_t XT2OFF; /*! XT2 off. This bit turns off the XT2 oscillator
193 * 0 XT2 is on
194 * 1 XT2 is off if it is not used for MCLK or SMCLK. */
195 XTS_t XTS; /*! LFXT1 mode select.
196 * 0 Low frequency mode
197 * 1 High frequency mode */
198 DIVA_t DIVA; /*! Divider for ACLK
199 * 00 /1
200 * 01 /2
201 * 10 /4
202 * 11 /8 */
203 RSEL0_t RSEL0; /*! Range select bit 0 */
204 RSEL1_t RSEL1; /*! Range select bit 1 */
205 RSEL2_t RSEL2; /*! Range select bit 2 */
206 RSEL3_t RSEL3; /*! Range select bit 3 */
207 }
208
209 /*!
210 * ======== BCSCTL2_t ========
211 * BCS Control Register 2
212 *
213 * @field(SELM) These bits select the MCLK source.
214 * @field(SELS) These bits select the SMCLK source. When
215 * XT2 oscillator present, 0 selects DCOCLK and
216 * 1 selects XT2CLK; otherwise 0 selects LFXT1CLK and
217 * 1 selects VLOCLK.
218 * @field(DCOR) 0 - Internal resistor, 1 - external resistor
219 */
220 struct BCSCTL2_t {
221 SELM_t SELM; /*! Select MCLK. These bits select the MCLK source.
222 * 00 DCOCLK
223 * 01 DCOCLK
224 * 10 XT2CLK when XT2 oscillator present on-chip. LFXT1CLK or VLOCLK
225 * when XT2 oscillator not present on-chip.
226 * 11 LFXT1CLK or VLOCLK */
227 DIVM_t DIVM; /*! Divider for MCLK
228 * 00 /1
229 * 01 /2
230 * 10 /4
231 * 11 /8 */
232 SELS_t SELS; /*! Select SMCLK. This bit selects the SMCLK source.
233 * 0 DCOCLK
234 * 1 XT2CLK when XT2 oscillator present. LFXT1CLK or VLOCLK when
235 * XT2 oscillator not present */
236 DIVS_t DIVS; /*! Divider for SMCLK
237 * 00 /1
238 * 01 /2
239 * 10 /4
240 * 11 /8 */
241 DCOR_t DCOR; /*! DCO resistor select
242 * 0 Internal resistor
243 * 1 External resistor */
244 }
245
246 /*!
247 * ======== BCSCTL3_t ========
248 * BCS Control register 3
249 *
250 * @field(LFXT1S) These bits select between LFXT1 and VLO and XTS = 0,
251 * and select the frequency range for LFXT1 when XTS = 1
252 * @field(XCAP) These bits select the effective capacitance seen by
253 * the LFXT1 crystal when XTS = 0. If XTS = 1 or if
254 * LFCT1Sx = 11, then XCAPx should be 00.
255 */
256 struct BCSCTL3_t {
257 XT2S_t XT2S; /*! XT2 range select. These bits select the frequency range for XT2.
258 * 00 0.4 - 1-MHz crystal or resonator
259 * 01 1 - 3-MHz crystal or resonator
260 * 10 3 - 16-MHz crystal or resonator
261 * 11 Digital external 0.4 - 16-MHz clock source */
262 LFXT1S_t LFXT1S; /*! Low-frequency clock select and LFXT1 range select. These bits select
263 * between LFXT1 and VLO when XTS = 0, and select the frequency range
264 * for LFXT1 when XTS = 1
265 *
266 * When XTS = 0:
267 * 00 32768 Hz Crystal on LFXT1
268 * 01 Reserved
269 * 10 VLOCLK (Reserved in MSP430x21x1 devices)
270 * 11 Digital external clock source
271 *
272 * When XTS = 1 (Not applicable for MSP430x20xx devices)
273 * 00 0.4 - 1-MHz crystal or resonator
274 * 01 1 - 3-MHz crystal or resonator
275 * 10 3 - 16-MHz crystal or resonator
276 * 11 Digital external 0.4 - 16-MHz clock source */
277 XCAP_t XCAP; /*! Oscillator capacitor selection. These bits select the effective capacitance
278 * seen by the LFXT1 crystal when XTS = 0. If XTS = 1 or if LFCT1Sx = 11
279 * XCAPx should be 00.
280 * 00 ~1 pF
281 * 01 ~6 pF
282 * 10 ~10 pF
283 * 11 ~12.5 pF */
284 XT2OF_t XT2OF; /*! XT2 oscillator fault
285 * 0 No fault condition present
286 * 1 Fault condition present */
287 LFXT1OF_t LFXT1OF; /*! LFXT1 oscillator fault
288 * 0 No fault condition present
289 * 1 Fault condition present */
290 }
291
292 instance:
293
294 /*! DCO Clock Frequency Control */
295 config DCOCTL_t DCOCTL = {
296 MOD0 : MOD0_OFF,
297 MOD1 : MOD1_OFF,
298 MOD2 : MOD2_OFF,
299 MOD3 : MOD3_OFF,
300 MOD4 : MOD4_OFF,
301 DCO0 : DCO0,
302 DCO1 : DCO1,
303 DCO2 : DCO2_OFF,
304 };
305
306 /*! Basic Clock System Control 1 */
307 config BCSCTL1_t BCSCTL1 = {
308 XT2OFF : XT2OFF,
309 XTS : XTS_OFF,
310 DIVA : DIVA_0,
311 RSEL0 : RSEL0,
312 RSEL1 : RSEL1,
313 RSEL2 : RSEL2,
314 RSEL3 : RSEL3_OFF
315 };
316
317 /*! Basic Clock System Control 2 */
318 config BCSCTL2_t BCSCTL2 = {
319 SELM : SELM_0,
320 DIVM : DIVM_0,
321 SELS : SELS_OFF,
322 DIVS : DIVS_0,
323 DCOR : DCOR_OFF
324 };
325
326 /*! Basic Clock System Control 3 */
327 config BCSCTL3_t BCSCTL3 = {
328 XT2S : XT2S_0,
329 LFXT1S : LFXT1S_0,
330 XCAP : XCAP_1
331 };
332
333 /*! Determine if each Register needs to be forced set or not */
334 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
335 [
336 { register : "DCOCTL" , regForceSet : false },
337 { register : "BCSCTL1" , regForceSet : false },
338 { register : "BCSCTL2" , regForceSet : false },
339 { register : "BCSCTL3" , regForceSet : false }
340 ];
341
342 /*! Basic Clock System + pre-calibrated system frequency */
343 config UInt preCalibratedValues = 0;
344
345 /*!
346 * ======== preCalibratedValues truth table ========
347 *
348 * hasAllCal = false
349 * UInt - Description
350 * 0 - 1 MHz
351 * 1 - Custom
352 *
353 * hasAllCal = true
354 * UInt - Description
355 * 0 - 1 MHz
356 * 1 - 8 MHz
357 * 2 - 12 MHz
358 * 3 - 16 MHz
359 * 4 - Custom
360 */
361 config String preCalibratedValuesItems[length];
362
363 config float VLOCLKHz = 12000;
364 config float WATCHCRYSTALCLKHz = 32768;
365 config float LFXT1CLKHz = 0;
366 config float XT2CLKHz = 0;
367
368 /*!
369 * ======== enableXT2 ========
370 * Set whether XT2 is used on the device. This is different than hasXT2
371 * variable.
372 */
373 config Bool enableXT2 = false;
374 }