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12 /*!
13 * ======== ADC12 ========
14 * MSP430 12-bit Analog to Digital Converter
15 */
16 metaonly module ADC12 inherits IADC {
17
18 /*! SHT1 Bits */
19 enum ADC12SHT1_t {
20 SHT1_0 = (0*0x1000u), /*! 4 ADC12CLK cycles */
21 SHT1_1 = (1*0x1000u), /*! 8 ADC12CLK cycles */
22 SHT1_2 = (2*0x1000u), /*! 16 ADC12CLK cycles */
23 SHT1_3 = (3*0x1000u), /*! 32 ADC12CLK cycles */
24 SHT1_4 = (4*0x1000u), /*! 64 ADC12CLK cycles */
25 SHT1_5 = (5*0x1000u), /*! 96 ADC12CLK cycles */
26 SHT1_6 = (6*0x1000u), /*! 128 ADC12CLK cycles */
27 SHT1_7 = (7*0x1000u), /*! 192 ADC12CLK cycles */
28 SHT1_8 = (8*0x1000u), /*! 256 ADC12CLK cycles */
29 SHT1_9 = (9*0x1000u), /*! 384 ADC12CLK cycles */
30 SHT1_10 = (10*0x1000u), /*! 512 ADC12CLK cycles */
31 SHT1_11 = (11*0x1000u), /*! 768 ADC12CLK cycles */
32 SHT1_12 = (12*0x1000u), /*! 1024 ADC12CLK cycles */
33 SHT1_13 = (13*0x1000u), /*! 1024 ADC12CLK cycles */
34 SHT1_14 = (14*0x1000u), /*! 1024 ADC12CLK cycles */
35 SHT1_15 = 15*0x1000u /*! 1024 ADC12CLK cycles */
36 };
37
38 /*! SHT0 Bits */
39 enum ADC12SHT0_t {
40 SHT0_0 = (0*0x1000u), /*! 4 ADC12CLK cycles */
41 SHT0_1 = (1*0x1000u), /*! 8 ADC12CLK cycles */
42 SHT0_2 = (2*0x1000u), /*! 16 ADC12CLK cycles */
43 SHT0_3 = (3*0x1000u), /*! 32 ADC12CLK cycles */
44 SHT0_4 = (4*0x1000u), /*! 64 ADC12CLK cycles */
45 SHT0_5 = (5*0x1000u), /*! 96 ADC12CLK cycles */
46 SHT0_6 = (6*0x1000u), /*! 128 ADC12CLK cycles */
47 SHT0_7 = (7*0x1000u), /*! 192 ADC12CLK cycles */
48 SHT0_8 = (8*0x1000u), /*! 256 ADC12CLK cycles */
49 SHT0_9 = (9*0x1000u), /*! 384 ADC12CLK cycles */
50 SHT0_10 = (10*0x1000u), /*! 512 ADC12CLK cycles */
51 SHT0_11 = (11*0x1000u), /*! 768 ADC12CLK cycles */
52 SHT0_12 = (12*0x1000u), /*! 1024 ADC12CLK cycles */
53 SHT0_13 = (13*0x1000u), /*! 1024 ADC12CLK cycles */
54 SHT0_14 = (14*0x1000u), /*! 1024 ADC12CLK cycles */
55 SHT0_15 = 15*0x1000u /*! 1024 ADC12CLK cycles */
56 };
57
58 /*! MSC Bit */
59 enum MSC_t {
60 MSC_OFF = 0x000, /*! The sampling timer requires a rising edge of the SHI
61 * signal to trigger each sample-and-conversion */
62 MSC = 0x080 /*! The first rising edge of the SHI signal triggers
63 * the sampling timer, but further sample-and-conversions
64 * are performed automatically as soon as the prior conversion
65 * is completed */
66 };
67
68 /*! REF2_5V Bit */
69 enum REF2_5V_t {
70 REF2_5V_OFF = 0x000, /*! 1.5V */
71 REF2_5V = 0x040 /*! 2.5V */
72 };
73
74 /*! REFON Bit */
75 enum REFON_t {
76 REFON_OFF = 0x000, /*! Reference off */
77 REFON = 0x020 /*! Reference on */
78 };
79
80 /*! ADC12ON Bit */
81 enum ADC12ON_t {
82 ADC12ON_OFF = 0x000, /*! ADC12 off */
83 ADC12ON = 0x010 /*! ADC12 on */
84 };
85
86 /*! ADC12OVIE Bit */
87 enum ADC12OVIE_t {
88 ADC12OVIE_OFF = 0x000, /*! Overflow interrupt disabled */
89 ADC12OVIE = 0x008 /*! Overflow interrupt enabled */
90 };
91
92 /*! ADC12TOVIE Bit */
93 enum ADC12TOVIE_t {
94 ADC12TOVIE_OFF = 0x000, /*! Conversion time overflow interrupt disabled */
95 ADC12TOVIE = 0x004 /*! Conversion time overflow interrupt disabled */
96 };
97
98 /*! ENC Bit */
99 enum ENC_t {
100 ENC_OFF = 0x000, /*! ADC12 disabled */
101 ENC = 0x002 /*! ADC12 enabled */
102 };
103
104 /*! ADC12SC Bit */
105 enum ADC12SC_t {
106 ADC12SC_OFF = 0x000, /*! No sample-and-conversion-start */
107 ADC12SC = 0x001 /*! Start sample-and-conversion */
108 };
109
110 /*! CSTARTADD Bits */
111 enum CSTARTADD_t {
112 CSTARTADD_0 = (0*0x1000u), /*! ADC12MEM0 */
113 CSTARTADD_1 = (1*0x1000u), /*! ADC12MEM1 */
114 CSTARTADD_2 = (2*0x1000u), /*! ADC12MEM2 */
115 CSTARTADD_3 = (3*0x1000u), /*! ADC12MEM3 */
116 CSTARTADD_4 = (4*0x1000u), /*! ADC12MEM4 */
117 CSTARTADD_5 = (5*0x1000u), /*! ADC12MEM5 */
118 CSTARTADD_6 = (6*0x1000u), /*! ADC12MEM6 */
119 CSTARTADD_7 = (7*0x1000u), /*! ADC12MEM7 */
120 CSTARTADD_8 = (8*0x1000u), /*! ADC12MEM8 */
121 CSTARTADD_9 = (9*0x1000u), /*! ADC12MEM9 */
122 CSTARTADD_10 = (10*0x1000u), /*! ADC12MEM10 */
123 CSTARTADD_11 = (11*0x1000u), /*! ADC12MEM11 */
124 CSTARTADD_12 = (12*0x1000u), /*! ADC12MEM12 */
125 CSTARTADD_13 = (13*0x1000u), /*! ADC12MEM13 */
126 CSTARTADD_14 = (14*0x1000u), /*! ADC12MEM14 */
127 CSTARTADD_15 = 15*0x1000u /*! ADC12MEM15 */
128 };
129
130 /*! SHS Bits */
131 enum SHS_t {
132 SHS_0 = (0*0x400u), /*! ADC12SC bit */
133 SHS_1 = (1*0x400u), /*! Timer_A.OUT1 */
134 SHS_2 = (2*0x400u), /*! Timer_B.OUT0 */
135 SHS_3 = 3*0x400u /*! Timer_B.OUT1 */
136 };
137
138 /*! SHP Bits */
139 enum SHP_t {
140 SHP_OFF = 0x0000, /*! SAMPCON signal is sourced from the sample-input signal */
141 SHP = 0x0200 /*! SAMPCON signal is sourced from the sampling timer. */
142 };
143
144 /*! ISSH Bits */
145 enum ISSH_t {
146 ISSH_OFF = 0x0000, /*! The sample-input signal is not inverted */
147 ISSH = 0x0100 /*! The sample-input signal is inverted */
148 };
149
150
151 /*! ADC12DIV Bits */
152 enum ADC12DIV_t {
153 ADC12DIV_0 = (0*0x20u), /*! Divide by 1 */
154 ADC12DIV_1 = (1*0x20u), /*! Divide by 2 */
155 ADC12DIV_2 = (2*0x20u), /*! Divide by 3 */
156 ADC12DIV_3 = (3*0x20u), /*! Divide by 4 */
157 ADC12DIV_4 = (4*0x20u), /*! Divide by 5 */
158 ADC12DIV_5 = (5*0x20u), /*! Divide by 6 */
159 ADC12DIV_6 = (6*0x20u), /*! Divide by 7 */
160 ADC12DIV_7 = 7*0x20u /*! Divide by 8 */
161 };
162
163 /*! ADC12SSEL Bits */
164 enum ADC12SSEL_t {
165 ADC12SSEL_0 = (0*8u), /*! ADC12OSC */
166 ADC12SSEL_1 = (1*8u), /*! ACLK */
167 ADC12SSEL_2 = (2*8u), /*! MCLK */
168 ADC12SSEL_3 = 3*8u /*! SMCLK */
169 };
170
171 /*! CONSEQ Bits */
172 enum CONSEQ_t {
173 CONSEQ_0 = (0*2u), /*! Single channel single conversion */
174 CONSEQ_1 = (1*2u), /*! Sequence of channels */
175 CONSEQ_2 = (2*2u), /*! Repeat single channel */
176 CONSEQ_3 = 3*2u /*! Repeat sequence of channels */
177 };
178
179 /*! ADC12 Busy Bit */
180 enum ADC12BUSY_t {
181 ADC12BUSY_OFF = 0x0000,
182 ADC12BUSY = 0x0001
183 };
184
185 /*! EOS Bit */
186 enum EOS_t {
187 EOS_OFF = 0x0000, /*! Not end of sequence */
188 EOS = 0x0080 /*! End of sequence */
189 };
190
191 /*! SREF Bits */
192 enum SREF_t {
193 SREF_0 = (0*0x10u), /*! VR+ = AVcc and VR-- = AVss */
194 SREF_1 = (1*0x10u), /*! VR+ = VREF+ and VR-- = AVss */
195 SREF_2 = (2*0x10u), /*! VR+ = VeREF+ and VR-- = AVss */
196 SREF_3 = (3*0x10u), /*! VR+ = VeREF+ and VR-- = AVss */
197 SREF_4 = (4*0x10u), /*! VR+ = AVcc and VR-- = VREF--/ VeREF-- */
198 SREF_5 = (5*0x10u), /*! VR+ = VREF+ and VR-- = VREF--/ VeREF-- */
199 SREF_6 = (6*0x10u), /*! VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
200 SREF_7 = 7*0x10u /*! VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
201 };
202
203 /*! ADC12 Interrupt Enable Bit 15 */
204 enum ADC12IE15_t {
205 ADC12IE15_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG15 bit */
206 ADC12IE15 = 0x8000 /*! Enable the interrupt request for the ADC12IFG15 bit */
207 };
208
209 /*! ADC12 Interrupt Enable Bit 14 */
210 enum ADC12IE14_t {
211 ADC12IE14_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG14 bit */
212 ADC12IE14 = 0x4000 /*! Enable the interrupt request for the ADC12IFG14 bit */
213 };
214
215 /*! ADC12 Interrupt Enable Bit 13 */
216 enum ADC12IE13_t {
217 ADC12IE13_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG13 bit */
218 ADC12IE13 = 0x2000 /*! Enable the interrupt request for the ADC12IFG13 bit */
219 };
220
221 /*! ADC12 Interrupt Enable Bit 12 */
222 enum ADC12IE12_t {
223 ADC12IE12_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG12 bit */
224 ADC12IE12 = 0x1000 /*! Enable the interrupt request for the ADC12IFG12 bit */
225 };
226
227 /*! ADC12 Interrupt Enable Bit 11 */
228 enum ADC12IE11_t {
229 ADC12IE11_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG11 bit */
230 ADC12IE11 = 0x0800 /*! Enable the interrupt request for the ADC12IFG11 bit */
231 };
232
233 /*! ADC12 Interrupt Enable Bit 10 */
234 enum ADC12IE10_t {
235 ADC12IE10_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG10 bit */
236 ADC12IE10 = 0x0400 /*! Enable the interrupt request for the ADC12IFG10 bit */
237 };
238
239 /*! ADC12 Interrupt Enable Bit 9 */
240 enum ADC12IE9_t {
241 ADC12IE9_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG9 bit */
242 ADC12IE9 = 0x0200 /*! Enable the interrupt request for the ADC12IFG9 bit */
243 };
244
245 /*! ADC12 Interrupt Enable Bit 8 */
246 enum ADC12IE8_t {
247 ADC12IE8_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG8 bit */
248 ADC12IE8 = 0x0100 /*! Enable the interrupt request for the ADC12IFG8 bit */
249 };
250
251 /*! ADC12 Interrupt Enable Bit 7 */
252 enum ADC12IE7_t {
253 ADC12IE7_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG7 bit */
254 ADC12IE7 = 0x0080 /*! Enable the interrupt request for the ADC12IFG7 bit */
255 };
256
257 /*! ADC12 Interrupt Enable Bit 6 */
258 enum ADC12IE6_t {
259 ADC12IE6_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG6 bit */
260 ADC12IE6 = 0x0040 /*! Enable the interrupt request for the ADC12IFG6 bit */
261 };
262
263 /*! ADC12 Interrupt Enable Bit 5 */
264 enum ADC12IE5_t {
265 ADC12IE5_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG5 bit */
266 ADC12IE5 = 0x0020 /*! Enable the interrupt request for the ADC12IFG5 bit */
267 };
268
269 /*! ADC12 Interrupt Enable Bit 4 */
270 enum ADC12IE4_t {
271 ADC12IE4_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG4 bit */
272 ADC12IE4 = 0x0010 /*! Enable the interrupt request for the ADC12IFG4 bit */
273 };
274
275 /*! ADC12 Interrupt Enable Bit 3 */
276 enum ADC12IE3_t {
277 ADC12IE3_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG3 bit */
278 ADC12IE3 = 0x0008 /*! Enable the interrupt request for the ADC12IFG3 bit */
279 };
280
281 /*! ADC12 Interrupt Enable Bit 2 */
282 enum ADC12IE2_t {
283 ADC12IE2_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG2 bit */
284 ADC12IE2 = 0x0004 /*! Enable the interrupt request for the ADC12IFG2 bit */
285 };
286
287 /*! ADC12 Interrupt Enable Bit 1 */
288 enum ADC12IE1_t {
289 ADC12IE1_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG1 bit */
290 ADC12IE1 = 0x0002 /*! Enable the interrupt request for the ADC12IFG1 bit */
291 };
292
293 /*! ADC12 Interrupt Enable Bit 0 */
294 enum ADC12IE0_t {
295 ADC12IE0_OFF = 0x0000, /*! Disable the interrupt request for the ADC12IFG0 bit */
296 ADC12IE0 = 0x0001 /*! Enable the interrupt request for the ADC12IFG0 bit */
297 };
298
299 /*! INCH Bits */
300 enum INCH_t {
301 INCH_0 = (0), /*! A0 */
302 INCH_1 = (1), /*! A1 */
303 INCH_2 = (2), /*! A2 */
304 INCH_3 = (3), /*! A3 */
305 INCH_4 = (4), /*! A4 */
306 INCH_5 = (5), /*! A5 */
307 INCH_6 = (6), /*! A6 */
308 INCH_7 = (7), /*! A7 */
309 INCH_8 = (8), /*! VeREF+ */
310 INCH_9 = (9), /*! VREF--/VeREF- */
311 INCH_10 = (10), /*! Temperature diode */
312 INCH_11 = (11), /*! (AVcc - AVss) / 2 */
313 INCH_12 = (12), /*! GND */
314 INCH_13 = (13), /*! GND */
315 INCH_14 = (14), /*! GND */
316 INCH_15 = 15 /*! GND */
317 };
318
319
320 /*! ADC12IV Definitions */
321 enum ADC12IV_t {
322 ADC12IV_NONE = (0x0000), /*! No Interrupt pending */
323 ADC12IV_ADC12OVIFG = (0x0002), /*! ADC12OVIFG */
324 ADC12IV_ADC12TOVIFG = (0x0004), /*! ADC12TOVIFG */
325 ADC12IV_ADC12IFG0 = (0x0006), /*! ADC12IFG0 */
326 ADC12IV_ADC12IFG1 = (0x0008), /*! ADC12IFG1 */
327 ADC12IV_ADC12IFG2 = (0x000A), /*! ADC12IFG2 */
328 ADC12IV_ADC12IFG3 = (0x000C), /*! ADC12IFG3 */
329 ADC12IV_ADC12IFG4 = (0x000E), /*! ADC12IFG4 */
330 ADC12IV_ADC12IFG5 = (0x0010), /*! ADC12IFG5 */
331 ADC12IV_ADC12IFG6 = (0x0012), /*! ADC12IFG6 */
332 ADC12IV_ADC12IFG7 = (0x0014), /*! ADC12IFG7 */
333 ADC12IV_ADC12IFG8 = (0x0016), /*! ADC12IFG8 */
334 ADC12IV_ADC12IFG9 = (0x0018), /*! ADC12IFG9 */
335 ADC12IV_ADC12IFG10 = (0x001A), /*! ADC12IFG10 */
336 ADC12IV_ADC12IFG11 = (0x001C), /*! ADC12IFG11 */
337 ADC12IV_ADC12IFG12 = (0x001E), /*! ADC12IFG12 */
338 ADC12IV_ADC12IFG13 = (0x0020), /*! ADC12IFG13 */
339 ADC12IV_ADC12IFG14 = (0x0022), /*! ADC12IFG14 */
340 ADC12IV_ADC12IFG15 = 0x0024 /*! ADC12IFG15 */
341 };
342
343 /*! ADC12 Control Register 0 */
344 struct ADC12CTL0_t {
345 ADC12SHT1_t ADC12SHT1; /*! Sample-and-hold time. These bits define the number
346 * of ADC12CLK cycles in the sampling period for registers
347 * ADC12MEM8 to ADC12MEM15. */
348 ADC12SHT0_t ADC12SHT0; /*! Sample-and-hold time. These bits define the number
349 * of ADC12CLK cycles in the sampling period for registers
350 * ADC12MEM0 to ADC12MEM7. */
351 MSC_t MSC; /*! Multiple sample and conversion. Valid only for sequence
352 * or repeated modes.
353 * 0 The sampling timer requires a rising edge of the SHI signal
354 * to trigger each sample-and-conversion.
355 * 1 The first rising edge of the SHI signal triggers the sampling
356 * timer, but further sample-and-conversions are performed
357 * automatically as soon as the prior conversion is completed. */
358 REF2_5V_t REF2_5V; /*! Reference generator voltage. REFON must also be set.
359 * 0 1.5V
360 * 1 2.5V */
361 REFON_t REFON; /*! Reference generator on
362 * 0 Reference off
363 * 1 Reference on */
364 ADC12ON_t ADC12ON; /*! ADC12 on
365 * 0 ADC12 off
366 * 1 ADC12 on */
367 ADC12OVIE_t ADC12OVIE; /*! ADC12MEMx overflow-interrupt enable. The GIE bit must also be
368 * set to enable the interrupt.
369 * 0 Overflow interrupt disabled
370 * 1 Overflow interrupt enabled */
371 ADC12TOVIE_t ADC12TOVIE; /*! ADC12 conversion-time-overflow interrupt enable.
372 * The GIE bit must also be set to enable the interrupt.
373 * 0 Conversion time overflow interrupt disabled
374 * 1 Conversion time overflow interrupt enabled */
375 ENC_t ENC; /*! Enable conversion
376 * 0 ADC12 disabled
377 * 1 ADC12 enabled */
378 ADC12SC_t ADC12SC; /*! Start conversion. Software-controlled sample-and-conversion start.
379 * ADC12SC and ENC may be set together with one instruction. ADC12SC is
380 * reset automatically.
381 * 0 No sample-and-conversion-start
382 * 1 Start sample-and-conversion */
383 };
384
385 /*! ADC12 Control Register 1 */
386 struct ADC12CTL1_t {
387 CSTARTADD_t CSTARTADD; /*! Conversion start address. These bits select which ADC12
388 * conversion-memory register is used for a single conversion or for the first
389 * conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh,
390 * corresponding to ADC12MEM0 to ADC12MEM15. */
391 SHS_t SHS; /*! Sample-and-hold source select
392 * 00 ADC12SC bit
393 * 01 Timer_A.OUT1
394 * 10 Timer_B.OUT0
395 * 11 Timer_B.OUT1 */
396 SHP_t SHP; /*! Sample-and-hold pulse-mode select. This bit selects the source of the
397 * sampling signal (SAMPCON) to be either the output of the sampling timer or
398 * the sample-input signal directly.
399 * 0 SAMPCON signal is sourced from the sample-input signal.
400 * 1 SAMPCON signal is sourced from the sampling timer. */
401 ISSH_t ISSH; /*! Invert signal sample-and-hold
402 * 0 The sample-input signal is not inverted.
403 * 1 The sample-input signal is inverted. */
404 ADC12DIV_t ADC12DIV; /*! ADC12 clock divider
405 * 000 /1
406 * 001 /2
407 * 010 /3
408 * 011 /4
409 * 100 /5
410 * 101 /6
411 * 110 /7
412 * 111 /8 */
413 ADC12SSEL_t ADC12SSEL; /*! ADC12 clock source select
414 * 00 ADC12OSC
415 * 01 ACLK
416 * 10 MCLK
417 * 11 SMCLK */
418 CONSEQ_t CONSEQ; /*! Conversion sequence mode select
419 * 00 Single-channel, single-conversion
420 * 01 Sequence-of-channels
421 * 10 Repeat-single-channel
422 * 11 Repeat-sequence-of-channels */
423 ADC12BUSY_t ADC12BUSY; /*! ADC12 busy. This bit indicates an active sample or conversion operation.
424 * 0 No operation is active.
425 * 1 A sequence, sample, or conversion is active. */
426 };
427
428 /*! ADC12 Conversion Memory Control Registers */
429 struct ADC12MCTL_t {
430 EOS_t EOS; /*! End of sequence. Indicates the last conversion in a sequence.
431 * 0 Not end of sequence
432 * 1 End of sequence */
433 SREF_t SREF; /*! Select reference
434 * 000 VR+ = AVCC and VR-- = AVSS
435 * 001 VR+ = VREF+ and VR-- = AVSS
436 * 010 VR+ = VeREF+ and VR-- = AVSS
437 * 011 VR+ = VeREF+ and VR-- = AVSS
438 * 100 VR+ = AVCC and VR-- = VREF--/ VeREF--
439 * 101 VR+ = VREF+ and VR-- = VREF--/ VeREF--
440 * 110 VR+ = VeREF+ and VR-- = VREF--/ VeREF--
441 * 111 VR+ = VeREF+ and VR-- = VREF--/ VeREF-- */
442 INCH_t INCH; /*! Input channel select
443 * 0000 A0
444 * 0001 A1
445 * 0010 A2
446 * 0011 A3
447 * 0100 A4
448 * 0101 A5
449 * 0110 A6
450 * 0111 A7
451 * 1000 VeREF+
452 * 1001 VREF--/VeREF--
453 * 1010 Temperature diode
454 * 1011 (AVCC � AVSS) / 2
455 * 1100 GND
456 * 1101 GND
457 * 1110 GND
458 * 1111 GND */
459 };
460
461 /*! ADC12 Interrupt Enable Register */
462 struct ADC12IE_t {
463 ADC12IE15_t ADC12IE15; /*! Enable or disable the interrupt request for the ADC12IFG15 bit.
464 * 0 Interrupt disabled
465 * 1 Interrupt enabled */
466 ADC12IE14_t ADC12IE14; /*! Enable or disable the interrupt request for the ADC12IFG14 bit.
467 * 0 Interrupt disabled
468 * 1 Interrupt enabled */
469 ADC12IE13_t ADC12IE13; /*! Enable or disable the interrupt request for the ADC12IFG13 bit.
470 * 0 Interrupt disabled
471 * 1 Interrupt enabled */
472 ADC12IE12_t ADC12IE12; /*! Enable or disable the interrupt request for the ADC12IFG12 bit.
473 * 0 Interrupt disabled
474 * 1 Interrupt enabled */
475 ADC12IE11_t ADC12IE11; /*! Enable or disable the interrupt request for the ADC12IFG11 bit.
476 * 0 Interrupt disabled
477 * 1 Interrupt enabled */
478 ADC12IE10_t ADC12IE10; /*! Enable or disable the interrupt request for the ADC12IFG10 bit.
479 * 0 Interrupt disabled
480 * 1 Interrupt enabled */
481 ADC12IE9_t ADC12IE9; /*! Enable or disable the interrupt request for the ADC12IFG9 bit.
482 * 0 Interrupt disabled
483 * 1 Interrupt enabled */
484 ADC12IE8_t ADC12IE8; /*! Enable or disable the interrupt request for the ADC12IFG8 bit.
485 * 0 Interrupt disabled
486 * 1 Interrupt enabled */
487 ADC12IE7_t ADC12IE7; /*! Enable or disable the interrupt request for the ADC12IFG7 bit.
488 * 0 Interrupt disabled
489 * 1 Interrupt enabled */
490 ADC12IE6_t ADC12IE6; /*! Enable or disable the interrupt request for the ADC12IFG6 bit.
491 * 0 Interrupt disabled
492 * 1 Interrupt enabled */
493 ADC12IE5_t ADC12IE5; /*! Enable or disable the interrupt request for the ADC12IFG5 bit.
494 * 0 Interrupt disabled
495 * 1 Interrupt enabled */
496 ADC12IE4_t ADC12IE4; /*! Enable or disable the interrupt request for the ADC12IFG4 bit.
497 * 0 Interrupt disabled
498 * 1 Interrupt enabled */
499 ADC12IE3_t ADC12IE3; /*! Enable or disable the interrupt request for the ADC12IFG3 bit.
500 * 0 Interrupt disabled
501 * 1 Interrupt enabled */
502 ADC12IE2_t ADC12IE2; /*! Enable or disable the interrupt request for the ADC12IFG2 bit.
503 * 0 Interrupt disabled
504 * 1 Interrupt enabled */
505 ADC12IE1_t ADC12IE1; /*! Enable or disable the interrupt request for the ADC12IFG1 bit.
506 * 0 Interrupt disabled
507 * 1 Interrupt enabled */
508 ADC12IE0_t ADC12IE0; /*! Enable or disable the interrupt request for the ADC12IFG0 bit.
509 * 0 Interrupt disabled
510 * 1 Interrupt enabled */
511 };
512
513 instance:
514 /*! ADC12CTL0 Register */
515 config ADC12CTL0_t ADC12CTL0 = {
516 ADC12SHT1 : SHT1_0,
517 ADC12SHT0 : SHT0_0,
518 MSC : MSC_OFF,
519 REF2_5V : REF2_5V_OFF,
520 REFON : REFON_OFF,
521 ADC12ON : ADC12ON_OFF,
522 ADC12OVIE : ADC12OVIE_OFF,
523 ADC12TOVIE : ADC12TOVIE_OFF,
524 ENC : ENC_OFF,
525 ADC12SC : ADC12SC_OFF
526 };
527
528 /*! ADC12CTL1 Register */
529 config ADC12CTL1_t ADC12CTL1 = {
530 CSTARTADD : CSTARTADD_0,
531 SHS : SHS_0,
532 SHP : SHP_OFF,
533 ISSH : ISSH_OFF,
534 ADC12DIV : ADC12DIV_0,
535 ADC12SSEL : ADC12SSEL_0,
536 CONSEQ : CONSEQ_0,
537 ADC12BUSY : ADC12BUSY_OFF
538 };
539
540 /*! ADC12MCTL0 Register */
541 config ADC12MCTL_t ADC12MCTL0 = {
542 EOS : EOS_OFF,
543 SREF : SREF_0,
544 INCH : INCH_0
545 };
546
547 /*! ADC12MCTL1 Register */
548 config ADC12MCTL_t ADC12MCTL1 = {
549 EOS : EOS_OFF,
550 SREF : SREF_0,
551 INCH : INCH_0
552 };
553
554 /*! ADC12MCTL2 Register */
555 config ADC12MCTL_t ADC12MCTL2 = {
556 EOS : EOS_OFF,
557 SREF : SREF_0,
558 INCH : INCH_0
559 };
560
561 /*! ADC12MCTL3 Register */
562 config ADC12MCTL_t ADC12MCTL3 = {
563 EOS : EOS_OFF,
564 SREF : SREF_0,
565 INCH : INCH_0
566 };
567
568 /*! ADC12MCTL4 Register */
569 config ADC12MCTL_t ADC12MCTL4 = {
570 EOS : EOS_OFF,
571 SREF : SREF_0,
572 INCH : INCH_0
573 };
574
575 /*! ADC12MCTL5 Register */
576 config ADC12MCTL_t ADC12MCTL5 = {
577 EOS : EOS_OFF,
578 SREF : SREF_0,
579 INCH : INCH_0
580 };
581
582 /*! ADC12MCTL6 Register */
583 config ADC12MCTL_t ADC12MCTL6 = {
584 EOS : EOS_OFF,
585 SREF : SREF_0,
586 INCH : INCH_0
587 };
588
589 /*! ADC12MCTL7 Register */
590 config ADC12MCTL_t ADC12MCTL7 = {
591 EOS : EOS_OFF,
592 SREF : SREF_0,
593 INCH : INCH_0
594 };
595
596 /*! ADC12MCTL8 Register */
597 config ADC12MCTL_t ADC12MCTL8 = {
598 EOS : EOS_OFF,
599 SREF : SREF_0,
600 INCH : INCH_0
601 };
602
603 /*! ADC12MCTL9 Register */
604 config ADC12MCTL_t ADC12MCTL9 = {
605 EOS : EOS_OFF,
606 SREF : SREF_0,
607 INCH : INCH_0
608 };
609
610 /*! ADC12MCTL10 Register */
611 config ADC12MCTL_t ADC12MCTL10 = {
612 EOS : EOS_OFF,
613 SREF : SREF_0,
614 INCH : INCH_0
615 };
616
617 /*! ADC12MCTL11 Register */
618 config ADC12MCTL_t ADC12MCTL11 = {
619 EOS : EOS_OFF,
620 SREF : SREF_0,
621 INCH : INCH_0
622 };
623
624 /*! ADC12MCTL12 Register */
625 config ADC12MCTL_t ADC12MCTL12 = {
626 EOS : EOS_OFF,
627 SREF : SREF_0,
628 INCH : INCH_0
629 };
630
631 /*! ADC12MCTL13 Register */
632 config ADC12MCTL_t ADC12MCTL13 = {
633 EOS : EOS_OFF,
634 SREF : SREF_0,
635 INCH : INCH_0
636 };
637
638 /*! ADC12MCTL14 Register */
639 config ADC12MCTL_t ADC12MCTL14 = {
640 EOS : EOS_OFF,
641 SREF : SREF_0,
642 INCH : INCH_0
643 };
644
645 /*! ADC12MCTL15 Register */
646 config ADC12MCTL_t ADC12MCTL15 = {
647 EOS : EOS_OFF,
648 SREF : SREF_0,
649 INCH : INCH_0
650 };
651
652 /*! ADC12 Interrupt Enable Register */
653 config ADC12IE_t ADC12IE = {
654 ADC12IE15 : ADC12IE15_OFF,
655 ADC12IE14 : ADC12IE14_OFF,
656 ADC12IE13 : ADC12IE13_OFF,
657 ADC12IE12 : ADC12IE12_OFF,
658 ADC12IE11 : ADC12IE11_OFF,
659 ADC12IE10 : ADC12IE10_OFF,
660 ADC12IE9 : ADC12IE9_OFF,
661 ADC12IE8 : ADC12IE8_OFF,
662 ADC12IE7 : ADC12IE7_OFF,
663 ADC12IE6 : ADC12IE6_OFF,
664 ADC12IE5 : ADC12IE5_OFF,
665 ADC12IE4 : ADC12IE4_OFF,
666 ADC12IE3 : ADC12IE3_OFF,
667 ADC12IE2 : ADC12IE2_OFF,
668 ADC12IE1 : ADC12IE1_OFF,
669 ADC12IE0 : ADC12IE0_OFF
670 };
671
672
673 /*! ADC12MEM0 Register */
674 config Bits16 ADC12MEM0 = 0;
675
676 /*! ADC12MEM1 Register */
677 config Bits16 ADC12MEM1 = 0;
678
679 /*! ADC12MEM2 Register */
680 config Bits16 ADC12MEM2 = 0;
681
682 /*! ADC12MEM3 Register */
683 config Bits16 ADC12MEM3 = 0;
684
685 /*! ADC12MEM4 Register */
686 config Bits16 ADC12MEM4 = 0;
687
688 /*! ADC12MEM5 Register */
689 config Bits16 ADC12MEM5 = 0;
690
691 /*! ADC12MEM6 Register */
692 config Bits16 ADC12MEM6 = 0;
693
694 /*! ADC12MEM7 Register */
695 config Bits16 ADC12MEM7 = 0;
696
697 /*! ADC12MEM8 Register */
698 config Bits16 ADC12MEM8 = 0;
699
700 /*! ADC12MEM9 Register */
701 config Bits16 ADC12MEM9 = 0;
702
703 /*! ADC12MEM10 Register */
704 config Bits16 ADC12MEM10 = 0;
705
706 /*! ADC12MEM11 Register */
707 config Bits16 ADC12MEM11 = 0;
708
709 /*! ADC12MEM12 Register */
710 config Bits16 ADC12MEM12 = 0;
711
712 /*! ADC12MEM13 Register */
713 config Bits16 ADC12MEM13 = 0;
714
715 /*! ADC12MEM14 Register */
716 config Bits16 ADC12MEM14 = 0;
717
718 /*! ADC12MEM15 Register */
719 config Bits16 ADC12MEM15 = 0;
720
721 /*! ADC12IV Register */
722 config Bits16 ADC12IV = ADC12IV_NONE;
723
724 /*! ADC12IFG Register */
725 config Bits16 ADC12IFG = 0;
726
727 /*! ADC12 has 16 interrupt enable */
728 config regIntVect_t interruptSource[16];
729
730 /*! Determine if each Register needs to be forced set or not */
731 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
732 [
733 { register : "ADC12CTL0" , regForceSet : false },
734 { register : "ADC12CTL1" , regForceSet : false },
735 { register : "ADC12IFG" , regForceSet : false },
736 { register : "ADC12IV" , regForceSet : false },
737 { register : "ADC12IE" , regForceSet : false },
738 { register : "ADC12MCTL0" , regForceSet : false },
739 { register : "ADC12MCTL1" , regForceSet : false },
740 { register : "ADC12MCTL2" , regForceSet : false },
741 { register : "ADC12MCTL3" , regForceSet : false },
742 { register : "ADC12MCTL4" , regForceSet : false },
743 { register : "ADC12MCTL5" , regForceSet : false },
744 { register : "ADC12MCTL6" , regForceSet : false },
745 { register : "ADC12MCTL7" , regForceSet : false },
746 { register : "ADC12MCTL8" , regForceSet : false },
747 { register : "ADC12MCTL9" , regForceSet : false },
748 { register : "ADC12MCTL10" , regForceSet : false },
749 { register : "ADC12MCTL11" , regForceSet : false },
750 { register : "ADC12MCTL12" , regForceSet : false },
751 { register : "ADC12MCTL13" , regForceSet : false },
752 { register : "ADC12MCTL14" , regForceSet : false },
753 { register : "ADC12MCTL15" , regForceSet : false },
754 { register : "ADC12MEM0" , regForceSet : false },
755 { register : "ADC12MEM1" , regForceSet : false },
756 { register : "ADC12MEM2" , regForceSet : false },
757 { register : "ADC12MEM3" , regForceSet : false },
758 { register : "ADC12MEM4" , regForceSet : false },
759 { register : "ADC12MEM5" , regForceSet : false },
760 { register : "ADC12MEM6" , regForceSet : false },
761 { register : "ADC12MEM7" , regForceSet : false },
762 { register : "ADC12MEM8" , regForceSet : false },
763 { register : "ADC12MEM9" , regForceSet : false },
764 { register : "ADC12MEM10" , regForceSet : false },
765 { register : "ADC12MEM11" , regForceSet : false },
766 { register : "ADC12MEM12" , regForceSet : false },
767 { register : "ADC12MEM13" , regForceSet : false },
768 { register : "ADC12MEM14" , regForceSet : false },
769 { register : "ADC12MEM15" , regForceSet : false },
770 ];
771 }