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12 /*!
13 * ======== ADC10 ========
14 * MSP430 10-bit Analog to Digital Converter
15 */
16 metaonly module ADC10 inherits IADC {
17
18 /*! ADC10 Start Conversion */
19 enum ADC10SC_t {
20 ADC10SC_OFF = 0x000, /*! No conversion. */
21 ADC10SC = 0x001 /*! Start ADC conversion manually. */
22 };
23
24 /*! ADC10 Enable Conversion */
25 enum ENC_t {
26 ENC_OFF = 0x000, /*! Disable ADC. */
27 ENC = 0x002 /*! Enable ADC. */
28 };
29
30 /*! ADC10 Interrupt Flag */
31 enum ADC10IFG_t {
32 ADC10IFG_OFF = 0x000, /*! Clear ADC interrupt flag. */
33 ADC10IFG = 0x004 /*! Set ADC interrupt flag. */
34 };
35
36 /*! ADC10 Interrupt Enable */
37 enum ADC10IE_t {
38 ADC10IE_OFF = 0x000, /*! Disable ADC interrupt. */
39 ADC10IE = 0x008 /*! Enable ADC interrupt. */
40 };
41
42 /*! ADC10 On/Enable */
43 enum ADC10ON_t {
44 ADC10ON_OFF = 0x000, /*! Switch Off ADC10. */
45 ADC10ON = 0x010 /*! Switch On ADC10. */
46 };
47
48 /*! ADC10 Reference on */
49 enum REFON_t {
50 REFON_OFF = 0x000, /*! Disable ADC reference generator. */
51 REFON = 0x020 /*! Enable ADC reference generator. */
52 };
53
54 /*! ADC10 Ref 0:1.5V / 1:2.5V */
55 enum REF2_5V_t {
56 REF2_5V_OFF = 0x000, /*! Set reference voltage generator = 1.5V. */
57 REF2_5V = 0x040 /*! Set reference voltage generator = 2.5V. */
58 };
59
60 /*! ADC10 Multiple SampleConversion */
61 enum MSC_t {
62 MSC_OFF = 0x000, /*! Disable multiple sample and conversion. */
63 MSC = 0x080 /*! Enable multiple sample and conversion. */
64 };
65
66 /*! ADC10 Reference Burst Mode */
67 enum REFBURST_t {
68 REFBURST_OFF = 0x000, /*! Reference buffer on continuously. */
69 REFBURST = 0x100 /*! Reference buffer on only during sample-and-conversion. */
70 };
71
72 /*! ADC10 Enable output of Ref. */
73 enum REFOUT_t {
74 REFOUT_OFF = 0x000, /*! Reference output off. */
75 REFOUT = 0x200 /*! Reference output on. */
76 };
77
78 /*! ADC10 Sampling Rate 0:200ksps / 1:50ksps */
79 enum ADC10SR_t {
80 ADC10SR_OFF = 0x000, /*! Reference buffer supports up to ~200 ksps. */
81 ADC10SR = 0x400 /*! Reference buffer supports up to ~50 ksps. */
82 };
83
84 /*! ADC10 Sample Hold Select 0 */
85 enum ADC10SHT_t {
86 ADC10SHT_0 = (0*0x800u), /*! 4 x ADC10CLKs. */
87 ADC10SHT_1 = (1*0x800u), /*! 8 x ADC10CLKs. */
88 ADC10SHT_2 = (2*0x800u), /*! 16 x ADC10CLKs. */
89 ADC10SHT_3 = 3*0x800u /*! 64 x ADC10CLKs. */
90 };
91
92 /*! ADC10 Reference Select 0 */
93 enum SREF_t {
94 SREF_0 = (0*0x2000u), /*! VR+ = VCC and VR- = VSS. */
95 SREF_1 = (1*0x2000u), /*! VR+ = VREF+ and VR- = VSS. */
96 SREF_2 = (2*0x2000u), /*! VR+ = VeREF+ and VR- = VSS. */
97 SREF_3 = (3*0x2000u), /*! VR+ = Buffered VeREF+ and VR- = VSS. */
98 SREF_4 = (4*0x2000u), /*! VR+ = VCC and VR- = VREF-/ VeREF-. */
99 SREF_5 = (5*0x2000u), /*! VR+ = VREF+ and VR- = VREF-/ VeREF-. */
100 SREF_6 = (6*0x2000u), /*! VR+ = VeREF+ and VR- = VREF-/ VeREF-. */
101 SREF_7 = 7*0x2000u /*! VR+ = Buffered VeREF+ and VR- = VREF-/ VeREF-. */
102 };
103
104 enum ADC10BUSY_t {
105 ADC10BUSY_OFF = 0x0000, /*! No operation is active. */
106 ADC10BUSY = 0x0001 /*! A sequence, sample, or conversion is active. */
107 };
108
109 /*! Types of conversion */
110 enum CONSEQ_t {
111 CONSEQ_0 = (0*2u), /*! Single channel single conversion. */
112 CONSEQ_1 = (1*2u), /*! Sequence of channels. */
113 CONSEQ_2 = (2*2u), /*! Repeat single channel. */
114 CONSEQ_3 = 3*2u /*! Repeat sequence of channels. */
115 };
116
117 /*! ADC10 Clock Source */
118 enum ADC10SSEL_t {
119 ADC10SSEL_0 = (0*8u), /*! ADC10OSC. */
120 ADC10SSEL_1 = (1*8u), /*! ACLK. */
121 ADC10SSEL_2 = (2*8u), /*! MCLK.*/
122 ADC10SSEL_3 = 3*8u /*! SMCLK. */
123 };
124
125 /*! ADC10 Clock Divider */
126 enum ADC10DIV_t {
127 ADC10DIV_0 = (0*0x20u), /*! Divide by 1. */
128 ADC10DIV_1 = (1*0x20u), /*! Divide by 2. */
129 ADC10DIV_2 = (2*0x20u), /*! Divide by 3. */
130 ADC10DIV_3 = (3*0x20u), /*! Divide by 4. */
131 ADC10DIV_4 = (4*0x20u), /*! Divide by 5. */
132 ADC10DIV_5 = (5*0x20u), /*! Divide by 6. */
133 ADC10DIV_6 = (6*0x20u), /*! Divide by 7. */
134 ADC10DIV_7 = 7*0x20u /*! Divide by 8. */
135 };
136
137 /*! ADC10 input signal inversion */
138 enum ISSH_t {
139 ISSH_OFF = 0x0000, /*! Input signal not inverted. */
140 ISSH = 0x0100 /*! Input signal inverted. */
141 };
142
143 /*! ADC10 output as 2's complement */
144 enum ADC10DF_t {
145 ADC10DF_OFF = 0x0000, /*! ADC10 Data Format as binary. */
146 ADC10DF = 0x0200 /*! ADC10 Data Format as 2's complement */
147 };
148
149 /*! ADC10 trigger */
150 enum SHS_t {
151 SHS_0 = (0*0x400u), /*! ADC10SC. */
152 SHS_1 = (1*0x400u), /*! Timer_A OUT1. */
153 SHS_2 = (2*0x400u), /*! Timer_A OUT0. */
154 SHS_3 = 3*0x400u /*! Timer_A OUT2. */
155 };
156
157 /*! ADC10 Channel Selection */
158 enum INCH_t {
159 INCH_0 = (0*0x1000u), /*! ADC Channel 0. */
160 INCH_1 = (1*0x1000u), /*! ADC Channel 1. */
161 INCH_2 = (2*0x1000u), /*! ADC Channel 2. */
162 INCH_3 = (3*0x1000u), /*! ADC Channel 3. */
163 INCH_4 = (4*0x1000u), /*! ADC Channel 4. */
164 INCH_5 = (5*0x1000u), /*! ADC Channel 5. */
165 INCH_6 = (6*0x1000u), /*! ADC Channel 6. */
166 INCH_7 = (7*0x1000u), /*! ADC Channel 7. */
167 INCH_8 = (8*0x1000u), /*! ADC VeRef+. */
168 INCH_9 = (9*0x1000u), /*! ADC VeRef-. */
169 INCH_10 = (10*0x1000u), /*! Temperature Sensor. */
170 INCH_11 = (11*0x1000u), /*! ADC convert VCC. */
171 INCH_12 = (12*0x1000u), /*! ADC Channel 12. */
172 INCH_13 = (13*0x1000u), /*! ADC Channel 13. */
173 INCH_14 = (14*0x1000u), /*! ADC Channel 14. */
174 INCH_15 = 15*0x1000u /*! ADC Channel 15. */
175 };
176
177 /*!
178 * ======== ADC10CT_t ========
179 * Data transfer modes
180 *
181 * @see #ADC10DTC0
182 */
183 enum ADC10CT_t {
184 ADC10CT_OFF = 0x000, /*! Data is transferred is stopped after every conversion. */
185 ADC10CT = 0x004 /*! Data is transferred continuously after every conversion. */
186 }
187
188 /*!
189 * ======== ADC10TB_t ========
190 * Block data transfer modes
191 *
192 * @see #ADC10DTC0
193 */
194 enum ADC10TB_t {
195 ADC10TB_OFF = 0x000, /*! One-block transfer mode. */
196 ADC10TB = 0x008 /*! Two-block transfer mode. */
197 }
198
199
200 /*!
201 * ======== ADC10CTL0_t ========
202 * ADC10 Control Register 0
203 *
204 * @see #ADC10CTL0
205 */
206 struct ADC10CTL0_t {
207 ADC10SC_t ADC10SC; /*! Start conversion. Software-controlled sample-and-conversion start.
208 * ADC10SC and ENC may be set together with one instruction. ADC10SC is
209 * reset automatically.
210 * 0 No sample-and-conversion start
211 * 1 Start sample-and-conversion */
212 ENC_t ENC; /*! Enable conversion
213 * 0 ADC10 disabled
214 * 1 ADC10 enabled */
215 ADC10IFG_t ADC10IFG; /*! ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion
216 * result. It is automatically reset when the interrupt request is accepted, or it may
217 * be reset by software. When using the DTC this flag is set when a block of
218 * transfers is completed.
219 * 0 No interrupt pending
220 * 1 Interrupt pending */
221 ADC10IE_t ADC10IE; /*! ADC10 interrupt enable
222 * 0 Interrupt disabled
223 * 1 Interrupt enabled */
224 ADC10ON_t ADC10ON; /*! ADC10 on
225 * 0 ADC10 off
226 * 1 ADC10 on */
227 REFON_t REFON; /*! Reference generator on
228 * 0 Reference off
229 * 1 Reference on */
230 REF2_5V_t REF2_5V; /*! Reference-generator voltage. REFON must also be set.
231 * 0 1.5 V
232 * 1 2.5 V */
233 MSC_t MSC; /*! Multiple sample and conversion. Valid only for sequence or repeated modes.
234 * 0 The sampling requires a rising edge of the SHI signal to trigger each
235 * sample-and-conversion.
236 * 1 The first rising edge of the SHI signal triggers the sampling timer, but
237 * further sample-and-conversions are performed automatically as soon
238 * as the prior conversion is completed */
239 REFBURST_t REFBURST; /*! Reference burst.
240 * 0 Reference buffer on continuously
241 * 1 Reference buffer on only during sample-and-conversion */
242 REFOUT_t REFOUT; /*! Reference output
243 * 0 Reference output off
244 * 1 Reference output on, use internal reference
245 voltage externally on pin VREF+ */
246 ADC10SR_t ADC10SR; /*! ADC10 sampling rate. This bit selects the reference buffer drive capability for
247 * the maximum sampling rate. Setting ADC10SR reduces the current
248 * consumption of the reference buffer.
249 * 0 Reference buffer supports up to ~200 ksps
250 * 1 Reference buffer supports up to ~50 ksps */
251 ADC10SHT_t ADC10SHT; /*! ADC10 sample-and-hold time
252 * 00 4 x ADC10CLKs
253 * 01 8 x ADC10CLKs
254 * 10 16 x ADC10CLKs
255 * 11 64 x ADC10CLKs */
256 SREF_t SREF; /*! Select reference
257 * 000 VR+ = VCC and VR- = VSS
258 * 001 VR+ = VREF+ and VR- = VSS
259 * 010 VR+ = VeREF+ and VR- = VSS
260 * 011 VR+ = Buffered VeREF+ and VR- = VSS
261 * 100 VR+ = VCC and VR- = VREF-/ VeREF-
262 * 101 VR+ = VREF+ and VR- = VREF-/ VeREF-
263 * 110 VR+ = VeREF+ and VR- = VREF-/ VeREF-
264 * 111 VR+ = Buffered VeREF+ and VR- = VREF-/ VeREF- */
265 }
266
267 /*!
268 * ======== ADC10CTL1_t ========
269 * ADC10 Control Register 1
270 *
271 * @see #ADC10CTL1
272 */
273 struct ADC10CTL1_t {
274 ADC10BUSY_t ADC10BUSY; /*! ADC10 busy. This bit indicates an active sample or conversion operation
275 * 0 No operation is active.
276 * 1 A sequence, sample, or conversion is active. */
277 CONSEQ_t CONSEQ; /*! Conversion sequence mode select
278 * 00 Single-channel-single-conversion
279 * 01 Sequence-of-channels
280 * 10 Repeat-single-channel
281 * 11 Repeat-sequence-of-channels */
282 ADC10SSEL_t ADC10SSEL; /*! ADC10 clock source select
283 * 00 ADC10OSC
284 * 01 ACLK
285 * 10 MCLK
286 * 11 SMCLK */
287 ADC10DIV_t ADC10DIV; /*! ADC10 clock divider
288 * 000 /1
289 * 001 /2
290 * 010 /3
291 * 011 /4
292 * 100 /5
293 * 101 /6
294 * 110 /7
295 * 111 /8 */
296 ISSH_t ISSH; /*! Invert signal sample-and-hold
297 * 0 The sample-input signal is not inverted.
298 * 1 The sample-input signal is inverted. */
299 ADC10DF_t ADC10DF; /*! ADC10 data format
300 * 0 Straight binary
301 * 1 2s complement */
302 SHS_t SHS; /*! Sample-and-hold source select
303 * 00 ADC10SC bit
304 * 01 Timer_A.OUT1
305 * 10 Timer_A.OUT0
306 * 11 Timer_A.OUT2 (Timer_A.OUT1 on MSP430x20x2 devices) */
307 INCH_t INCH; /*! Input channel select. These bits select the channel for a single-conversion or
308 * the highest channel for a sequence of conversions.
309 * 0000 A0
310 * 0001 A1
311 * 0010 A2
312 * 0011 A3
313 * 0100 A4
314 * 0101 A5
315 * 0110 A6
316 * 0111 A7
317 * 1000 VeREF+
318 * 1001 VREF-/VeREF-
319 * 1010 Temperature sensor
320 * 1011 (VCC � VSS) / 2
321 * 1100 A12
322 * 1101 A13
323 * 1110 A14
324 * 1111 A15 */
325 }
326
327 /*!
328 * ======== ADC10DTC0_t ========
329 * Data Transfer Control Register 0
330 *
331 * @see #ADC10DTC0
332 */
333 struct ADC10DTC0_t {
334 ADC10TB_t ADC10TB; /*! ADC10 two-block mode
335 * 0 One-block transfer mode
336 * 1 Two-block transfer mode */
337 ADC10CT_t ADC10CT; /*! ADC10 continuous transfer
338 * 0 Data transfer stops when one block (one-block mode) or two blocks
339 * (two-block mode) have completed.
340 * 1 Data is transferred continuously. DTC operation is stopped only if
341 * ADC10CT cleared, or ADC10SA is written to. */
342 }
343
344 instance:
345 /*! Control Register 0 */
346 config ADC10CTL0_t ADC10CTL0 = {
347 ADC10SC : ADC10SC_OFF,
348 ENC : ENC_OFF,
349 ADC10IFG: ADC10IFG_OFF,
350 ADC10IE : ADC10IE_OFF,
351 ADC10ON : ADC10ON_OFF,
352 REFON : REFON_OFF,
353 REF2_5V : REF2_5V_OFF,
354 MSC : MSC_OFF,
355 REFBURST: REFBURST_OFF,
356 REFOUT : REFOUT_OFF,
357 ADC10SR : ADC10SR_OFF,
358 ADC10SHT: ADC10SHT_0,
359 SREF : SREF_0
360 };
361
362 /*! Control Register 1 */
363 config ADC10CTL1_t ADC10CTL1 = {
364 ADC10BUSY : ADC10BUSY_OFF,
365 CONSEQ : CONSEQ_0,
366 ADC10SSEL : ADC10SSEL_0,
367 ADC10DIV : ADC10DIV_0,
368 ISSH : ISSH_OFF,
369 ADC10DF : ADC10DF_OFF,
370 SHS : SHS_0,
371 INCH : INCH_0
372 };
373
374 /*!
375 * Analog (Input) Enable Control Register 0
376 *
377 * Bit n enables the corresponding pin for analog
378 * input. Bit 0 corresponds to A0, bit 1 corresponds to A1, ...
379 */
380 config Bits16 ADC10AE0 = 0;
381
382 /*!
383 * Analog (Input) Enable Control Register 1
384 *
385 * Bits 0, 1, 2, and 3 are reserved.
386 *
387 * Starting with bit 4, bit n enables pin n+8 for analog
388 * input: Bit 4 corresponds to A12, bit 5 corresponds to A13, ...
389 */
390 config Bits16 ADC10AE1 = 0;
391
392 /*! Data Transfer Control Register 0 */
393 config ADC10DTC0_t ADC10DTC0 = {
394 ADC10TB : ADC10TB_OFF,
395 ADC10CT : ADC10CT_OFF
396 };
397
398 /*!
399 * Data Transfer Control Register 1
400 *
401 * This register defines the number of transfers in each block: 0
402 * implies DTC is disabled, 1 through 0xff are valid transfer counts.
403 */
404 config Bits8 ADC10DTC1 = 0;
405
406 /*! Data Transfer Start Address */
407 config Bits16 *ADC10SA = 0x200;
408
409 /*! ADC10 has 1 interrupt enable */
410 config regIntVect_t interruptSource[1];
411
412 /*! Determine if each Register needs to be forced set or not */
413 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
414 [
415 { register : "ADC10CTL0" , regForceSet : false },
416 { register : "ADC10CTL1" , regForceSet : false },
417 { register : "ADC10AE0" , regForceSet : false },
418 { register : "ADC10AE1" , regForceSet : false },
419 { register : "ADC10DTC0" , regForceSet : false },
420 { register : "ADC10DTC1" , regForceSet : false },
421 { register : "ADC10SA" , regForceSet : false }
422 ];
423 }