1 /*
2 * Copyright (c) 2012 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== ITMS320TCI663x.xdc ========
15 *
16 */
17
18 package ti.catalog.c6000;
19
20 metaonly interface ITMS320TCI663x inherits ti.catalog.ICpuDataSheet
21 {
22 /* These are the available sizes for L1 caches */
23 config long cacheSizeL1[string] = [
24 ["0k", 0x0000],
25 ["4k", 0x1000],
26 ["8k", 0x2000],
27 ["16k", 0x4000],
28 ["32k", 0x8000],
29 ];
30
31 /* These are the available sizes for L2 cche */
32 config long cacheSizeL2[string] = [
33 ["0k", 0x000000],
34 ["32k", 0x008000],
35 ["64k", 0x010000],
36 ["128k", 0x020000],
37 ["256k", 0x040000],
38 ["512k", 0x080000],
39 ["1024k", 0x100000]
40 ];
41
42 /* This is used by platform wizard for setting default cache sizes */
43 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
44 ['l1PMode', {
45 desc:"L1P Cache",
46 base: 0x00E00000,
47 map : [
48 ["0k",0x0000],
49 ["4k",0x1000],
50 ["8k",0x2000],
51 ["16k",0x4000],
52 ["32k",0x8000]
53 ],
54 defaultValue: "32k",
55 memorySection: "L1PSRAM"
56 }],
57 ['l1DMode', {
58 desc:"L1D Cache",
59 base: 0x00F00000,
60 map : [
61 ["0k",0x0000],
62 ["4k",0x1000],
63 ["8k",0x2000],
64 ["16k",0x4000],
65 ["32k",0x8000]
66 ],
67 defaultValue: "32k",
68 memorySection: "L1DSRAM"
69 }],
70 ['l2Mode', {
71 desc:"L2 Cache",
72 base: 0x00800000,
73 map : [
74 ["0k",0x0000],
75 ["32k",0x8000],
76 ["64k",0x10000],
77 ["128k", 0x020000],
78 ["256k", 0x040000],
79 ["512k", 0x080000],
80 ["1024k", 0x100000]
81 ],
82 defaultValue: "0k",
83 memorySection: "L2SRAM"}
84 ],
85 ];
86
87 instance:
88
89 override config string cpuCore = "6600";
90 override config string isa = "66";
91 override config string cpuCoreRevision = "1.0";
92
93 override config int minProgUnitSize = 1;
94 override config int minDataUnitSize = 1;
95 override config int dataWordSize = 4;
96
97 /*!
98 * ======== memMap ========
99 * The default memory map for this device
100 */
101 config xdc.platform.IPlatform.Memory memMap[string] = [
102 ["L2SRAM", {
103 comment: "1MB L2 SRAM/CACHE",
104 name: "L2SRAM",
105 base: 0x00800000,
106 len: 0x00100000,
107 space: "code/data",
108 access: "RWX"
109 }],
110
111 ["L1PSRAM", {
112 comment: "32KB RAM/CACHE L1 program memory",
113 name: "L1PSRAM",
114 base: 0x00E00000,
115 len: 0x00008000,
116 space: "code",
117 access: "RWX"
118 }],
119
120 ["L1DSRAM", {
121 comment: "32KB RAM/CACHE L1 data memory",
122 name: "L1DSRAM",
123 base: 0x00F00000,
124 len: 0x00008000,
125 space: "data",
126 access: "RW"
127 }],
128
129 ["MSMCSRAM", {
130 comment: "6MB MSMC SRAM",
131 name: "MSMCSRAM",
132 base: 0x0C000000,
133 len: 0x00600000,
134 space: "code/data",
135 access: "RWX"
136 }],
137 ];
138 };
139 /*
140 * @(#) ti.catalog.c6000; 1, 0, 0, 0,399; 8-17-2012 22:13:34; /db/ztree/library/trees/platform/platform-n27x/src/
141 */
142