1    /*
     2     *  Copyright (c) 2012 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * */
    12    
    13    /*
    14     *  ======== ITI8148.xdc ========
    15     *
    16     */
    17    
    18    /*!
    19     *  ======== ITI8148 ========
    20     *  An interface implemented by all TI8148 devices
    21     *
    22     *  This interface is defined to factor common data about all TI8148 type devices
    23     *  into a single place; they all have the same internal memory.
    24     */
    25    metaonly interface ITI8148 inherits ti.catalog.ICpuDataSheet
    26    {
    27    instance:
    28        config ti.catalog.peripherals.hdvicp2.HDVICP2.Instance hdvicp0;
    29    
    30        override config string cpuCore           = "CM3";
    31        override config string isa               = "v7M";
    32        override config string cpuCoreRevision   = "1.0";
    33        override config int    minProgUnitSize   = 1;
    34        override config int    minDataUnitSize   = 1;
    35        override config int    dataWordSize      = 4;
    36    
    37        /*!
    38         *  ======== memMap ========
    39         *  The memory map returned be getMemoryMap().
    40         */
    41        config xdc.platform.IPlatform.Memory memMap[string] = [
    42    
    43            /*
    44             * AMMU mapped L2 BOOT virtual address
    45             * Physical address is 0x5502_0000, virt is 0x00000000
    46             * Reset vectors and other boot code is placed here.
    47             *
    48             * Note that actual L2 RAM is 256K starting at 0x5502_0000.
    49             * The first 16K is reserved for reset vectors (i.e. L2_BOOT).
    50             * The remaining 240K is placed in the L2_RAM definition.
    51             */
    52            ["L2_BOOT", {
    53                name: "L2_BOOT",
    54                base: 0x00000000,
    55                len:  0x4000
    56            }],
    57    
    58            /*
    59             * AMMU mapped L2 RAM virtual address
    60             * Physical address is 0x5502_4000, virt is 0x2000_4000
    61             *
    62             * Note that actual L2 RAM is 256K starting at 0x5502_0000.
    63             * The first 16K is reserved for reset vectors (i.e. L2_BOOT).
    64             * The remaining 240K is placed in the L2_RAM definition.
    65             */
    66            ["L2_RAM", {
    67                name: "L2_RAM",
    68                base: 0x20004000,
    69                len:  0x3C000
    70            }],
    71    
    72            /*
    73             * OCMC (On-chip RAM)
    74             * Physical address is 0x40300000
    75             * Size is 128K
    76             */
    77            ["OCMC", {
    78                name: "OCMC",
    79                base: 0x00300000,
    80                len:  0x20000
    81            }],
    82        ];
    83    };
    84    /*
    85     *  @(#) ti.catalog.arm.cortexm3; 1, 0, 0,155; 8-17-2012 22:13:11; /db/ztree/library/trees/platform/platform-n27x/src/
    86     */
    87