1 /*
2 * Copyright (c) 2012 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * */
12
13 /*
14 * ======== Platform.xdc ========
15 * Platform support for evmTI816X
16 *
17 */
18
19 package ti.platforms.evmTI816X;
20
21 /*!
22 * ======== Platform ========
23 * Platform support for the evmTI816X
24 *
25 * This module implements xdc.platform.IPlatform and defines configuration
26 * parameters that correspond to this platform's Cpu's, Board's, etc.
27 *
28 * The configuration parameters are initialized in this package's
29 * configuration script (package.cfg) and "bound" to the TCOM object
30 * model. Once they are part of the model, these parameters are
31 * queried by a program's configuration script.
32 *
33 * This particular platform has 4 CPU's, a host GPP, 2 M3's, and a
34 * C674 DSP.
35 */
36 metaonly module Platform inherits xdc.platform.IPlatform
37 {
38 readonly config xdc.platform.IPlatform.Board BOARD = {
39 id: "0",
40 boardName: "evmTI816X",
41 boardFamily: "evmTI816X",
42 boardRevision: null
43 };
44
45 /* C674 GEM */
46 readonly config xdc.platform.IExeContext.Cpu GEM = {
47 id: "0",
48 clockRate: 800.0,
49 catalogName: "ti.catalog.c6000",
50 deviceName: "TMS320TI816X",
51 revision: ""
52 };
53
54 /* M3 Subsystem */
55 readonly config xdc.platform.IExeContext.Cpu DSS = {
56 id: "1",
57 clockRate: 250.0,
58 catalogName: "ti.catalog.arm.cortexm3",
59 deviceName: "TMS320TI816X",
60 revision: "1.0"
61 };
62
63 /* GPP */
64 readonly config xdc.platform.IExeContext.Cpu GPP = {
65 id: "2",
66 clockRate: 1000.0, /* Typically set by the HLOS */
67 catalogName: "ti.catalog.arm.cortexa8",
68 deviceName: "TMS320TI816X",
69 revision: "1.0"
70 };
71
72 instance:
73
74 override readonly config xdc.platform.IPlatform.Memory
75 externalMemoryMap[string] = [
76 ["DDR3_HOST", {
77 comment: "DDR3 Memory reserved for use by the A8",
78 name: "DDR3_HOST",
79 base: 0x80000000,
80 len: 0x0B000000 /* 176 MB */
81 }],
82 ["DDR3_DSP", {
83 comment: "DDR3 Memory reserved for use by the C674",
84 name: "DDR3_DSP",
85 base: 0x8B000000,
86 len: 0x02000000 /* 32 MB */
87 }],
88 ["DDR3_SR1", {
89 comment: "DDR3 Memory reserved for use by SharedRegion 1",
90 name: "DDR3_SR1",
91 base: 0x8D000000,
92 len: 0x00C00000 /* 12 MB */
93 }],
94 ["DDR3_HDVPSS", {
95 comment: "DDR3 Memory reserved for use by HDVPSS",
96 name: "DDR3_HDVPSS",
97 base: 0x8DC00000,
98 len: 0x00200000 /* 2 MB */
99 }],
100 ["DDR3_V4L2", {
101 comment: "DDR3 Memory reserved for use by V4L2",
102 name: "DDR3_V4L2",
103 base: 0x8DE00000,
104 len: 0x00200000 /* 2 MB */
105 }],
106 ["DDR3_SR0", {
107 comment: "DDR3 Memory reserved for use by SharedRegion 0",
108 name: "DDR3_SR0",
109 base: 0x8E000000,
110 len: 0x01000000 /* 16 MB */
111 }],
112 ["DDR3_M3", {
113 comment: "DDR3 Memory reserved for use by the M3 core",
114 name: "DDR3_M3",
115 base: 0x8F000000,
116 len: 0x01000000 /* 16 MB */
117 }],
118 ];
119
120 /*
121 * ======== l1PMode ========
122 * Define the amount of L1P RAM used for L1 Program Cache.
123 *
124 * Check the device documentation for valid values.
125 */
126 config String l1PMode = "32k";
127
128 /*
129 * ======== l1DMode ========
130 * Define the amount of L1D RAM used for L1 Data Cache.
131 *
132 * Check the device documentation for valid values.
133 */
134 config String l1DMode = "32k";
135
136 /*
137 * ======== l2Mode ========
138 * Define the amount of L2 RAM used for L2 Cache.
139 *
140 * Check the device documentation for valid values.
141 */
142 config String l2Mode = "0k";
143 };
144 /*
145 * @(#) ti.platforms.evmTI816X; 1, 0, 0,68; 8-17-2012 22:16:09; /db/ztree/library/trees/platform/platform-n27x/src/
146 */
147