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19 package ti.platforms.evmTI813X;
20
21 /*!
22 * ======== Platform ========
23 * Platform support for the evmTI813X
24 *
25 * This module implements xdc.platform.IPlatform and defines configuration
26 * parameters that correspond to this platform's Cpu's, Board's, etc.
27 *
28 * The configuration parameters are initialized in this package's
29 * configuration script (package.cfg) and "bound" to the TCOM object
30 * model. Once they are part of the model, these parameters are
31 * queried by a program's configuration script.
32 *
33 * This particular platform has 3 CPU's, a host GPP, and 2 M3's.
34 */
35 metaonly module Platform inherits xdc.platform.IPlatform
36 {
37 /*!
38 * ======== BOARD ========
39 * This platform's board attributes
40 */
41 readonly config xdc.platform.IPlatform.Board BOARD = {
42 id: "0",
43 boardName: "evmTI813X",
44 boardFamily: "evmTI813X",
45 boardRevision: null
46 };
47
48
49 readonly config xdc.platform.IExeContext.Cpu DSS = {
50 id: "0",
51 clockRate: 200.0,
52 catalogName: "ti.catalog.arm.cortexm3",
53 deviceName: "TMS320TI813X",
54 revision: "1.0"
55 };
56
57
58 readonly config xdc.platform.IExeContext.Cpu GPP = {
59 id: "1",
60 clockRate: 600.0,
61 catalogName: "ti.catalog.arm.cortexa8",
62 deviceName: "TMS320TI813X",
63 revision: "1.0"
64 };
65
66 instance:
67
68 override readonly config xdc.platform.IPlatform.Memory
69 externalMemoryMap[string] = [
70 ["DDR3_HOST", {
71 comment: "DDR3 Memory reserved for use by the A8",
72 name: "DDR3_HOST",
73 base: 0x80000000,
74 len: 0x0D000000
75 }],
76 ["DDR3_SR1", {
77 comment: "DDR3 Memory reserved for use by SharedRegion 1",
78 name: "DDR3_SR1",
79 base: 0x8D000000,
80 len: 0x00C00000
81 }],
82 ["DDR3_HDVPSS", {
83 comment: "DDR3 Memory reserved for use by HDVPSS",
84 name: "DDR3_HDVPSS",
85 base: 0x8DC00000,
86 len: 0x00200000
87 }],
88 ["DDR3_V4L2", {
89 comment: "DDR3 Memory reserved for use by V4L2",
90 name: "DDR3_V4L2",
91 base: 0x8DE00000,
92 len: 0x00200000
93 }],
94 ["DDR3_SR0", {
95 comment: "DDR3 Memory reserved for use by SharedRegion 0",
96 name: "DDR3_SR0",
97 base: 0x8E000000,
98 len: 0x01000000
99 }],
100 ["DDR3_M3", {
101 comment: "DDR3 Memory reserved for use by the M3 core",
102 name: "DDR3_M3",
103 base: 0x8F000000,
104 len: 0x01000000
105 }],
106 ];
107
108 };
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