1    /* --COPYRIGHT--,EPL
     2     *  Copyright (c) 2008 Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     * 
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     * 
    11     * --/COPYRIGHT--*/
    12    import ti.catalog.msp430.peripherals.clock.IClock;
    13    
    14    /*!
    15     *  ======== WDT+ ========
    16     *  MSP430 Watchdog Timer+
    17     */
    18    metaonly module WDTplus inherits IWDT
    19    {
    20        enum WDTPW_t {
    21            WDTPW_OFF = 0x0000,         /*! no Watchdog password value */
    22            WDTPW     = 0x5A00          /*! Watchdog password */
    23        };
    24        
    25        enum WDTHOLD_t {
    26            WDTHOLD_OFF = 0x0000,       /*! Watchdog timer+ is not stopped */
    27            WDTHOLD     = 0x0080        /*! Watchdog timer+ is stopped */
    28        };
    29        
    30        enum WDTNMIES_t {
    31            WDTNMIES_OFF = 0x0000,      /*! NMI on rising edge */
    32            WDTNMIES     = 0x0040       /*! NMI on falling edge */
    33        };
    34        
    35        enum WDTNMI_t {
    36            WDTNMI_OFF = 0x0000,        /*! Reset function */
    37            WDTNMI     = 0x0020         /*! NMI function */
    38        };
    39    
    40        enum WDTTMSEL_t {
    41            WDTTMSEL_OFF = 0x0000,      /*! Watchdog mode */
    42            WDTTMSEL     = 0x0010       /*! Interval timer mode */
    43        };
    44        
    45        enum WDTCNTCL_t {
    46            WDTCNTCL_OFF = 0x0000,      /*! No action */
    47            WDTCNTCL     = 0x0008       /*! WDTCNT = 0000h */
    48        };
    49        
    50        enum WDTSSEL_t {
    51            WDTSSEL_OFF = 0x0000,       /*! SMCLK */
    52            WDTSSEL     = 0x0004        /*! ACLK */
    53        };
    54    
    55        enum WDTIS1_t {
    56            WDTIS1_OFF = 0x0000,        /*! Watchdog clock source bit1 disabled */
    57            WDTIS1     = 0x0002         /*! Watchdog clock source bit1 enabled */
    58        };
    59        
    60        enum WDTIS0_t {
    61            WDTIS0_OFF = 0x0000,        /*! Watchdog clock source bit0 disabled */
    62            WDTIS0     = 0x0001         /*! Watchdog clock source bit0 enabled */
    63        };
    64        
    65        /* WDTCTL Register */
    66        struct WDTCTL_t {
    67            WDTPW_t     WDTPW;          /*! WDT+ password */
    68            WDTHOLD_t   WDTHOLD;        /*! Watchdog timer+ hold. This bit stops the watchdog timer+. Setting
    69                                         *WDTHOLD = 1 when the WDT+ is not in use conserves power.
    70                                         *  0    Watchdog timer+ is not stopped
    71                                         *  1    Watchdog timer+ is stopped
    72                                         */
    73            WDTNMIES_t  WDTNMIES;       /*! Watchdog timer+ NMI edge select. This bit selects the interrupt edge for the
    74                                         *NMI interrupt when WDTNMI = 1. Modifying this bit can trigger an NMI. Modify
    75                                         *this bit when WDTIE = 0 to avoid triggering an accidental NMI.
    76                                         *  0    NMI on rising edge
    77                                         *  1    NMI on falling edge
    78                                         */
    79            WDTNMI_t    WDTNMI;         /*! Watchdog timer+ NMI select. This bit selects the function for the RST/NMI pin.
    80                                         *  0    Reset function
    81                                         *  1    NMI function
    82                                         */
    83            WDTTMSEL_t  WDTTMSEL;       /*! Watchdog timer+ mode select
    84                                         *  0    Watchdog mode
    85                                         *  1    Interval timer mode
    86                                         */
    87            WDTCNTCL_t  WDTCNTCL;       /*! Watchdog timer+ counter clear. Setting WDTCNTCL = 1 clears the count
    88                                         *value to 0000h. WDTCNTCL is automatically reset.
    89                                         *  0    No action
    90                                         *  1    WDTCNT = 0000h
    91                                         */
    92            WDTSSEL_t   WDTSSEL;        /*! Watchdog timer+ clock source select
    93                                         *  0    SMCLK
    94                                         *  1    ACLK
    95                                         */
    96            WDTIS0_t    WDTIS0;         /*! Watchdog timer+ interval select. These bits select the watchdog timer+
    97                                         *interval to set the WDTIFG flag and/or generate a PUC.
    98                                         *  00   Watchdog clock source /32768
    99                                         *  01   Watchdog clock source /8192
   100                                         *  10   Watchdog clock source /512
   101                                         *  11   Watchdog clock source /64
   102                                         */
   103            WDTIS1_t    WDTIS1;          /*! Watchdog timer+ interval select. These bits select the watchdog timer+
   104                                          *interval to set the WDTIFG flag and/or generate a PUC.
   105                                          *  00   Watchdog clock source /32768
   106                                          *  01   Watchdog clock source /8192
   107                                          *  10   Watchdog clock source /512
   108                                          *  11   Watchdog clock source /64
   109                                          */
   110        }
   111        
   112        create(IClock.Instance clock);
   113        
   114    instance:
   115        /*! WDTCTL, Watchdog Timer+ Register */
   116        config WDTCTL_t WDTCTL = {
   117            WDTPW       : WDTPW,
   118            WDTHOLD     : WDTHOLD_OFF,
   119            WDTNMIES    : WDTNMIES_OFF,
   120            WDTNMI      : WDTNMI_OFF,
   121            WDTTMSEL    : WDTTMSEL_OFF,
   122            WDTCNTCL    : WDTCNTCL_OFF,
   123            WDTSSEL     : WDTSSEL_OFF,
   124            WDTIS0      : WDTIS0_OFF,
   125            WDTIS1      : WDTIS1_OFF,
   126        };
   127    
   128        /*! Determine if each Register needs to be forced set or not */
   129        readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
   130        [
   131            { register : "WDTCTL" , regForceSet : true }
   132        ];
   133        
   134        /*!
   135         *  ======== baseAddr ========
   136         *  Address of the peripheral's control register.
   137         *
   138         *  A peripheral's registers are commonly accessed through a structure
   139         *  that defines the offsets of a particular register from the lowest
   140         *  address mapped to a peripheral. That lowest address is specified by
   141         *  this parameter.
   142         */
   143        config UInt baseAddr;
   144    
   145        /*! @_nodoc */
   146        config IClock.Instance clock;
   147    }