1 /* --COPYRIGHT--,EPL
2 * Copyright (c) 2008 Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * --/COPYRIGHT--*/
12 /*!
13 * ======== ITimer_A ========
14 * MSP430 ITimer_A interface
15 */
16 metaonly interface ITimer_A inherits ITimer {
17
18 enum TASSEL_t {
19 TASSEL_0 = (0*0x100u), /*! TACLK */
20 TASSEL_1 = (1*0x100u), /*! ACLK */
21 TASSEL_2 = (2*0x100u), /*! SMCLK */
22 TASSEL_3 = 3*0x100u /*! INCLK */
23 };
24
25 enum TACLR_t {
26 TACLR_OFF = (0x0000), /* Timer A counter clear */
27 TACLR = 0x0004 /* Timer A counter clear */
28 };
29
30 enum TAIE_t {
31 TAIE_OFF = (0x0000), /* Timer A counter interrupt enable */
32 TAIE = 0x0002 /* Timer A counter interrupt enable */
33 };
34
35 enum TAIFG_t {
36 TAIFG_OFF = (0x000), /* Timer A counter interrupt flag */
37 TAIFG = (0x0001) /* Timer A counter interrupt flag */
38 };
39
40 enum MC_t {
41 MC_0 = (0*0x10u), /*! Stop Mode */
42 MC_1 = (1*0x10u), /*! Up Mode */
43 MC_2 = (2*0x10u), /*! Continuous Mode */
44 MC_3 = 3*0x10u /*! Up/Down Mode */
45 };
46
47 enum ID_t {
48 ID_0 = (0*0x40u), /*! Divider - /1 */
49 ID_1 = (1*0x40u), /*! Divider - /2 */
50 ID_2 = (2*0x40u), /*! Divider - /4 */
51 ID_3 = 3*0x40u /*! Divider - /8 */
52 };
53
54 enum CM_t {
55 CM_0 = (0*0x4000u), /*! No Capture */
56 CM_1 = (1*0x4000u), /*! Rising Edge */
57 CM_2 = (2*0x4000u), /*! Falling Edge */
58 CM_3 = 3*0x4000u /*! Both Edges */
59 };
60
61 enum CCIS_t {
62 CCIS_0 = (0*0x1000u), /*! CCIxA */
63 CCIS_1 = (1*0x1000u), /*! CCIxB */
64 CCIS_2 = (2*0x1000u), /*! GND */
65 CCIS_3 = 3*0x1000u /*! Vcc */
66 };
67
68 enum SCS_t {
69 SCS_OFF = (0x0000), /*! Asynchronous Capture */
70 SCS = 0x0800 /*! Sychronous Capture */
71 };
72
73 enum SCCI_t {
74 SCCI_OFF = (0x0000), /*! Latched capture signal (read) */
75 SCCI = 0x0400 /*! Latched capture signal (read) */
76 };
77
78 enum CAP_t {
79 CAP_OFF = (0x0000), /*! Compare mode */
80 CAP = 0x0100 /*! Capture mode */
81 };
82
83 enum CCIE_t {
84 CCIE_OFF = (0x0000), /* Capture/compare interrupt disable */
85 CCIE = (0x0010) /* Capture/compare interrupt enable */
86 };
87
88 enum CCI_t {
89 CCI_OFF = (0x0008), /* Capture input signal (read) */
90 CCI = (0x0008) /* Capture input signal (read) */
91 };
92
93 enum OUT_t {
94 OUT_OFF = (0x0000), /* PWM Output signal if output mode 0 */
95 OUT = (0x0004) /* PWM Output signal if output mode 0 */
96 };
97
98 enum COV_t {
99 COV_OFF = (0x0000), /* Capture/compare overflow flag */
100 COV = (0x0002) /* Capture/compare overflow flag */
101 };
102
103 enum CCIFG_t {
104 CCIFG_OFF = (0x0000), /* Capture/compare interrupt flag */
105 CCIFG = (0x0001) /* Capture/compare interrupt flag */
106 };
107
108 enum OUTMOD_t {
109 OUTMOD_0 = (0*0x20u), /*! PWM output mode: 0 - OUT bit value */
110 OUTMOD_1 = (1*0x20u), /*! PWM output mode: 1 - Set */
111 OUTMOD_2 = (2*0x20u), /*! PWM output mode: 2 - PWM toggle/reset */
112 OUTMOD_3 = (3*0x20u), /*! PWM output mode: 3 - PWM set/reset */
113 OUTMOD_4 = (4*0x20u), /*! PWM output mode: 4 - Toggle */
114 OUTMOD_5 = (5*0x20u), /*! PWM output mode: 5 - Reset */
115 OUTMOD_6 = (6*0x20u), /*! PWM output mode: 6 - PWM toggle/set */
116 OUTMOD_7 = 7*0x20u /*! PWM output mode: 7 - PWM reset/set */
117 };
118
119 /*! TA3IV Definitions */
120 enum IVValues {
121 TAIV_NONE = 0x0000, /*! No Interrupt pending */
122 TAIV_TACCR1 = 0x0002, /*! TACCR1_CCIFG */
123 TAIV_TACCR2 = 0x0004, /*! TACCR2_CCIFG */
124 TAIV_6 = 0x0006, /*! Reserved */
125 TAIV_8 = 0x0008, /*! Reserved */
126 TAIV_TAIFG = 0x000A /*! TAIFG */
127 };
128
129 /*!
130 * ======== TACTL_t ========
131 * Timer_A Control Register
132 *
133 * @see #TACTL_t
134 */
135 struct TACTL_t {
136 TASSEL_t TASSEL; /*! Timer_A clock source select
137 * 00 TACLK
138 * 01 ACLK
139 * 10 SMCLK
140 * 11 INCLK */
141 ID_t ID; /*! Input divider. These bits select the divider for the input clock.
142 * 00 /1
143 * 01 /2
144 * 10 /4
145 * 11 /8 */
146 MC_t MC; /*! Mode control. Setting MCx = 00h when Timer_A is not in use conserves
147 * power.
148 * 00 Stop mode: the timer is halted.
149 * 01 Up mode: the timer counts up to TACCR0.
150 * 10 Continuous mode: the timer counts up to 0FFFFh.
151 * 11 Up/down mode: the timer counts up to TACCR0 then down to 0000h. */
152 TACLR_t TACLR; /*! Timer_A clear. Setting this bit resets TAR, the clock divider, and the count
153 * direction. The TACLR bit is automatically reset and is always read as zero. */
154 TAIE_t TAIE; /*! Timer_A interrupt enable. This bit enables the TAIFG interrupt request.
155 * 0 Interrupt disabled
156 * 1 Interrupt enabled */
157 TAIFG_t TAIFG; /*! Timer_A interrupt flag
158 * 0 No interrupt pending
159 * 1 Interrupt pending */
160 }
161
162 /*!
163 * ======== TACCTLx_t ========
164 * Capture/Compare Control Register
165 *
166 * @see #TACCTLx_t
167 */
168 struct TACCTLx_t {
169 CM_t CM; /*! Capture mode
170 * 00 No capture
171 * 01 Capture on rising edge
172 * 10 Capture on falling edge
173 * 11 Capture on both rising and falling edges */
174 CCIS_t CCIS; /*! Capture/compare input select. These bits select the TACCRx input signal.
175 * See the device-specific data sheet for specific signal connections.
176 * 00 CCIxA
177 * 01 CCIxB
178 * 10 GND
179 * 11 VCC */
180 SCS_t SCS; /*! Synchronize capture source. This bit is used to synchronize the capture input
181 * signal with the timer clock.
182 * 0 Asynchronous capture
183 * 1 Synchronous capture */
184 SCCI_t SCCI; /*! Synchronized capture/compare input. The selected CCI input signal is
185 * latched with the EQUx signal and can be read via this bit */
186 CAP_t CAP; /*! Capture mode
187 * 0 Compare mode
188 * 1 Capture mode */
189 OUTMOD_t OUTMOD; /*! Output mode. Modes 2, 3, 6, and 7 are not useful for TACCR0 because
190 * EQUx = EQU0.
191 * 000 OUT bit value
192 * 001 Set
193 * 010 Toggle/reset
194 * 011 Set/reset
195 * 100 Toggle
196 * 101 Reset
197 * 110 Toggle/set
198 * 111 Reset/set */
199 CCIE_t CCIE; /*! Capture/compare interrupt enable. This bit enables the interrupt request of
200 * the corresponding CCIFG flag.
201 * 0 Interrupt disabled
202 * 1 Interrupt enabled */
203 CCI_t CCI; /*! Capture/compare input. The selected input signal can be read by this bit. */
204 OUT_t OUT; /*! Output. For output mode 0, this bit directly controls the state of the output.
205 * 0 Output low
206 * 1 Output high */
207 COV_t COV; /*! Capture overflow. This bit indicates a capture overflow occurred. COV must
208 * be reset with software.
209 * 0 No capture overflow occurred
210 * 1 Capture overflow occurred */
211 CCIFG_t CCIFG; /*! Capture/compare interrupt flag
212 * 0 No interrupt pending
213 * 1 Interrupt pending */
214 }
215
216 instance:
217 /*! Timer_A TACLK */
218 config float TACLK = 0;
219
220 /*! Timer_A INCLK */
221 config float INCLK = 0;
222 }