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12 /*!
13 * ======== IFlash ========
14 * MSP430 IFlash interface
15 */
16 metaonly interface IFlash inherits xdc.platform.IPeripheral {
17
18 enum FWKEY_t {
19 FWKEY_OFF = 0x00,
20 FWKEY = 0xA500
21 };
22
23 /*! Block write mode */
24 enum BLKWRT_t {
25 BLKWRT_OFF = (0x0000), /*! Block-write mode is off */
26 BLKWRT = 0x0080 /*! Block-write mode is on */
27 };
28
29 /*! Write */
30 enum WRT_t {
31 WRT_OFF = (0x0000), /*! Write mode is off */
32 WRT = 0x0040 /*! Write mode is on */
33 };
34
35 /*! Enable Emergency Interrupt Exit */
36 enum EEIEX_t {
37 EEIEX_OFF = (0x0000), /*! Exit interrupt disabled */
38 EEIEX = 0x0010 /*! Exit interrupt enabled */
39 };
40
41 /*! Enable Erase Interrupts */
42 enum EEI_t {
43 EEI_OFF = (0x0000), /*! Interrupts during segment erase disabled */
44 EEI = 0x0008 /*! Interrupts during segment erase enabled */
45 };
46
47 /*! Mass erase */
48 enum MERAS_t {
49 MERAS_OFF = (0x0000), /*! Mass erase disabled */
50 MERAS = 0x0004 /*! Mass erase enabled */
51 };
52
53 /*! Erase */
54 enum ERASE_t {
55 ERASE_OFF = (0x0000), /*! Erase disabled */
56 ERASE = 0x0002 /*! Erase enabled */
57 };
58
59 enum FSSEL_t {
60 FSSEL_0 = 0x0000, /*! ACLK */
61 FSSEL_1 = 0x0040, /*! MCLK */
62 FSSEL_2 = 0x0080 /*! SMCLK */
63 };
64
65 /*! Flash controller clock divider bit 0 */
66 enum FN0_t {
67 FN0_OFF = (0x0000), /*! Flash controller clock divider bit 0 */
68 FN0 = 0x0001 /*! Flash controller clock divider bit 0 */
69 };
70
71 /*! Flash controller clock divider bit 1 */
72 enum FN1_t {
73 FN1_OFF = (0x0000), /*! Flash controller clock divider bit 1 */
74 FN1 = 0x0002 /*! Flash controller clock divider bit 1 */
75 };
76
77 /*! Flash controller clock divider bit 2 */
78 enum FN2_t {
79 FN2_OFF = (0x0000), /*! Flash controller clock divider bit 2 */
80 FN2 = 0x0004 /*! Flash controller clock divider bit 2 */
81 };
82
83 /*! Flash controller clock divider bit 3 */
84 enum FN3_t {
85 FN3_OFF = (0x0000), /*! Flash controller clock divider bit 3 */
86 FN3 = 0x0008 /*! Flash controller clock divider bit 3 */
87 };
88
89 /*! Flash controller clock divider bit 4 */
90 enum FN4_t {
91 FN4_OFF = (0x0000), /*! Flash controller clock divider bit 4 */
92 FN4 = 0x0010 /*! Flash controller clock divider bit 4 */
93 };
94
95 /*! Flash controller clock divider bit 5 */
96 enum FN5_t {
97 FN5_OFF = (0x0000), /*! Flash controller clock divider bit 5 */
98 FN5 = 0x0020 /*! Flash controller clock divider bit 5 */
99 };
100
101 /*! Operation failure */
102 enum FAIL_t {
103 FAIL_OFF = (0x0000), /*! No failure */
104 FAIL = 0x0080 /*! Failure */
105 };
106
107 /*! SegmentA and Info lock */
108 enum LOCKA_t {
109 LOCKA_OFF = (0x0000), /*! Segment A unlocked and all information memory is erased during a mass erase */
110 LOCKA = 0x0040 /*! Segment A locked and all information memory is protected from erasure during a mass erase */
111 };
112
113 /*! Emergency exit */
114 enum EMEX_t {
115 EMEX_OFF = (0x0000), /*! No emergency exit */
116 EMEX = 0x0020 /*! Emergency exit */
117 };
118
119 /*! Lock */
120 enum LOCK_t {
121 LOCK_OFF = (0x0000), /*! Unlocked */
122 LOCK = 0x0010 /*! Locked */
123 };
124
125 /*! Wait */
126 enum WAIT_t {
127 WAIT_OFF = (0x0000), /*! The flash memory is not ready for the next byte/word write */
128 WAIT = 0x0008 /*! The flash memory is ready for the next byte/word write */
129 };
130
131 /*! Access violation interrupt flag */
132 enum ACCVIFG_t {
133 ACCVIFG_OFF = (0x0000), /*! No interrupt pending */
134 ACCVIFG = 0x0004 /*! Interrupt pending */
135 };
136
137 /*! Flash security key violation */
138 enum KEYV_t {
139 KEYV_OFF = (0x0000), /*! FCTLx password was written correctly */
140 KEYV = 0x0002 /*! FCTLx password was written incorrectly */
141 };
142
143 /*! Busy */
144 enum BUSY_t {
145 BUSY_OFF = (0x0000), /*! Not Busy */
146 BUSY = 0x0001 /*! Busy */
147 };
148
149 /*!
150 * ======== ForceSetDefaultRegister_t ========
151 * Force Set Default Register
152 *
153 * Type to store if each register needs to be forced initialized
154 * even if the register is in default state.
155 *
156 * @see #ForceSetDefaultRegister_t
157 */
158 struct ForceSetDefaultRegister_t {
159 String register;
160 Bool regForceSet;
161 }
162
163
164 instance:
165 /*! Max Flash Timing Generator Value from Datasheet */
166 config UInt8 uMaxFtg;
167
168 /*! Min Flash Timing Generator Value from Datasheet */
169 config UInt8 uMinFtg;
170
171 }