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12
13 /*!
14 * ======== IDAC ========
15 * MSP430 Digital to Analog Converter Interface
16 */
17 metaonly interface IDAC inherits xdc.platform.IPeripheral {
18
19
20 /*! DAC12OPS Bit */
21 enum DAC12OPS_t {
22 DAC12OPS_OFF = 0x0000,
23 DAC12OPS = 0x8000
24 };
25
26 /*! DAC12SREFx Bits */
27 enum DAC12SREF_t {
28 DAC12SREF_0 = (0*0x2000u),
29 DAC12SREF_1 = (1*0x2000u),
30 DAC12SREF_2 = (2*0x2000u),
31 DAC12SREF_3 = (3*0x2000u)
32 };
33
34 /*! DAC12RES Bit */
35 enum DAC12RES_t {
36 DAC12RES_OFF = 0x0000,
37 DAC12RES = 0x1000
38 };
39
40 /*! DAC12LSELx Bits */
41 enum DAC12LSEL_t {
42 DAC12LSEL_0 = (0*0x0400u),
43 DAC12LSEL_1 = (1*0x0400u),
44 DAC12LSEL_2 = (2*0x0400u),
45 DAC12LSEL_3 = (3*0x0400u)
46 };
47
48 /*! DAC12CALON Bit */
49 enum DAC12CALON_t {
50 DAC12CALON_OFF = 0x0000,
51 DAC12CALON = 0x0200
52 };
53
54 /*! DAC12IR Bit */
55 enum DAC12IR_t {
56 DAC12IR_OFF = 0x0000,
57 DAC12IR = 0x0100
58 };
59
60 /*! DAC12AMPx Bits */
61 enum DAC12AMP_t {
62 DAC12AMP_0 = (0*0x0020u),
63 DAC12AMP_1 = (1*0x0020u),
64 DAC12AMP_2 = (2*0x0020u),
65 DAC12AMP_3 = (3*0x0020u),
66 DAC12AMP_4 = (4*0x0020u),
67 DAC12AMP_5 = (5*0x0020u),
68 DAC12AMP_6 = (6*0x0020u),
69 DAC12AMP_7 = (7*0x0020u)
70 };
71
72 /*! DAC12DF Bit */
73 enum DAC12DF_t {
74 DAC12DF_OFF = 0x0000,
75 DAC12DF = 0x0010
76 };
77
78 /*! DAC12IE Bit */
79 enum DAC12IE_t {
80 DAC12IE_OFF = 0x0000,
81 DAC12IE = 0x0008
82 };
83
84 /*! DAC12IFG Bit */
85 enum DAC12IFG_t {
86 DAC12IFG_OFF = 0x0000,
87 DAC12IFG = 0x0004
88 };
89
90 /*! DAC12ENC Bit */
91 enum DAC12ENC_t {
92 DAC12ENC_OFF = 0x0000,
93 DAC12ENC = 0x0002
94 };
95
96 /*! DAC12GRP Bit */
97 enum DAC12GRP_t {
98 DAC12GRP_OFF = 0x0000,
99 DAC12GRP = 0x0001
100 };
101
102 /*!
103 * ======== ForceSetDefaultRegister_t ========
104 * Force Set Default Register
105 *
106 * Type to store if each register needs to be forced initialized
107 * even if the register is in default state.
108 *
109 * @see #ForceSetDefaultRegister_t
110 */
111 struct ForceSetDefaultRegister_t {
112 String register;
113 Bool regForceSet;
114 }
115
116 /*!
117 * ======== regIntVect_t ========
118 * Interrupt vector description
119 *
120 * Type to describe a single interrupt vector pin and all its possible
121 * configurations.
122 *
123 * @see #regIntVect_t
124 */
125 struct regIntVect_t {
126 String registerName;
127 String registerDescription;
128 String isrToggleString;
129 String priorityName;
130 Bool interruptEnable;
131 Bool interruptHandler;
132 Int priority;
133 }
134 instance:
135
136 }